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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 52# RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -run-pass=si-peephole-sdwa -o - %s | FileCheck %s3 4---5name: sdwa_opsel_hazard6body: |7 ; CHECK-LABEL: name: sdwa_opsel_hazard8 ; CHECK: bb.0:9 ; CHECK-NEXT: successors: %bb.7(0x40000000), %bb.8(0x40000000)10 ; CHECK-NEXT: liveins: $vgpr0, $sgpr4_sgpr5, $sgpr611 ; CHECK-NEXT: {{ $}}12 ; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF13 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:sreg_64_xexec_xnull = IMPLICIT_DEF14 ; CHECK-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF15 ; CHECK-NEXT: [[GLOBAL_LOAD_DWORD_SADDR:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR killed [[DEF1]], [[DEF2]], 0, 0, implicit $exec16 ; CHECK-NEXT: [[SI_IF:%[0-9]+]]:sreg_32 = SI_IF undef [[DEF]], %bb.8, implicit-def dead $exec, implicit-def dead $scc, implicit $exec17 ; CHECK-NEXT: S_BRANCH %bb.718 ; CHECK-NEXT: {{ $}}19 ; CHECK-NEXT: bb.1:20 ; CHECK-NEXT: successors: %bb.2(0x80000000)21 ; CHECK-NEXT: {{ $}}22 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 255, implicit $exec23 ; CHECK-NEXT: [[V_AND_B32_sdwa:%[0-9]+]]:vgpr_32 = V_AND_B32_sdwa 0, undef [[GLOBAL_LOAD_DWORD_SADDR]], 0, [[V_MOV_B32_e32_]], 0, 6, 0, 5, 6, implicit $exec24 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 2, implicit $exec25 ; CHECK-NEXT: [[V_LSHLREV_B32_sdwa:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_sdwa 0, [[V_MOV_B32_e32_1]], 0, undef [[GLOBAL_LOAD_DWORD_SADDR]], 0, 6, 0, 6, 2, implicit $exec26 ; CHECK-NEXT: {{ $}}27 ; CHECK-NEXT: bb.2:28 ; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.4(0x40000000)29 ; CHECK-NEXT: {{ $}}30 ; CHECK-NEXT: [[SI_IF1:%[0-9]+]]:sreg_32 = SI_IF killed undef %9, %bb.4, implicit-def dead $exec, implicit-def dead $scc, implicit $exec31 ; CHECK-NEXT: S_BRANCH %bb.332 ; CHECK-NEXT: {{ $}}33 ; CHECK-NEXT: bb.3:34 ; CHECK-NEXT: successors: %bb.4(0x80000000)35 ; CHECK-NEXT: {{ $}}36 ; CHECK-NEXT: bb.4:37 ; CHECK-NEXT: successors: %bb.5(0x40000000), %bb.6(0x40000000)38 ; CHECK-NEXT: {{ $}}39 ; CHECK-NEXT: [[SI_IF2:%[0-9]+]]:sreg_32 = SI_IF killed undef [[SI_IF1]], %bb.6, implicit-def dead $exec, implicit-def dead $scc, implicit $exec40 ; CHECK-NEXT: S_BRANCH %bb.541 ; CHECK-NEXT: {{ $}}42 ; CHECK-NEXT: bb.5:43 ; CHECK-NEXT: successors: %bb.6(0x80000000)44 ; CHECK-NEXT: {{ $}}45 ; CHECK-NEXT: bb.6:46 ; CHECK-NEXT: successors: %bb.9(0x40000000), %bb.10(0x40000000)47 ; CHECK-NEXT: {{ $}}48 ; CHECK-NEXT: [[SI_IF3:%[0-9]+]]:sreg_32 = SI_IF undef [[DEF]], %bb.10, implicit-def dead $exec, implicit-def dead $scc, implicit $exec49 ; CHECK-NEXT: S_BRANCH %bb.950 ; CHECK-NEXT: {{ $}}51 ; CHECK-NEXT: bb.7:52 ; CHECK-NEXT: successors: %bb.8(0x80000000)53 ; CHECK-NEXT: {{ $}}54 ; CHECK-NEXT: bb.8:55 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)56 ; CHECK-NEXT: {{ $}}57 ; CHECK-NEXT: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 16, undef [[GLOBAL_LOAD_DWORD_SADDR]], implicit $exec58 ; CHECK-NEXT: [[SI_IF4:%[0-9]+]]:sreg_32 = SI_IF killed undef [[SI_IF]], %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec59 ; CHECK-NEXT: S_BRANCH %bb.160 ; CHECK-NEXT: {{ $}}61 ; CHECK-NEXT: bb.9:62 ; CHECK-NEXT: successors: %bb.10(0x80000000)63 ; CHECK-NEXT: {{ $}}64 ; CHECK-NEXT: bb.10:65 ; CHECK-NEXT: S_ENDPGM 066 bb.0:67 successors: %bb.7(0x40000000), %bb.8(0x40000000)68 liveins: $vgpr0, $sgpr4_sgpr5, $sgpr669 70 %0:sreg_32 = IMPLICIT_DEF71 %1:sreg_64_xexec_xnull = IMPLICIT_DEF72 %2:vgpr_32 = IMPLICIT_DEF73 %3:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR killed %1, %2, 0, 0, implicit $exec74 %4:sreg_32 = SI_IF undef %0, %bb.8, implicit-def dead $exec, implicit-def dead $scc, implicit $exec75 S_BRANCH %bb.776 77 bb.1:78 successors: %bb.2(0x80000000)79 80 %5:vgpr_32 = V_AND_B32_e64 undef %6, 255, implicit $exec81 %7:vgpr_32 = V_LSHLREV_B32_e64 2, killed undef %5, implicit $exec82 83 bb.2:84 successors: %bb.3(0x40000000), %bb.4(0x40000000)85 86 %8:sreg_32 = SI_IF killed undef %9, %bb.4, implicit-def dead $exec, implicit-def dead $scc, implicit $exec87 S_BRANCH %bb.388 89 bb.3:90 successors: %bb.4(0x80000000)91 92 bb.4:93 successors: %bb.5(0x40000000), %bb.6(0x40000000)94 95 %10:sreg_32 = SI_IF killed undef %8, %bb.6, implicit-def dead $exec, implicit-def dead $scc, implicit $exec96 S_BRANCH %bb.597 98 bb.5:99 successors: %bb.6(0x80000000)100 101 bb.6:102 successors: %bb.9(0x40000000), %bb.10(0x40000000)103 104 %11:sreg_32 = SI_IF undef %0, %bb.10, implicit-def dead $exec, implicit-def dead $scc, implicit $exec105 S_BRANCH %bb.9106 107 bb.7:108 successors: %bb.8(0x80000000)109 110 bb.8:111 successors: %bb.1(0x40000000), %bb.2(0x40000000)112 113 %6:vgpr_32 = V_LSHRREV_B32_e64 16, undef %3, implicit $exec114 %9:sreg_32 = SI_IF killed undef %4, %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec115 S_BRANCH %bb.1116 117 bb.9:118 successors: %bb.10(0x80000000)119 120 bb.10:121 S_ENDPGM 0122 123...124 125