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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 42# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=si-peephole-sdwa -verify-machineinstrs -o - %s | FileCheck -check-prefix=SDWA %s3# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=si-peephole-sdwa -verify-machineinstrs -o - %s | FileCheck -check-prefix=SDWA %s4# RUN: llc -mtriple=amdgcn -mcpu=fiji -passes=si-peephole-sdwa -o - %s | FileCheck -check-prefix=SDWA %s5# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -passes=si-peephole-sdwa -o - %s | FileCheck -check-prefix=SDWA %s6---7name: add_f16_u32_preserve8tracksRegLiveness: true9registers:10 - { id: 0, class: vreg_64 }11 - { id: 1, class: vreg_64 }12 - { id: 2, class: sreg_64 }13 - { id: 3, class: vgpr_32 }14 - { id: 4, class: vgpr_32 }15 - { id: 5, class: vgpr_32 }16 - { id: 6, class: vgpr_32 }17 - { id: 7, class: vgpr_32 }18 - { id: 8, class: vgpr_32 }19 - { id: 9, class: vgpr_32 }20 - { id: 10, class: vgpr_32 }21 - { id: 11, class: vgpr_32 }22 - { id: 12, class: vgpr_32 }23 - { id: 13, class: vgpr_32 }24body: |25 bb.0:26 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $sgpr30_sgpr3127 28 ; SDWA-LABEL: name: add_f16_u32_preserve29 ; SDWA: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $sgpr30_sgpr3130 ; SDWA-NEXT: {{ $}}31 ; SDWA-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr30_sgpr3132 ; SDWA-NEXT: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr333 ; SDWA-NEXT: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr134 ; SDWA-NEXT: [[FLAT_LOAD_DWORD:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[COPY2]], 0, 0, implicit $exec, implicit $flat_scr :: (load (s32))35 ; SDWA-NEXT: [[FLAT_LOAD_DWORD1:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[COPY1]], 0, 0, implicit $exec, implicit $flat_scr :: (load (s32))36 ; SDWA-NEXT: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 65535, [[FLAT_LOAD_DWORD]], implicit $exec37 ; SDWA-NEXT: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 16, [[FLAT_LOAD_DWORD1]], implicit $exec38 ; SDWA-NEXT: [[V_BFE_U32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_U32_e64 [[FLAT_LOAD_DWORD]], 8, 8, implicit $exec39 ; SDWA-NEXT: [[V_LSHRREV_B32_e32_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e32 24, [[FLAT_LOAD_DWORD1]], implicit $exec40 ; SDWA-NEXT: [[V_MUL_F32_sdwa:%[0-9]+]]:vgpr_32 = V_MUL_F32_sdwa 0, [[FLAT_LOAD_DWORD]], 0, [[FLAT_LOAD_DWORD1]], 0, 0, 5, 0, 1, 3, implicit $mode, implicit $exec41 ; SDWA-NEXT: [[V_ADD_F16_sdwa:%[0-9]+]]:vgpr_32 = V_ADD_F16_sdwa 0, [[FLAT_LOAD_DWORD]], 0, [[FLAT_LOAD_DWORD1]], 0, 0, 1, 2, 4, 5, implicit $mode, implicit $exec, implicit [[V_MUL_F32_sdwa]](tied-def 0)42 ; SDWA-NEXT: FLAT_STORE_DWORD [[COPY2]], [[V_ADD_F16_sdwa]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s32))43 ; SDWA-NEXT: $sgpr30_sgpr31 = COPY [[COPY]]44 ; SDWA-NEXT: S_SETPC_B64_return $sgpr30_sgpr3145 %2 = COPY $sgpr30_sgpr3146 %1 = COPY $vgpr2_vgpr347 %0 = COPY $vgpr0_vgpr148 %3 = FLAT_LOAD_DWORD %0, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32))49 %4 = FLAT_LOAD_DWORD %1, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32))50 51 %5 = V_AND_B32_e32 65535, %3, implicit $exec52 %6 = V_LSHRREV_B32_e64 16, %4, implicit $exec53 %7 = V_BFE_U32_e64 %3, 8, 8, implicit $exec54 %8 = V_LSHRREV_B32_e32 24, %4, implicit $exec55 56 %9 = V_ADD_F16_e64 0, %5, 0, %6, 0, 0, implicit $mode, implicit $exec57 %10 = V_LSHLREV_B16_e64 8, %9, implicit $exec58 %11 = V_MUL_F32_e64 0, %7, 0, %8, 0, 0, implicit $mode, implicit $exec59 %12 = V_LSHLREV_B32_e64 16, %11, implicit $exec60 61 %13 = V_OR_B32_e64 %10, %12, implicit $exec62 63 FLAT_STORE_DWORD %0, %13, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32))64 $sgpr30_sgpr31 = COPY %265 S_SETPC_B64_return $sgpr30_sgpr3166...67---68name: sdwa_preserve_keep69tracksRegLiveness: true70registers:71 - { id: 0, class: vreg_64 }72 - { id: 1, class: vreg_64 }73 - { id: 2, class: sreg_64 }74 - { id: 3, class: vgpr_32 }75 - { id: 4, class: vgpr_32 }76 - { id: 5, class: sreg_32_xm0_xexec }77 - { id: 6, class: vgpr_32 }78 - { id: 7, class: vgpr_32 }79 - { id: 8, class: sreg_32_xm0 }80 - { id: 9, class: vgpr_32 }81 - { id: 10, class: sreg_32_xm0 }82 - { id: 11, class: vgpr_32 }83 - { id: 17, class: vgpr_32 }84body: |85 bb.0:86 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $sgpr30_sgpr3187 88 ; SDWA-LABEL: name: sdwa_preserve_keep89 ; SDWA: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $sgpr30_sgpr3190 ; SDWA-NEXT: {{ $}}91 ; SDWA-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr30_sgpr3192 ; SDWA-NEXT: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr393 ; SDWA-NEXT: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr194 ; SDWA-NEXT: [[FLAT_LOAD_DWORD:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[COPY2]], 0, 0, implicit $exec, implicit $flat_scr :: (load (s32))95 ; SDWA-NEXT: [[FLAT_LOAD_DWORD1:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[COPY1]], 0, 0, implicit $exec, implicit $flat_scr :: (load (s32))96 ; SDWA-NEXT: [[V_LSHRREV_B16_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B16_e64 8, [[FLAT_LOAD_DWORD]], implicit $exec97 ; SDWA-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 25598 ; SDWA-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[FLAT_LOAD_DWORD]], killed [[S_MOV_B32_]], implicit $exec99 ; SDWA-NEXT: [[V_MOV_B32_sdwa:%[0-9]+]]:vgpr_32 = V_MOV_B32_sdwa 0, [[FLAT_LOAD_DWORD1]], 0, 5, 2, 4, implicit $exec, implicit [[V_AND_B32_e64_]](tied-def 0)100 ; SDWA-NEXT: FLAT_STORE_DWORD [[COPY2]], [[V_MOV_B32_sdwa]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s32))101 ; SDWA-NEXT: S_ENDPGM 0102 %2 = COPY $sgpr30_sgpr31103 %1 = COPY $vgpr2_vgpr3104 %0 = COPY $vgpr0_vgpr1105 %3 = FLAT_LOAD_DWORD %0, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32))106 %4 = FLAT_LOAD_DWORD %1, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32))107 108 %9:vgpr_32 = V_LSHRREV_B16_e64 8, %3, implicit $exec109 %10:sreg_32_xm0 = S_MOV_B32 255110 %11:vgpr_32 = V_AND_B32_e64 %3, killed %10, implicit $exec111 %17:vgpr_32 = V_MOV_B32_sdwa 0, %4, 0, 5, 2, 4, implicit $exec, implicit %11(tied-def 0)112 FLAT_STORE_DWORD %0, %17, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32))113 S_ENDPGM 0114 115...116---117name: sdwa_preserve_remove118tracksRegLiveness: true119registers:120 - { id: 0, class: vreg_64 }121 - { id: 1, class: vreg_64 }122 - { id: 2, class: sreg_64 }123 - { id: 3, class: vgpr_32 }124 - { id: 4, class: vgpr_32 }125 - { id: 5, class: sreg_32_xm0_xexec }126 - { id: 6, class: vgpr_32 }127 - { id: 7, class: vgpr_32 }128 - { id: 8, class: sreg_32_xm0 }129 - { id: 9, class: vgpr_32 }130 - { id: 10, class: sreg_32_xm0 }131 - { id: 11, class: vgpr_32 }132 - { id: 17, class: vgpr_32 }133body: |134 bb.0:135 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $sgpr30_sgpr31136 137 ; SDWA-LABEL: name: sdwa_preserve_remove138 ; SDWA: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $sgpr30_sgpr31139 ; SDWA-NEXT: {{ $}}140 ; SDWA-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr30_sgpr31141 ; SDWA-NEXT: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3142 ; SDWA-NEXT: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1143 ; SDWA-NEXT: [[FLAT_LOAD_DWORD:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[COPY2]], 0, 0, implicit $exec, implicit $flat_scr :: (load (s32))144 ; SDWA-NEXT: [[FLAT_LOAD_DWORD1:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[COPY1]], 0, 0, implicit $exec, implicit $flat_scr :: (load (s32))145 ; SDWA-NEXT: [[V_LSHRREV_B16_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B16_e64 8, [[FLAT_LOAD_DWORD]], implicit $exec146 ; SDWA-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 65535147 ; SDWA-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[FLAT_LOAD_DWORD]], killed [[S_MOV_B32_]], implicit $exec148 ; SDWA-NEXT: [[V_MOV_B32_sdwa:%[0-9]+]]:vgpr_32 = V_MOV_B32_sdwa 0, [[FLAT_LOAD_DWORD1]], 0, 5, 2, 4, implicit $exec, implicit [[FLAT_LOAD_DWORD]](tied-def 0)149 ; SDWA-NEXT: FLAT_STORE_DWORD [[COPY2]], [[V_MOV_B32_sdwa]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s32))150 ; SDWA-NEXT: S_ENDPGM 0151 %2 = COPY $sgpr30_sgpr31152 %1 = COPY $vgpr2_vgpr3153 %0 = COPY $vgpr0_vgpr1154 %3 = FLAT_LOAD_DWORD %0, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32))155 %4 = FLAT_LOAD_DWORD %1, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32))156 157 %9:vgpr_32 = V_LSHRREV_B16_e64 8, %3, implicit $exec158 %10:sreg_32_xm0 = S_MOV_B32 65535159 %11:vgpr_32 = V_AND_B32_e64 %3, killed %10, implicit $exec160 %17:vgpr_32 = V_MOV_B32_sdwa 0, %4, 0, 5, 2, 4, implicit $exec, implicit %11(tied-def 0)161 FLAT_STORE_DWORD %0, %17, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32))162 S_ENDPGM 0163 164...165---166name: add_f16_u32_preserve_different_bb167tracksRegLiveness: true168body: |169 ; SDWA-LABEL: name: add_f16_u32_preserve_different_bb170 ; SDWA: bb.0:171 ; SDWA-NEXT: successors: %bb.1(0x80000000)172 ; SDWA-NEXT: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $sgpr30_sgpr31173 ; SDWA-NEXT: {{ $}}174 ; SDWA-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr30_sgpr31175 ; SDWA-NEXT: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3176 ; SDWA-NEXT: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1177 ; SDWA-NEXT: [[FLAT_LOAD_DWORD:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[COPY2]], 0, 0, implicit $exec, implicit $flat_scr :: (load (s32))178 ; SDWA-NEXT: [[FLAT_LOAD_DWORD1:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[COPY1]], 0, 0, implicit $exec, implicit $flat_scr :: (load (s32))179 ; SDWA-NEXT: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 65535, [[FLAT_LOAD_DWORD]], implicit $exec180 ; SDWA-NEXT: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 16, [[FLAT_LOAD_DWORD1]], implicit $exec181 ; SDWA-NEXT: [[V_BFE_U32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_U32_e64 [[FLAT_LOAD_DWORD]], 8, 8, implicit $exec182 ; SDWA-NEXT: [[V_LSHRREV_B32_e32_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e32 24, [[FLAT_LOAD_DWORD1]], implicit $exec183 ; SDWA-NEXT: {{ $}}184 ; SDWA-NEXT: bb.1:185 ; SDWA-NEXT: successors: %bb.2(0x80000000)186 ; SDWA-NEXT: {{ $}}187 ; SDWA-NEXT: [[V_MUL_F32_sdwa:%[0-9]+]]:vgpr_32 = V_MUL_F32_sdwa 0, [[FLAT_LOAD_DWORD]], 0, [[FLAT_LOAD_DWORD1]], 0, 0, 5, 0, 1, 3, implicit $mode, implicit $exec188 ; SDWA-NEXT: {{ $}}189 ; SDWA-NEXT: bb.2:190 ; SDWA-NEXT: [[V_ADD_F16_sdwa:%[0-9]+]]:vgpr_32 = V_ADD_F16_sdwa 0, [[FLAT_LOAD_DWORD]], 0, [[FLAT_LOAD_DWORD1]], 0, 0, 1, 2, 4, 5, implicit $mode, implicit $exec, implicit [[V_MUL_F32_sdwa]](tied-def 0)191 ; SDWA-NEXT: FLAT_STORE_DWORD [[COPY2]], [[V_ADD_F16_sdwa]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s32))192 ; SDWA-NEXT: $sgpr30_sgpr31 = COPY [[COPY]]193 ; SDWA-NEXT: S_SETPC_B64_return $sgpr30_sgpr31194 bb.0:195 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $sgpr30_sgpr31196 197 %2:sreg_64 = COPY $sgpr30_sgpr31198 %1:vreg_64 = COPY $vgpr2_vgpr3199 %0:vreg_64 = COPY $vgpr0_vgpr1200 %3:vgpr_32 = FLAT_LOAD_DWORD %0, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32))201 %4:vgpr_32 = FLAT_LOAD_DWORD %1, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32))202 203 %5:vgpr_32 = V_AND_B32_e32 65535, %3, implicit $exec204 %6:vgpr_32 = V_LSHRREV_B32_e64 16, %4, implicit $exec205 %7:vgpr_32 = V_BFE_U32_e64 %3, 8, 8, implicit $exec206 %8:vgpr_32 = V_LSHRREV_B32_e32 24, %4, implicit $exec207 208 %9:vgpr_32 = V_ADD_F16_e64 0, %5, 0, %6, 0, 0, implicit $mode, implicit $exec209 %10:vgpr_32 = V_LSHLREV_B16_e64 8, %9, implicit $exec210 211 bb.1:212 %11:vgpr_32 = V_MUL_F32_e64 0, %7, 0, %8, 0, 0, implicit $mode, implicit $exec213 %12:vgpr_32 = V_LSHLREV_B32_e64 16, %11, implicit $exec214 215 bb.2:216 %13:vgpr_32 = V_OR_B32_e64 %10, %12, implicit $exec217 218 FLAT_STORE_DWORD %0, %13, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32))219 $sgpr30_sgpr31 = COPY %2220 S_SETPC_B64_return $sgpr30_sgpr31221...222 223# Should not add kill flag to reused ops in SDWAInst224 225---226name: multiuse_kill227tracksRegLiveness: true228 229body: |230 bb.0:231 ; SDWA-LABEL: name: multiuse_kill232 ; SDWA: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF233 ; SDWA-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF234 ; SDWA-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF235 ; SDWA-NEXT: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 16, killed [[DEF]], implicit $exec236 ; SDWA-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 65535237 ; SDWA-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 killed [[S_MOV_B32_]], [[DEF1]], implicit $exec238 ; SDWA-NEXT: [[V_OR_B32_sdwa:%[0-9]+]]:vgpr_32 = V_OR_B32_sdwa 0, [[DEF1]], 0, [[V_LSHLREV_B32_e64_]], 0, 6, 0, 4, 6, implicit $exec239 ; SDWA-NEXT: [[V_LSHLREV_B32_e64_1:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 16, killed [[DEF2]], implicit $exec240 ; SDWA-NEXT: [[V_OR_B32_sdwa1:%[0-9]+]]:vgpr_32 = V_OR_B32_sdwa 0, [[DEF1]], 0, [[V_LSHLREV_B32_e64_1]], 0, 6, 0, 4, 6, implicit $exec241 ; SDWA-NEXT: S_ENDPGM 0242 %0:vgpr_32 = IMPLICIT_DEF243 %1:vgpr_32 = IMPLICIT_DEF244 %2:vgpr_32 = IMPLICIT_DEF245 %3:vgpr_32 = V_LSHLREV_B32_e64 16, killed %0, implicit $exec246 %4:sreg_32 = S_MOV_B32 65535247 %5:vgpr_32 = V_AND_B32_e64 killed %4, killed %1, implicit $exec248 %6:vgpr_32 = V_OR_B32_e64 %5, killed %3, implicit $exec249 %7:vgpr_32 = V_LSHLREV_B32_e64 16, killed %2, implicit $exec250 %8:vgpr_32 = V_OR_B32_e64 %5, killed %7, implicit $exec251 252 S_ENDPGM 0253 254...255