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1# RUN: llc -mtriple=amdgcn -mcpu=fiji -start-before si-peephole-sdwa -o - %s | FileCheck -check-prefix=VI -check-prefix=GCN %s2# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -start-before si-peephole-sdwa -o - %s | FileCheck -check-prefix=GFX9 -check-prefix=GCN %s3 4# GCN-LABEL: {{^}}sdwa_imm_operand:5# GCN: v_mov_b32_e32 v[[SHIFT:[0-9]+]], 26# GCN-NOT: v_mov_b32_e32 v{{[0-9]+}}, 27# GCN: BB0_1:8# GCN: v_lshlrev_b32_sdwa v{{[0-9]+}}, v[[SHIFT]], v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_19# GCN: v_lshlrev_b32_sdwa v{{[0-9]+}}, v[[SHIFT]], v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_110 11# GCN-LABEL: {{^}}sdwa_sgpr_operand:12# VI: v_mov_b32_e32 v[[SHIFT:[0-9]+]], 213# VI-NOT: v_mov_b32_e32 v{{[0-9]+}}, 214# VI: BB1_1:15# VI: v_lshlrev_b32_sdwa v{{[0-9]+}}, v[[SHIFT]], v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_116# VI: v_lshlrev_b32_sdwa v{{[0-9]+}}, v[[SHIFT]], v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_117 18# GFX9: s_mov_b32 s[[SHIFT:[0-9]+]], 219# GFX9-NOT: v_mov_b32_e32 v{{[0-9]+}}, 220# GFX9: BB1_1:21# GFX9: v_lshlrev_b32_sdwa v{{[0-9]+}}, s[[SHIFT]], v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_122# GFX9: v_lshlrev_b32_sdwa v{{[0-9]+}}, s[[SHIFT]], v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_123 24--- |25 ; ModuleID = 'sdwa-scalar-ops.opt.ll'26 source_filename = "sdwa-scalar-ops.opt.ll"27 28 define amdgpu_kernel void @sdwa_imm_operand(ptr addrspace(1) nocapture %arg) {29 bb:30 br label %bb231 32 bb1: ; preds = %bb233 ret void34 35 bb2: ; preds = %bb2, %bb36 %lsr.iv = phi i64 [ %lsr.iv.next, %bb2 ], [ 0, %bb ]37 %bc = bitcast ptr addrspace(1) %arg to ptr addrspace(1)38 %uglygep4 = getelementptr i8, ptr addrspace(1) %bc, i64 %lsr.iv39 %uglygep45 = bitcast ptr addrspace(1) %uglygep4 to ptr addrspace(1)40 %tmp5 = load i32, ptr addrspace(1) %uglygep45, align 441 %tmp6 = lshr i32 %tmp5, 842 %tmp7 = and i32 %tmp6, 25543 %tmp8 = zext i32 %tmp7 to i6444 %tmp9 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 %tmp845 store i32 1, ptr addrspace(1) %tmp9, align 446 %scevgep = getelementptr i32, ptr addrspace(1) %uglygep45, i64 147 %tmp13 = load i32, ptr addrspace(1) %scevgep, align 448 %tmp14 = lshr i32 %tmp13, 849 %tmp15 = and i32 %tmp14, 25550 %tmp16 = zext i32 %tmp15 to i6451 %tmp17 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 %tmp1652 store i32 1, ptr addrspace(1) %tmp17, align 453 %lsr.iv.next = add nuw nsw i64 %lsr.iv, 854 %tmp1 = trunc i64 %lsr.iv.next to i3255 %tmp19 = icmp eq i32 %tmp1, 409656 br i1 %tmp19, label %bb1, label %bb257 }58 59 define amdgpu_kernel void @sdwa_sgpr_operand(ptr addrspace(1) nocapture %arg) {60 bb:61 br label %bb262 63 bb1: ; preds = %bb264 ret void65 66 bb2: ; preds = %bb2, %bb67 %lsr.iv = phi i64 [ %lsr.iv.next, %bb2 ], [ 0, %bb ]68 %bc = bitcast ptr addrspace(1) %arg to ptr addrspace(1)69 %uglygep4 = getelementptr i8, ptr addrspace(1) %bc, i64 %lsr.iv70 %uglygep45 = bitcast ptr addrspace(1) %uglygep4 to ptr addrspace(1)71 %tmp5 = load i32, ptr addrspace(1) %uglygep45, align 472 %tmp6 = lshr i32 %tmp5, 873 %tmp7 = and i32 %tmp6, 25574 %tmp8 = zext i32 %tmp7 to i6475 %tmp9 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 %tmp876 store i32 1, ptr addrspace(1) %tmp9, align 477 %scevgep = getelementptr i32, ptr addrspace(1) %uglygep45, i64 178 %tmp13 = load i32, ptr addrspace(1) %scevgep, align 479 %tmp14 = lshr i32 %tmp13, 880 %tmp15 = and i32 %tmp14, 25581 %tmp16 = zext i32 %tmp15 to i6482 %tmp17 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 %tmp1683 store i32 1, ptr addrspace(1) %tmp17, align 484 %lsr.iv.next = add nuw nsw i64 %lsr.iv, 885 %tmp1 = trunc i64 %lsr.iv.next to i3286 %tmp19 = icmp eq i32 %tmp1, 409687 br i1 %tmp19, label %bb1, label %bb288 }89 90...91---92name: sdwa_imm_operand93alignment: 194exposesReturnsTwice: false95legalized: false96regBankSelected: false97selected: false98tracksRegLiveness: true99registers:100 - { id: 0, class: sreg_64 }101 - { id: 1, class: sreg_64 }102 - { id: 2, class: vgpr_32 }103 - { id: 3, class: sgpr_128 }104 - { id: 4, class: sgpr_64 }105 - { id: 5, class: sreg_32_xm0 }106 - { id: 6, class: sgpr_32 }107 - { id: 7, class: sreg_64 }108 - { id: 8, class: sreg_64 }109 - { id: 9, class: sreg_64_xexec }110 - { id: 10, class: sreg_32_xm0 }111 - { id: 11, class: sreg_32_xm0 }112 - { id: 12, class: sreg_32_xm0 }113 - { id: 13, class: sreg_32_xm0 }114 - { id: 14, class: sreg_32_xm0 }115 - { id: 15, class: sreg_32_xm0 }116 - { id: 16, class: sreg_64 }117 - { id: 17, class: vgpr_32 }118 - { id: 18, class: vreg_64 }119 - { id: 19, class: sreg_32_xm0 }120 - { id: 20, class: sreg_32 }121 - { id: 21, class: sreg_32_xm0 }122 - { id: 22, class: sreg_32_xm0 }123 - { id: 23, class: sreg_32_xm0 }124 - { id: 24, class: sreg_64 }125 - { id: 25, class: sreg_32_xm0 }126 - { id: 26, class: sreg_32_xm0 }127 - { id: 27, class: sreg_32_xm0 }128 - { id: 28, class: sreg_32_xm0 }129 - { id: 29, class: sreg_64 }130 - { id: 30, class: vgpr_32 }131 - { id: 31, class: vreg_64 }132 - { id: 32, class: sreg_32_xm0 }133 - { id: 33, class: sreg_32_xm0 }134 - { id: 34, class: sreg_64 }135 - { id: 35, class: sreg_32_xm0 }136 - { id: 36, class: sreg_32_xm0 }137 - { id: 37, class: sreg_32_xm0 }138 - { id: 38, class: sreg_32_xm0 }139 - { id: 39, class: vreg_64 }140 - { id: 40, class: vgpr_32 }141 - { id: 41, class: vreg_64 }142 - { id: 42, class: sreg_32_xm0 }143 - { id: 43, class: sreg_32 }144 - { id: 44, class: sreg_32_xm0 }145 - { id: 45, class: sreg_64 }146 - { id: 46, class: sreg_32_xm0 }147 - { id: 47, class: sreg_32_xm0 }148 - { id: 48, class: sreg_32_xm0 }149 - { id: 49, class: sreg_32_xm0 }150 - { id: 50, class: sreg_64 }151 - { id: 51, class: vreg_64 }152 - { id: 52, class: sreg_64 }153 - { id: 53, class: sreg_32_xm0 }154 - { id: 54, class: sreg_32_xm0 }155 - { id: 55, class: sreg_32_xm0 }156 - { id: 56, class: sreg_32_xm0 }157 - { id: 57, class: sreg_64 }158 - { id: 58, class: sreg_32_xm0 }159 - { id: 59, class: sreg_32_xm0 }160 - { id: 60, class: vgpr_32 }161 - { id: 61, class: vgpr_32 }162 - { id: 62, class: vreg_64 }163 - { id: 63, class: vgpr_32 }164 - { id: 64, class: vgpr_32 }165 - { id: 65, class: vgpr_32 }166 - { id: 66, class: vgpr_32 }167 - { id: 67, class: vreg_64 }168 - { id: 68, class: vgpr_32 }169 - { id: 69, class: vgpr_32 }170 - { id: 70, class: vgpr_32 }171 - { id: 71, class: vgpr_32 }172 - { id: 72, class: vgpr_32 }173 - { id: 73, class: vgpr_32 }174 - { id: 74, class: vgpr_32 }175 - { id: 75, class: vreg_64 }176 - { id: 76, class: vgpr_32 }177 - { id: 77, class: vgpr_32 }178 - { id: 78, class: vgpr_32 }179 - { id: 79, class: vgpr_32 }180 - { id: 80, class: vreg_64 }181 - { id: 81, class: vgpr_32 }182 - { id: 82, class: vgpr_32 }183 - { id: 83, class: vgpr_32 }184liveins:185 - { reg: '$sgpr4_sgpr5', virtual-reg: '%4' }186frameInfo:187 isFrameAddressTaken: false188 isReturnAddressTaken: false189 hasStackMap: false190 hasPatchPoint: false191 stackSize: 0192 offsetAdjustment: 0193 maxAlignment: 0194 adjustsStack: false195 hasCalls: false196 hasOpaqueSPAdjustment: false197 hasVAStart: false198 hasMustTailInVarArgFunc: false199body: |200 bb.0.bb:201 successors: %bb.2.bb2(0x80000000)202 liveins: $sgpr4_sgpr5203 204 %4 = COPY $sgpr4_sgpr5205 %9 = S_LOAD_DWORDX2_IMM %4, 0, 0 :: (non-temporal dereferenceable invariant load (s64) from `ptr addrspace(4) poison`)206 %8 = S_MOV_B64 0207 %7 = COPY %9208 %30 = V_MOV_B32_e32 1, implicit $exec209 S_BRANCH %bb.2.bb2210 211 bb.1.bb1:212 S_ENDPGM 0213 214 bb.2.bb2:215 successors: %bb.1.bb1(0x04000000), %bb.2.bb2(0x7c000000)216 217 %0 = PHI %8, %bb.0.bb, %1, %bb.2.bb2218 %13 = COPY %7.sub1219 %14 = S_ADD_U32 %7.sub0, %0.sub0, implicit-def $scc220 %15 = S_ADDC_U32 %7.sub1, %0.sub1, implicit-def dead $scc, implicit $scc221 %16 = REG_SEQUENCE %14, %subreg.sub0, %15, %subreg.sub1222 %18 = COPY %16223 %17 = FLAT_LOAD_DWORD %18, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %ir.uglygep45)224 %60 = V_BFE_U32_e64 %17, 8, 8, implicit $exec225 %61 = V_LSHLREV_B32_e32 2, killed %60, implicit $exec226 %70 = V_ADD_CO_U32_e32 %7.sub0, %61, implicit-def $vcc, implicit $exec227 %66 = COPY %13228 %65 = V_ADDC_U32_e32 0, %66, implicit-def $vcc, implicit $vcc, implicit $exec229 %67 = REG_SEQUENCE %70, %subreg.sub0, killed %65, %subreg.sub1230 FLAT_STORE_DWORD %67, %30, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %ir.tmp9)231 %37 = S_ADD_U32 %14, 4, implicit-def $scc232 %38 = S_ADDC_U32 %15, 0, implicit-def dead $scc, implicit $scc233 %71 = COPY killed %37234 %72 = COPY killed %38235 %41 = REG_SEQUENCE killed %71, %subreg.sub0, killed %72, %subreg.sub1236 %40 = FLAT_LOAD_DWORD killed %41, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %ir.scevgep)237 %73 = V_BFE_U32_e64 %40, 8, 8, implicit $exec238 %74 = V_LSHLREV_B32_e32 2, killed %73, implicit $exec239 %83 = V_ADD_CO_U32_e32 %7.sub0, %74, implicit-def $vcc, implicit $exec240 %78 = V_ADDC_U32_e32 0, %66, implicit-def $vcc, implicit $vcc, implicit $exec241 %80 = REG_SEQUENCE %83, %subreg.sub0, killed %78, %subreg.sub1242 FLAT_STORE_DWORD %80, %30, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %ir.tmp17)243 %55 = S_ADD_U32 %0.sub0, 8, implicit-def $scc244 %56 = S_ADDC_U32 %0.sub1, 0, implicit-def dead $scc, implicit $scc245 %57 = REG_SEQUENCE %55, %subreg.sub0, killed %56, %subreg.sub1246 %1 = COPY %57247 S_CMPK_EQ_I32 %55, 4096, implicit-def $scc248 S_CBRANCH_SCC1 %bb.1.bb1, implicit $scc249 S_BRANCH %bb.2.bb2250 251...252---253name: sdwa_sgpr_operand254alignment: 1255exposesReturnsTwice: false256legalized: false257regBankSelected: false258selected: false259tracksRegLiveness: true260registers:261 - { id: 0, class: sreg_64 }262 - { id: 1, class: sreg_64 }263 - { id: 2, class: vgpr_32 }264 - { id: 3, class: sgpr_128 }265 - { id: 4, class: sgpr_64 }266 - { id: 5, class: sreg_32_xm0 }267 - { id: 6, class: sgpr_32 }268 - { id: 7, class: sreg_64 }269 - { id: 8, class: sreg_64 }270 - { id: 9, class: sreg_64_xexec }271 - { id: 10, class: sreg_32_xm0 }272 - { id: 11, class: sreg_32_xm0 }273 - { id: 12, class: sreg_32_xm0 }274 - { id: 13, class: sreg_32_xm0 }275 - { id: 14, class: sreg_32_xm0 }276 - { id: 15, class: sreg_32_xm0 }277 - { id: 16, class: sreg_64 }278 - { id: 17, class: vgpr_32 }279 - { id: 18, class: vreg_64 }280 - { id: 19, class: sreg_32_xm0 }281 - { id: 20, class: sreg_32 }282 - { id: 21, class: sreg_32_xm0 }283 - { id: 22, class: sreg_32_xm0 }284 - { id: 23, class: sreg_32_xm0 }285 - { id: 24, class: sreg_64 }286 - { id: 25, class: sreg_32_xm0 }287 - { id: 26, class: sreg_32_xm0 }288 - { id: 27, class: sreg_32_xm0 }289 - { id: 28, class: sreg_32_xm0 }290 - { id: 29, class: sreg_64 }291 - { id: 30, class: vgpr_32 }292 - { id: 31, class: vreg_64 }293 - { id: 32, class: sreg_32_xm0 }294 - { id: 33, class: sreg_32_xm0 }295 - { id: 34, class: sreg_64 }296 - { id: 35, class: sreg_32_xm0 }297 - { id: 36, class: sreg_32_xm0 }298 - { id: 37, class: sreg_32_xm0 }299 - { id: 38, class: sreg_32_xm0 }300 - { id: 39, class: vreg_64 }301 - { id: 40, class: vgpr_32 }302 - { id: 41, class: vreg_64 }303 - { id: 42, class: sreg_32_xm0 }304 - { id: 43, class: sreg_32 }305 - { id: 44, class: sreg_32_xm0 }306 - { id: 45, class: sreg_64 }307 - { id: 46, class: sreg_32_xm0 }308 - { id: 47, class: sreg_32_xm0 }309 - { id: 48, class: sreg_32_xm0 }310 - { id: 49, class: sreg_32_xm0 }311 - { id: 50, class: sreg_64 }312 - { id: 51, class: vreg_64 }313 - { id: 52, class: sreg_64 }314 - { id: 53, class: sreg_32_xm0 }315 - { id: 54, class: sreg_32_xm0 }316 - { id: 55, class: sreg_32_xm0 }317 - { id: 56, class: sreg_32_xm0 }318 - { id: 57, class: sreg_64 }319 - { id: 58, class: sreg_32_xm0 }320 - { id: 59, class: sreg_32_xm0 }321 - { id: 60, class: vgpr_32 }322 - { id: 61, class: vgpr_32 }323 - { id: 62, class: vreg_64 }324 - { id: 63, class: vgpr_32 }325 - { id: 64, class: vgpr_32 }326 - { id: 65, class: vgpr_32 }327 - { id: 66, class: vgpr_32 }328 - { id: 67, class: vreg_64 }329 - { id: 68, class: vgpr_32 }330 - { id: 69, class: vgpr_32 }331 - { id: 70, class: vgpr_32 }332 - { id: 71, class: vgpr_32 }333 - { id: 72, class: vgpr_32 }334 - { id: 73, class: vgpr_32 }335 - { id: 74, class: vgpr_32 }336 - { id: 75, class: vreg_64 }337 - { id: 76, class: vgpr_32 }338 - { id: 77, class: vgpr_32 }339 - { id: 78, class: vgpr_32 }340 - { id: 79, class: vgpr_32 }341 - { id: 80, class: vreg_64 }342 - { id: 81, class: vgpr_32 }343 - { id: 82, class: vgpr_32 }344 - { id: 83, class: vgpr_32 }345 - { id: 84, class: sreg_32_xm0 }346liveins:347 - { reg: '$sgpr4_sgpr5', virtual-reg: '%4' }348frameInfo:349 isFrameAddressTaken: false350 isReturnAddressTaken: false351 hasStackMap: false352 hasPatchPoint: false353 stackSize: 0354 offsetAdjustment: 0355 maxAlignment: 0356 adjustsStack: false357 hasCalls: false358 hasOpaqueSPAdjustment: false359 hasVAStart: false360 hasMustTailInVarArgFunc: false361body: |362 bb.0.bb:363 successors: %bb.2.bb2(0x80000000)364 liveins: $sgpr4_sgpr5365 366 %4 = COPY $sgpr4_sgpr5367 %9 = S_LOAD_DWORDX2_IMM %4, 0, 0 :: (non-temporal dereferenceable invariant load (s64) from `ptr addrspace(4) poison`)368 %8 = S_MOV_B64 0369 %7 = COPY %9370 %30 = V_MOV_B32_e32 1, implicit $exec371 %84 = S_MOV_B32 2372 S_BRANCH %bb.2.bb2373 374 bb.1.bb1:375 S_ENDPGM 0376 377 bb.2.bb2:378 successors: %bb.1.bb1(0x04000000), %bb.2.bb2(0x7c000000)379 380 %0 = PHI %8, %bb.0.bb, %1, %bb.2.bb2381 %13 = COPY %7.sub1382 %14 = S_ADD_U32 %7.sub0, %0.sub0, implicit-def $scc383 %15 = S_ADDC_U32 %7.sub1, %0.sub1, implicit-def dead $scc, implicit $scc384 %16 = REG_SEQUENCE %14, %subreg.sub0, %15, %subreg.sub1385 %18 = COPY %16386 %17 = FLAT_LOAD_DWORD %18, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %ir.uglygep45)387 %60 = V_BFE_U32_e64 %17, 8, 8, implicit $exec388 %61 = V_LSHLREV_B32_e32 %84, killed %60, implicit $exec389 %70 = V_ADD_CO_U32_e32 %7.sub0, %61, implicit-def $vcc, implicit $exec390 %66 = COPY %13391 %65 = V_ADDC_U32_e32 0, %66, implicit-def $vcc, implicit $vcc, implicit $exec392 %67 = REG_SEQUENCE %70, %subreg.sub0, killed %65, %subreg.sub1393 FLAT_STORE_DWORD %67, %30, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %ir.tmp9)394 %37 = S_ADD_U32 %14, 4, implicit-def $scc395 %38 = S_ADDC_U32 %15, 0, implicit-def dead $scc, implicit $scc396 %71 = COPY killed %37397 %72 = COPY killed %38398 %41 = REG_SEQUENCE killed %71, %subreg.sub0, killed %72, %subreg.sub1399 %40 = FLAT_LOAD_DWORD killed %41, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %ir.scevgep)400 %73 = V_BFE_U32_e64 %40, 8, 8, implicit $exec401 %74 = V_LSHLREV_B32_e32 %84, killed %73, implicit $exec402 %83 = V_ADD_CO_U32_e32 %7.sub0, %74, implicit-def $vcc, implicit $exec403 %78 = V_ADDC_U32_e32 0, %66, implicit-def $vcc, implicit $vcc, implicit $exec404 %80 = REG_SEQUENCE %83, %subreg.sub0, killed %78, %subreg.sub1405 FLAT_STORE_DWORD %80, %30, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %ir.tmp17)406 %55 = S_ADD_U32 %0.sub0, 8, implicit-def $scc407 %56 = S_ADDC_U32 %0.sub1, 0, implicit-def dead $scc, implicit $scc408 %57 = REG_SEQUENCE %55, %subreg.sub0, killed %56, %subreg.sub1409 %1 = COPY %57410 S_CMPK_EQ_I32 %55, 4096, implicit-def $scc411 S_CBRANCH_SCC1 %bb.1.bb1, implicit $scc412 S_BRANCH %bb.2.bb2413 414...415