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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefix=GFX7 %s3; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s4; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s5; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s6 7; Test if fcmp+select patterns form min/max instructions when allowed8; by flags.9 10; TODO: Merge with fmin_legacy.ll/fmax_legacy.ll11 12define float @v_test_fmin_legacy_ule_f32_safe(float %a, float %b) {13; GFX7-LABEL: v_test_fmin_legacy_ule_f32_safe:14; GFX7:       ; %bb.0:15; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)16; GFX7-NEXT:    v_min_legacy_f32_e32 v0, v1, v017; GFX7-NEXT:    s_setpc_b64 s[30:31]18;19; GFX9-LABEL: v_test_fmin_legacy_ule_f32_safe:20; GFX9:       ; %bb.0:21; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)22; GFX9-NEXT:    v_cmp_ngt_f32_e32 vcc, v0, v123; GFX9-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc24; GFX9-NEXT:    s_setpc_b64 s[30:31]25;26; GFX12-LABEL: v_test_fmin_legacy_ule_f32_safe:27; GFX12:       ; %bb.0:28; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x029; GFX12-NEXT:    s_wait_expcnt 0x030; GFX12-NEXT:    s_wait_samplecnt 0x031; GFX12-NEXT:    s_wait_bvhcnt 0x032; GFX12-NEXT:    s_wait_kmcnt 0x033; GFX12-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, v0, v134; GFX12-NEXT:    s_wait_alu depctr_va_vcc(0)35; GFX12-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo36; GFX12-NEXT:    s_setpc_b64 s[30:31]37  %cmp = fcmp ule float %a, %b38  %val = select i1 %cmp, float %a, float %b39  ret float %val40}41 42define float @v_test_fmin_legacy_ule_f32_nnan_flag(float %a, float %b) {43; GFX7-LABEL: v_test_fmin_legacy_ule_f32_nnan_flag:44; GFX7:       ; %bb.0:45; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)46; GFX7-NEXT:    v_min_legacy_f32_e32 v0, v1, v047; GFX7-NEXT:    s_setpc_b64 s[30:31]48;49; GFX9-LABEL: v_test_fmin_legacy_ule_f32_nnan_flag:50; GFX9:       ; %bb.0:51; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)52; GFX9-NEXT:    v_cmp_ngt_f32_e32 vcc, v0, v153; GFX9-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc54; GFX9-NEXT:    s_setpc_b64 s[30:31]55;56; GFX12-LABEL: v_test_fmin_legacy_ule_f32_nnan_flag:57; GFX12:       ; %bb.0:58; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x059; GFX12-NEXT:    s_wait_expcnt 0x060; GFX12-NEXT:    s_wait_samplecnt 0x061; GFX12-NEXT:    s_wait_bvhcnt 0x062; GFX12-NEXT:    s_wait_kmcnt 0x063; GFX12-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, v0, v164; GFX12-NEXT:    s_wait_alu depctr_va_vcc(0)65; GFX12-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo66; GFX12-NEXT:    s_setpc_b64 s[30:31]67  %cmp = fcmp ule float %a, %b68  %val = select nnan i1 %cmp, float %a, float %b69  ret float %val70}71 72define float @v_test_fmin_legacy_ule_f32_nsz_flag(float %a, float %b) {73; GFX7-LABEL: v_test_fmin_legacy_ule_f32_nsz_flag:74; GFX7:       ; %bb.0:75; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)76; GFX7-NEXT:    v_min_legacy_f32_e32 v0, v1, v077; GFX7-NEXT:    s_setpc_b64 s[30:31]78;79; GFX9-LABEL: v_test_fmin_legacy_ule_f32_nsz_flag:80; GFX9:       ; %bb.0:81; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)82; GFX9-NEXT:    v_cmp_ngt_f32_e32 vcc, v0, v183; GFX9-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc84; GFX9-NEXT:    s_setpc_b64 s[30:31]85;86; GFX12-LABEL: v_test_fmin_legacy_ule_f32_nsz_flag:87; GFX12:       ; %bb.0:88; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x089; GFX12-NEXT:    s_wait_expcnt 0x090; GFX12-NEXT:    s_wait_samplecnt 0x091; GFX12-NEXT:    s_wait_bvhcnt 0x092; GFX12-NEXT:    s_wait_kmcnt 0x093; GFX12-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, v0, v194; GFX12-NEXT:    s_wait_alu depctr_va_vcc(0)95; GFX12-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo96; GFX12-NEXT:    s_setpc_b64 s[30:31]97  %cmp = fcmp ule float %a, %b98  %val = select nsz i1 %cmp, float %a, float %b99  ret float %val100}101 102define float @v_test_fmin_legacy_ule_f32_nnan_nsz_flag(float %a, float %b) {103; GFX7-LABEL: v_test_fmin_legacy_ule_f32_nnan_nsz_flag:104; GFX7:       ; %bb.0:105; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)106; GFX7-NEXT:    v_min_f32_e32 v0, v0, v1107; GFX7-NEXT:    s_setpc_b64 s[30:31]108;109; GFX9-LABEL: v_test_fmin_legacy_ule_f32_nnan_nsz_flag:110; GFX9:       ; %bb.0:111; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)112; GFX9-NEXT:    v_min_f32_e32 v0, v0, v1113; GFX9-NEXT:    s_setpc_b64 s[30:31]114;115; GFX12-LABEL: v_test_fmin_legacy_ule_f32_nnan_nsz_flag:116; GFX12:       ; %bb.0:117; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0118; GFX12-NEXT:    s_wait_expcnt 0x0119; GFX12-NEXT:    s_wait_samplecnt 0x0120; GFX12-NEXT:    s_wait_bvhcnt 0x0121; GFX12-NEXT:    s_wait_kmcnt 0x0122; GFX12-NEXT:    v_min_num_f32_e32 v0, v0, v1123; GFX12-NEXT:    s_setpc_b64 s[30:31]124  %cmp = fcmp ule float %a, %b125  %val = select nnan nsz i1 %cmp, float %a, float %b126  ret float %val127}128 129define float @v_test_fmax_legacy_uge_f32_safe(float %a, float %b) {130; GFX7-LABEL: v_test_fmax_legacy_uge_f32_safe:131; GFX7:       ; %bb.0:132; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)133; GFX7-NEXT:    v_max_legacy_f32_e32 v0, v1, v0134; GFX7-NEXT:    s_setpc_b64 s[30:31]135;136; GFX9-LABEL: v_test_fmax_legacy_uge_f32_safe:137; GFX9:       ; %bb.0:138; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)139; GFX9-NEXT:    v_cmp_nlt_f32_e32 vcc, v0, v1140; GFX9-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc141; GFX9-NEXT:    s_setpc_b64 s[30:31]142;143; GFX12-LABEL: v_test_fmax_legacy_uge_f32_safe:144; GFX12:       ; %bb.0:145; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0146; GFX12-NEXT:    s_wait_expcnt 0x0147; GFX12-NEXT:    s_wait_samplecnt 0x0148; GFX12-NEXT:    s_wait_bvhcnt 0x0149; GFX12-NEXT:    s_wait_kmcnt 0x0150; GFX12-NEXT:    v_cmp_nlt_f32_e32 vcc_lo, v0, v1151; GFX12-NEXT:    s_wait_alu depctr_va_vcc(0)152; GFX12-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo153; GFX12-NEXT:    s_setpc_b64 s[30:31]154  %cmp = fcmp uge float %a, %b155  %val = select i1 %cmp, float %a, float %b156  ret float %val157}158 159define float @v_test_fmax_legacy_uge_f32_nnan_flag(float %a, float %b) {160; GFX7-LABEL: v_test_fmax_legacy_uge_f32_nnan_flag:161; GFX7:       ; %bb.0:162; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)163; GFX7-NEXT:    v_max_legacy_f32_e32 v0, v1, v0164; GFX7-NEXT:    s_setpc_b64 s[30:31]165;166; GFX9-LABEL: v_test_fmax_legacy_uge_f32_nnan_flag:167; GFX9:       ; %bb.0:168; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)169; GFX9-NEXT:    v_cmp_nlt_f32_e32 vcc, v0, v1170; GFX9-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc171; GFX9-NEXT:    s_setpc_b64 s[30:31]172;173; GFX12-LABEL: v_test_fmax_legacy_uge_f32_nnan_flag:174; GFX12:       ; %bb.0:175; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0176; GFX12-NEXT:    s_wait_expcnt 0x0177; GFX12-NEXT:    s_wait_samplecnt 0x0178; GFX12-NEXT:    s_wait_bvhcnt 0x0179; GFX12-NEXT:    s_wait_kmcnt 0x0180; GFX12-NEXT:    v_cmp_nlt_f32_e32 vcc_lo, v0, v1181; GFX12-NEXT:    s_wait_alu depctr_va_vcc(0)182; GFX12-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo183; GFX12-NEXT:    s_setpc_b64 s[30:31]184  %cmp = fcmp uge float %a, %b185  %val = select nnan i1 %cmp, float %a, float %b186  ret float %val187}188 189define float @v_test_fmax_legacy_uge_f32_nsz_flag(float %a, float %b) {190; GFX7-LABEL: v_test_fmax_legacy_uge_f32_nsz_flag:191; GFX7:       ; %bb.0:192; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)193; GFX7-NEXT:    v_max_legacy_f32_e32 v0, v1, v0194; GFX7-NEXT:    s_setpc_b64 s[30:31]195;196; GFX9-LABEL: v_test_fmax_legacy_uge_f32_nsz_flag:197; GFX9:       ; %bb.0:198; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)199; GFX9-NEXT:    v_cmp_nlt_f32_e32 vcc, v0, v1200; GFX9-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc201; GFX9-NEXT:    s_setpc_b64 s[30:31]202;203; GFX12-LABEL: v_test_fmax_legacy_uge_f32_nsz_flag:204; GFX12:       ; %bb.0:205; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0206; GFX12-NEXT:    s_wait_expcnt 0x0207; GFX12-NEXT:    s_wait_samplecnt 0x0208; GFX12-NEXT:    s_wait_bvhcnt 0x0209; GFX12-NEXT:    s_wait_kmcnt 0x0210; GFX12-NEXT:    v_cmp_nlt_f32_e32 vcc_lo, v0, v1211; GFX12-NEXT:    s_wait_alu depctr_va_vcc(0)212; GFX12-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo213; GFX12-NEXT:    s_setpc_b64 s[30:31]214  %cmp = fcmp uge float %a, %b215  %val = select nsz i1 %cmp, float %a, float %b216  ret float %val217}218 219define float @v_test_fmax_legacy_uge_f32_nnan_nsz_flag(float %a, float %b) {220; GFX7-LABEL: v_test_fmax_legacy_uge_f32_nnan_nsz_flag:221; GFX7:       ; %bb.0:222; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)223; GFX7-NEXT:    v_max_f32_e32 v0, v0, v1224; GFX7-NEXT:    s_setpc_b64 s[30:31]225;226; GFX9-LABEL: v_test_fmax_legacy_uge_f32_nnan_nsz_flag:227; GFX9:       ; %bb.0:228; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)229; GFX9-NEXT:    v_max_f32_e32 v0, v0, v1230; GFX9-NEXT:    s_setpc_b64 s[30:31]231;232; GFX12-LABEL: v_test_fmax_legacy_uge_f32_nnan_nsz_flag:233; GFX12:       ; %bb.0:234; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0235; GFX12-NEXT:    s_wait_expcnt 0x0236; GFX12-NEXT:    s_wait_samplecnt 0x0237; GFX12-NEXT:    s_wait_bvhcnt 0x0238; GFX12-NEXT:    s_wait_kmcnt 0x0239; GFX12-NEXT:    v_max_num_f32_e32 v0, v0, v1240; GFX12-NEXT:    s_setpc_b64 s[30:31]241  %cmp = fcmp uge float %a, %b242  %val = select nnan nsz i1 %cmp, float %a, float %b243  ret float %val244}245 246define <2 x float> @v_test_fmin_legacy_ule_v2f32_safe(<2 x float> %a, <2 x float> %b) {247; GFX7-LABEL: v_test_fmin_legacy_ule_v2f32_safe:248; GFX7:       ; %bb.0:249; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)250; GFX7-NEXT:    v_min_legacy_f32_e32 v0, v2, v0251; GFX7-NEXT:    v_min_legacy_f32_e32 v1, v3, v1252; GFX7-NEXT:    s_setpc_b64 s[30:31]253;254; GFX9-LABEL: v_test_fmin_legacy_ule_v2f32_safe:255; GFX9:       ; %bb.0:256; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)257; GFX9-NEXT:    v_cmp_ngt_f32_e32 vcc, v0, v2258; GFX9-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc259; GFX9-NEXT:    v_cmp_ngt_f32_e32 vcc, v1, v3260; GFX9-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc261; GFX9-NEXT:    s_setpc_b64 s[30:31]262;263; GFX12-LABEL: v_test_fmin_legacy_ule_v2f32_safe:264; GFX12:       ; %bb.0:265; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0266; GFX12-NEXT:    s_wait_expcnt 0x0267; GFX12-NEXT:    s_wait_samplecnt 0x0268; GFX12-NEXT:    s_wait_bvhcnt 0x0269; GFX12-NEXT:    s_wait_kmcnt 0x0270; GFX12-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, v0, v2271; GFX12-NEXT:    s_wait_alu depctr_va_vcc(0)272; GFX12-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo273; GFX12-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, v1, v3274; GFX12-NEXT:    s_wait_alu depctr_va_vcc(0)275; GFX12-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc_lo276; GFX12-NEXT:    s_setpc_b64 s[30:31]277  %cmp = fcmp ule <2 x float> %a, %b278  %val = select <2 x i1> %cmp, <2 x float> %a, <2 x float> %b279  ret <2 x float> %val280}281 282define <2 x float> @v_test_fmin_legacy_ule_v2f32_nnan_flag(<2 x float> %a, <2 x float> %b) {283; GFX7-LABEL: v_test_fmin_legacy_ule_v2f32_nnan_flag:284; GFX7:       ; %bb.0:285; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)286; GFX7-NEXT:    v_min_legacy_f32_e32 v0, v2, v0287; GFX7-NEXT:    v_min_legacy_f32_e32 v1, v3, v1288; GFX7-NEXT:    s_setpc_b64 s[30:31]289;290; GFX9-LABEL: v_test_fmin_legacy_ule_v2f32_nnan_flag:291; GFX9:       ; %bb.0:292; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)293; GFX9-NEXT:    v_cmp_ngt_f32_e32 vcc, v0, v2294; GFX9-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc295; GFX9-NEXT:    v_cmp_ngt_f32_e32 vcc, v1, v3296; GFX9-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc297; GFX9-NEXT:    s_setpc_b64 s[30:31]298;299; GFX12-LABEL: v_test_fmin_legacy_ule_v2f32_nnan_flag:300; GFX12:       ; %bb.0:301; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0302; GFX12-NEXT:    s_wait_expcnt 0x0303; GFX12-NEXT:    s_wait_samplecnt 0x0304; GFX12-NEXT:    s_wait_bvhcnt 0x0305; GFX12-NEXT:    s_wait_kmcnt 0x0306; GFX12-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, v0, v2307; GFX12-NEXT:    s_wait_alu depctr_va_vcc(0)308; GFX12-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo309; GFX12-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, v1, v3310; GFX12-NEXT:    s_wait_alu depctr_va_vcc(0)311; GFX12-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc_lo312; GFX12-NEXT:    s_setpc_b64 s[30:31]313  %cmp = fcmp ule <2 x float> %a, %b314  %val = select nnan <2 x i1> %cmp, <2 x float> %a, <2 x float> %b315  ret <2 x float> %val316}317 318define <2 x float> @v_test_fmin_legacy_ule_v2f32_nsz_flag(<2 x float> %a, <2 x float> %b) {319; GFX7-LABEL: v_test_fmin_legacy_ule_v2f32_nsz_flag:320; GFX7:       ; %bb.0:321; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)322; GFX7-NEXT:    v_min_legacy_f32_e32 v0, v2, v0323; GFX7-NEXT:    v_min_legacy_f32_e32 v1, v3, v1324; GFX7-NEXT:    s_setpc_b64 s[30:31]325;326; GFX9-LABEL: v_test_fmin_legacy_ule_v2f32_nsz_flag:327; GFX9:       ; %bb.0:328; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)329; GFX9-NEXT:    v_cmp_ngt_f32_e32 vcc, v0, v2330; GFX9-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc331; GFX9-NEXT:    v_cmp_ngt_f32_e32 vcc, v1, v3332; GFX9-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc333; GFX9-NEXT:    s_setpc_b64 s[30:31]334;335; GFX12-LABEL: v_test_fmin_legacy_ule_v2f32_nsz_flag:336; GFX12:       ; %bb.0:337; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0338; GFX12-NEXT:    s_wait_expcnt 0x0339; GFX12-NEXT:    s_wait_samplecnt 0x0340; GFX12-NEXT:    s_wait_bvhcnt 0x0341; GFX12-NEXT:    s_wait_kmcnt 0x0342; GFX12-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, v0, v2343; GFX12-NEXT:    s_wait_alu depctr_va_vcc(0)344; GFX12-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo345; GFX12-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, v1, v3346; GFX12-NEXT:    s_wait_alu depctr_va_vcc(0)347; GFX12-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc_lo348; GFX12-NEXT:    s_setpc_b64 s[30:31]349  %cmp = fcmp ule <2 x float> %a, %b350  %val = select nsz <2 x i1> %cmp, <2 x float> %a, <2 x float> %b351  ret <2 x float> %val352}353 354define <2 x float> @v_test_fmin_legacy_ule_v2f32_nnan_nsz_flag(<2 x float> %a, <2 x float> %b) {355; GFX7-LABEL: v_test_fmin_legacy_ule_v2f32_nnan_nsz_flag:356; GFX7:       ; %bb.0:357; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)358; GFX7-NEXT:    v_min_f32_e32 v0, v0, v2359; GFX7-NEXT:    v_min_f32_e32 v1, v1, v3360; GFX7-NEXT:    s_setpc_b64 s[30:31]361;362; GFX9-LABEL: v_test_fmin_legacy_ule_v2f32_nnan_nsz_flag:363; GFX9:       ; %bb.0:364; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)365; GFX9-NEXT:    v_min_f32_e32 v0, v0, v2366; GFX9-NEXT:    v_min_f32_e32 v1, v1, v3367; GFX9-NEXT:    s_setpc_b64 s[30:31]368;369; GFX12-LABEL: v_test_fmin_legacy_ule_v2f32_nnan_nsz_flag:370; GFX12:       ; %bb.0:371; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0372; GFX12-NEXT:    s_wait_expcnt 0x0373; GFX12-NEXT:    s_wait_samplecnt 0x0374; GFX12-NEXT:    s_wait_bvhcnt 0x0375; GFX12-NEXT:    s_wait_kmcnt 0x0376; GFX12-NEXT:    v_dual_min_num_f32 v0, v0, v2 :: v_dual_min_num_f32 v1, v1, v3377; GFX12-NEXT:    s_setpc_b64 s[30:31]378  %cmp = fcmp ule <2 x float> %a, %b379  %val = select nnan nsz <2 x i1> %cmp, <2 x float> %a, <2 x float> %b380  ret <2 x float> %val381}382 383define <2 x float> @v_test_fmax_legacy_uge_v2f32_safe(<2 x float> %a, <2 x float> %b) {384; GFX7-LABEL: v_test_fmax_legacy_uge_v2f32_safe:385; GFX7:       ; %bb.0:386; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)387; GFX7-NEXT:    v_max_legacy_f32_e32 v0, v2, v0388; GFX7-NEXT:    v_max_legacy_f32_e32 v1, v3, v1389; GFX7-NEXT:    s_setpc_b64 s[30:31]390;391; GFX9-LABEL: v_test_fmax_legacy_uge_v2f32_safe:392; GFX9:       ; %bb.0:393; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)394; GFX9-NEXT:    v_cmp_nlt_f32_e32 vcc, v0, v2395; GFX9-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc396; GFX9-NEXT:    v_cmp_nlt_f32_e32 vcc, v1, v3397; GFX9-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc398; GFX9-NEXT:    s_setpc_b64 s[30:31]399;400; GFX12-LABEL: v_test_fmax_legacy_uge_v2f32_safe:401; GFX12:       ; %bb.0:402; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0403; GFX12-NEXT:    s_wait_expcnt 0x0404; GFX12-NEXT:    s_wait_samplecnt 0x0405; GFX12-NEXT:    s_wait_bvhcnt 0x0406; GFX12-NEXT:    s_wait_kmcnt 0x0407; GFX12-NEXT:    v_cmp_nlt_f32_e32 vcc_lo, v0, v2408; GFX12-NEXT:    s_wait_alu depctr_va_vcc(0)409; GFX12-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo410; GFX12-NEXT:    v_cmp_nlt_f32_e32 vcc_lo, v1, v3411; GFX12-NEXT:    s_wait_alu depctr_va_vcc(0)412; GFX12-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc_lo413; GFX12-NEXT:    s_setpc_b64 s[30:31]414  %cmp = fcmp uge <2 x float> %a, %b415  %val = select <2 x i1> %cmp, <2 x float> %a, <2 x float> %b416  ret <2 x float> %val417}418 419define <2 x float> @v_test_fmax_legacy_uge_v2f32_nnan_flag(<2 x float> %a, <2 x float> %b) {420; GFX7-LABEL: v_test_fmax_legacy_uge_v2f32_nnan_flag:421; GFX7:       ; %bb.0:422; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)423; GFX7-NEXT:    v_max_legacy_f32_e32 v0, v2, v0424; GFX7-NEXT:    v_max_legacy_f32_e32 v1, v3, v1425; GFX7-NEXT:    s_setpc_b64 s[30:31]426;427; GFX9-LABEL: v_test_fmax_legacy_uge_v2f32_nnan_flag:428; GFX9:       ; %bb.0:429; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)430; GFX9-NEXT:    v_cmp_nlt_f32_e32 vcc, v0, v2431; GFX9-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc432; GFX9-NEXT:    v_cmp_nlt_f32_e32 vcc, v1, v3433; GFX9-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc434; GFX9-NEXT:    s_setpc_b64 s[30:31]435;436; GFX12-LABEL: v_test_fmax_legacy_uge_v2f32_nnan_flag:437; GFX12:       ; %bb.0:438; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0439; GFX12-NEXT:    s_wait_expcnt 0x0440; GFX12-NEXT:    s_wait_samplecnt 0x0441; GFX12-NEXT:    s_wait_bvhcnt 0x0442; GFX12-NEXT:    s_wait_kmcnt 0x0443; GFX12-NEXT:    v_cmp_nlt_f32_e32 vcc_lo, v0, v2444; GFX12-NEXT:    s_wait_alu depctr_va_vcc(0)445; GFX12-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo446; GFX12-NEXT:    v_cmp_nlt_f32_e32 vcc_lo, v1, v3447; GFX12-NEXT:    s_wait_alu depctr_va_vcc(0)448; GFX12-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc_lo449; GFX12-NEXT:    s_setpc_b64 s[30:31]450  %cmp = fcmp uge <2 x float> %a, %b451  %val = select nnan <2 x i1> %cmp, <2 x float> %a, <2 x float> %b452  ret <2 x float> %val453}454 455define <2 x float> @v_test_fmax_legacy_uge_v2f32_nsz_flag(<2 x float> %a, <2 x float> %b) {456; GFX7-LABEL: v_test_fmax_legacy_uge_v2f32_nsz_flag:457; GFX7:       ; %bb.0:458; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)459; GFX7-NEXT:    v_max_legacy_f32_e32 v0, v2, v0460; GFX7-NEXT:    v_max_legacy_f32_e32 v1, v3, v1461; GFX7-NEXT:    s_setpc_b64 s[30:31]462;463; GFX9-LABEL: v_test_fmax_legacy_uge_v2f32_nsz_flag:464; GFX9:       ; %bb.0:465; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)466; GFX9-NEXT:    v_cmp_nlt_f32_e32 vcc, v0, v2467; GFX9-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc468; GFX9-NEXT:    v_cmp_nlt_f32_e32 vcc, v1, v3469; GFX9-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc470; GFX9-NEXT:    s_setpc_b64 s[30:31]471;472; GFX12-LABEL: v_test_fmax_legacy_uge_v2f32_nsz_flag:473; GFX12:       ; %bb.0:474; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0475; GFX12-NEXT:    s_wait_expcnt 0x0476; GFX12-NEXT:    s_wait_samplecnt 0x0477; GFX12-NEXT:    s_wait_bvhcnt 0x0478; GFX12-NEXT:    s_wait_kmcnt 0x0479; GFX12-NEXT:    v_cmp_nlt_f32_e32 vcc_lo, v0, v2480; GFX12-NEXT:    s_wait_alu depctr_va_vcc(0)481; GFX12-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo482; GFX12-NEXT:    v_cmp_nlt_f32_e32 vcc_lo, v1, v3483; GFX12-NEXT:    s_wait_alu depctr_va_vcc(0)484; GFX12-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc_lo485; GFX12-NEXT:    s_setpc_b64 s[30:31]486  %cmp = fcmp uge <2 x float> %a, %b487  %val = select nsz <2 x i1> %cmp, <2 x float> %a, <2 x float> %b488  ret <2 x float> %val489}490 491define <2 x float> @v_test_fmax_legacy_uge_v2f32_nnan_nsz_flag(<2 x float> %a, <2 x float> %b) {492; GFX7-LABEL: v_test_fmax_legacy_uge_v2f32_nnan_nsz_flag:493; GFX7:       ; %bb.0:494; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)495; GFX7-NEXT:    v_max_f32_e32 v0, v0, v2496; GFX7-NEXT:    v_max_f32_e32 v1, v1, v3497; GFX7-NEXT:    s_setpc_b64 s[30:31]498;499; GFX9-LABEL: v_test_fmax_legacy_uge_v2f32_nnan_nsz_flag:500; GFX9:       ; %bb.0:501; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)502; GFX9-NEXT:    v_max_f32_e32 v0, v0, v2503; GFX9-NEXT:    v_max_f32_e32 v1, v1, v3504; GFX9-NEXT:    s_setpc_b64 s[30:31]505;506; GFX12-LABEL: v_test_fmax_legacy_uge_v2f32_nnan_nsz_flag:507; GFX12:       ; %bb.0:508; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0509; GFX12-NEXT:    s_wait_expcnt 0x0510; GFX12-NEXT:    s_wait_samplecnt 0x0511; GFX12-NEXT:    s_wait_bvhcnt 0x0512; GFX12-NEXT:    s_wait_kmcnt 0x0513; GFX12-NEXT:    v_dual_max_num_f32 v0, v0, v2 :: v_dual_max_num_f32 v1, v1, v3514; GFX12-NEXT:    s_setpc_b64 s[30:31]515  %cmp = fcmp uge <2 x float> %a, %b516  %val = select nnan nsz <2 x i1> %cmp, <2 x float> %a, <2 x float> %b517  ret <2 x float> %val518}519 520define half @v_test_fmin_legacy_ule_f16_safe(half %a, half %b) {521; GFX7-LABEL: v_test_fmin_legacy_ule_f16_safe:522; GFX7:       ; %bb.0:523; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)524; GFX7-NEXT:    v_cvt_f16_f32_e32 v0, v0525; GFX7-NEXT:    v_cvt_f16_f32_e32 v1, v1526; GFX7-NEXT:    v_cvt_f32_f16_e32 v0, v0527; GFX7-NEXT:    v_cvt_f32_f16_e32 v1, v1528; GFX7-NEXT:    v_min_legacy_f32_e32 v0, v1, v0529; GFX7-NEXT:    s_setpc_b64 s[30:31]530;531; GFX9-LABEL: v_test_fmin_legacy_ule_f16_safe:532; GFX9:       ; %bb.0:533; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)534; GFX9-NEXT:    v_cmp_ngt_f16_e32 vcc, v0, v1535; GFX9-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc536; GFX9-NEXT:    s_setpc_b64 s[30:31]537;538; GFX12-TRUE16-LABEL: v_test_fmin_legacy_ule_f16_safe:539; GFX12-TRUE16:       ; %bb.0:540; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0541; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0542; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0543; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0544; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0545; GFX12-TRUE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v0.l, v1.l546; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)547; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v1.l, v0.l, vcc_lo548; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]549;550; GFX12-FAKE16-LABEL: v_test_fmin_legacy_ule_f16_safe:551; GFX12-FAKE16:       ; %bb.0:552; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0553; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0554; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0555; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0556; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0557; GFX12-FAKE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v0, v1558; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)559; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo560; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]561  %cmp = fcmp ule half %a, %b562  %val = select i1 %cmp, half %a, half %b563  ret half %val564}565 566define half @v_test_fmin_legacy_ule_f16_nnan_flag(half %a, half %b) {567; GFX7-LABEL: v_test_fmin_legacy_ule_f16_nnan_flag:568; GFX7:       ; %bb.0:569; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)570; GFX7-NEXT:    v_cvt_f16_f32_e32 v0, v0571; GFX7-NEXT:    v_cvt_f16_f32_e32 v1, v1572; GFX7-NEXT:    v_cvt_f32_f16_e32 v0, v0573; GFX7-NEXT:    v_cvt_f32_f16_e32 v1, v1574; GFX7-NEXT:    v_min_legacy_f32_e32 v0, v1, v0575; GFX7-NEXT:    s_setpc_b64 s[30:31]576;577; GFX9-LABEL: v_test_fmin_legacy_ule_f16_nnan_flag:578; GFX9:       ; %bb.0:579; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)580; GFX9-NEXT:    v_cmp_ngt_f16_e32 vcc, v0, v1581; GFX9-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc582; GFX9-NEXT:    s_setpc_b64 s[30:31]583;584; GFX12-TRUE16-LABEL: v_test_fmin_legacy_ule_f16_nnan_flag:585; GFX12-TRUE16:       ; %bb.0:586; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0587; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0588; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0589; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0590; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0591; GFX12-TRUE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v0.l, v1.l592; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)593; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v1.l, v0.l, vcc_lo594; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]595;596; GFX12-FAKE16-LABEL: v_test_fmin_legacy_ule_f16_nnan_flag:597; GFX12-FAKE16:       ; %bb.0:598; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0599; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0600; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0601; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0602; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0603; GFX12-FAKE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v0, v1604; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)605; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo606; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]607  %cmp = fcmp ule half %a, %b608  %val = select nnan i1 %cmp, half %a, half %b609  ret half %val610}611 612define half @v_test_fmin_legacy_ule_f16_nsz_flag(half %a, half %b) {613; GFX7-LABEL: v_test_fmin_legacy_ule_f16_nsz_flag:614; GFX7:       ; %bb.0:615; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)616; GFX7-NEXT:    v_cvt_f16_f32_e32 v0, v0617; GFX7-NEXT:    v_cvt_f16_f32_e32 v1, v1618; GFX7-NEXT:    v_cvt_f32_f16_e32 v0, v0619; GFX7-NEXT:    v_cvt_f32_f16_e32 v1, v1620; GFX7-NEXT:    v_min_legacy_f32_e32 v0, v1, v0621; GFX7-NEXT:    s_setpc_b64 s[30:31]622;623; GFX9-LABEL: v_test_fmin_legacy_ule_f16_nsz_flag:624; GFX9:       ; %bb.0:625; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)626; GFX9-NEXT:    v_cmp_ngt_f16_e32 vcc, v0, v1627; GFX9-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc628; GFX9-NEXT:    s_setpc_b64 s[30:31]629;630; GFX12-TRUE16-LABEL: v_test_fmin_legacy_ule_f16_nsz_flag:631; GFX12-TRUE16:       ; %bb.0:632; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0633; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0634; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0635; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0636; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0637; GFX12-TRUE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v0.l, v1.l638; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)639; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v1.l, v0.l, vcc_lo640; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]641;642; GFX12-FAKE16-LABEL: v_test_fmin_legacy_ule_f16_nsz_flag:643; GFX12-FAKE16:       ; %bb.0:644; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0645; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0646; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0647; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0648; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0649; GFX12-FAKE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v0, v1650; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)651; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo652; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]653  %cmp = fcmp ule half %a, %b654  %val = select nsz i1 %cmp, half %a, half %b655  ret half %val656}657 658define half @v_test_fmin_legacy_ule_f16_nnan_nsz_flag(half %a, half %b) {659; GFX7-LABEL: v_test_fmin_legacy_ule_f16_nnan_nsz_flag:660; GFX7:       ; %bb.0:661; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)662; GFX7-NEXT:    v_cvt_f16_f32_e32 v1, v1663; GFX7-NEXT:    v_cvt_f16_f32_e32 v0, v0664; GFX7-NEXT:    v_cvt_f32_f16_e32 v1, v1665; GFX7-NEXT:    v_cvt_f32_f16_e32 v0, v0666; GFX7-NEXT:    v_min_f32_e32 v0, v0, v1667; GFX7-NEXT:    s_setpc_b64 s[30:31]668;669; GFX9-LABEL: v_test_fmin_legacy_ule_f16_nnan_nsz_flag:670; GFX9:       ; %bb.0:671; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)672; GFX9-NEXT:    v_min_f16_e32 v0, v0, v1673; GFX9-NEXT:    s_setpc_b64 s[30:31]674;675; GFX12-TRUE16-LABEL: v_test_fmin_legacy_ule_f16_nnan_nsz_flag:676; GFX12-TRUE16:       ; %bb.0:677; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0678; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0679; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0680; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0681; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0682; GFX12-TRUE16-NEXT:    v_min_num_f16_e32 v0.l, v0.l, v1.l683; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]684;685; GFX12-FAKE16-LABEL: v_test_fmin_legacy_ule_f16_nnan_nsz_flag:686; GFX12-FAKE16:       ; %bb.0:687; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0688; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0689; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0690; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0691; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0692; GFX12-FAKE16-NEXT:    v_min_num_f16_e32 v0, v0, v1693; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]694  %cmp = fcmp ule half %a, %b695  %val = select nnan nsz i1 %cmp, half %a, half %b696  ret half %val697}698 699define half @v_test_fmax_legacy_uge_f16_safe(half %a, half %b) {700; GFX7-LABEL: v_test_fmax_legacy_uge_f16_safe:701; GFX7:       ; %bb.0:702; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)703; GFX7-NEXT:    v_cvt_f16_f32_e32 v0, v0704; GFX7-NEXT:    v_cvt_f16_f32_e32 v1, v1705; GFX7-NEXT:    v_cvt_f32_f16_e32 v0, v0706; GFX7-NEXT:    v_cvt_f32_f16_e32 v1, v1707; GFX7-NEXT:    v_max_legacy_f32_e32 v0, v1, v0708; GFX7-NEXT:    s_setpc_b64 s[30:31]709;710; GFX9-LABEL: v_test_fmax_legacy_uge_f16_safe:711; GFX9:       ; %bb.0:712; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)713; GFX9-NEXT:    v_cmp_nlt_f16_e32 vcc, v0, v1714; GFX9-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc715; GFX9-NEXT:    s_setpc_b64 s[30:31]716;717; GFX12-TRUE16-LABEL: v_test_fmax_legacy_uge_f16_safe:718; GFX12-TRUE16:       ; %bb.0:719; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0720; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0721; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0722; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0723; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0724; GFX12-TRUE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v0.l, v1.l725; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)726; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v1.l, v0.l, vcc_lo727; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]728;729; GFX12-FAKE16-LABEL: v_test_fmax_legacy_uge_f16_safe:730; GFX12-FAKE16:       ; %bb.0:731; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0732; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0733; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0734; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0735; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0736; GFX12-FAKE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v0, v1737; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)738; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo739; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]740  %cmp = fcmp uge half %a, %b741  %val = select i1 %cmp, half %a, half %b742  ret half %val743}744 745define half @v_test_fmax_legacy_uge_f16_nnan_flag(half %a, half %b) {746; GFX7-LABEL: v_test_fmax_legacy_uge_f16_nnan_flag:747; GFX7:       ; %bb.0:748; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)749; GFX7-NEXT:    v_cvt_f16_f32_e32 v0, v0750; GFX7-NEXT:    v_cvt_f16_f32_e32 v1, v1751; GFX7-NEXT:    v_cvt_f32_f16_e32 v0, v0752; GFX7-NEXT:    v_cvt_f32_f16_e32 v1, v1753; GFX7-NEXT:    v_max_legacy_f32_e32 v0, v1, v0754; GFX7-NEXT:    s_setpc_b64 s[30:31]755;756; GFX9-LABEL: v_test_fmax_legacy_uge_f16_nnan_flag:757; GFX9:       ; %bb.0:758; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)759; GFX9-NEXT:    v_cmp_nlt_f16_e32 vcc, v0, v1760; GFX9-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc761; GFX9-NEXT:    s_setpc_b64 s[30:31]762;763; GFX12-TRUE16-LABEL: v_test_fmax_legacy_uge_f16_nnan_flag:764; GFX12-TRUE16:       ; %bb.0:765; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0766; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0767; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0768; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0769; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0770; GFX12-TRUE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v0.l, v1.l771; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)772; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v1.l, v0.l, vcc_lo773; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]774;775; GFX12-FAKE16-LABEL: v_test_fmax_legacy_uge_f16_nnan_flag:776; GFX12-FAKE16:       ; %bb.0:777; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0778; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0779; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0780; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0781; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0782; GFX12-FAKE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v0, v1783; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)784; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo785; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]786  %cmp = fcmp uge half %a, %b787  %val = select nnan i1 %cmp, half %a, half %b788  ret half %val789}790 791define half @v_test_fmax_legacy_uge_f16_nsz_flag(half %a, half %b) {792; GFX7-LABEL: v_test_fmax_legacy_uge_f16_nsz_flag:793; GFX7:       ; %bb.0:794; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)795; GFX7-NEXT:    v_cvt_f16_f32_e32 v0, v0796; GFX7-NEXT:    v_cvt_f16_f32_e32 v1, v1797; GFX7-NEXT:    v_cvt_f32_f16_e32 v0, v0798; GFX7-NEXT:    v_cvt_f32_f16_e32 v1, v1799; GFX7-NEXT:    v_max_legacy_f32_e32 v0, v1, v0800; GFX7-NEXT:    s_setpc_b64 s[30:31]801;802; GFX9-LABEL: v_test_fmax_legacy_uge_f16_nsz_flag:803; GFX9:       ; %bb.0:804; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)805; GFX9-NEXT:    v_cmp_nlt_f16_e32 vcc, v0, v1806; GFX9-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc807; GFX9-NEXT:    s_setpc_b64 s[30:31]808;809; GFX12-TRUE16-LABEL: v_test_fmax_legacy_uge_f16_nsz_flag:810; GFX12-TRUE16:       ; %bb.0:811; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0812; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0813; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0814; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0815; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0816; GFX12-TRUE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v0.l, v1.l817; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)818; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v1.l, v0.l, vcc_lo819; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]820;821; GFX12-FAKE16-LABEL: v_test_fmax_legacy_uge_f16_nsz_flag:822; GFX12-FAKE16:       ; %bb.0:823; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0824; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0825; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0826; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0827; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0828; GFX12-FAKE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v0, v1829; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)830; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo831; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]832  %cmp = fcmp uge half %a, %b833  %val = select nsz i1 %cmp, half %a, half %b834  ret half %val835}836 837define half @v_test_fmax_legacy_uge_f16_nnan_nsz_flag(half %a, half %b) {838; GFX7-LABEL: v_test_fmax_legacy_uge_f16_nnan_nsz_flag:839; GFX7:       ; %bb.0:840; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)841; GFX7-NEXT:    v_cvt_f16_f32_e32 v1, v1842; GFX7-NEXT:    v_cvt_f16_f32_e32 v0, v0843; GFX7-NEXT:    v_cvt_f32_f16_e32 v1, v1844; GFX7-NEXT:    v_cvt_f32_f16_e32 v0, v0845; GFX7-NEXT:    v_max_f32_e32 v0, v0, v1846; GFX7-NEXT:    s_setpc_b64 s[30:31]847;848; GFX9-LABEL: v_test_fmax_legacy_uge_f16_nnan_nsz_flag:849; GFX9:       ; %bb.0:850; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)851; GFX9-NEXT:    v_max_f16_e32 v0, v0, v1852; GFX9-NEXT:    s_setpc_b64 s[30:31]853;854; GFX12-TRUE16-LABEL: v_test_fmax_legacy_uge_f16_nnan_nsz_flag:855; GFX12-TRUE16:       ; %bb.0:856; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0857; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0858; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0859; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0860; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0861; GFX12-TRUE16-NEXT:    v_max_num_f16_e32 v0.l, v0.l, v1.l862; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]863;864; GFX12-FAKE16-LABEL: v_test_fmax_legacy_uge_f16_nnan_nsz_flag:865; GFX12-FAKE16:       ; %bb.0:866; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0867; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0868; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0869; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0870; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0871; GFX12-FAKE16-NEXT:    v_max_num_f16_e32 v0, v0, v1872; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]873  %cmp = fcmp uge half %a, %b874  %val = select nnan nsz i1 %cmp, half %a, half %b875  ret half %val876}877 878define <2 x half> @v_test_fmin_legacy_ule_v2f16_safe(<2 x half> %a, <2 x half> %b) {879; GFX7-LABEL: v_test_fmin_legacy_ule_v2f16_safe:880; GFX7:       ; %bb.0:881; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)882; GFX7-NEXT:    v_cvt_f16_f32_e32 v1, v1883; GFX7-NEXT:    v_cvt_f16_f32_e32 v0, v0884; GFX7-NEXT:    v_cvt_f16_f32_e32 v2, v2885; GFX7-NEXT:    v_cvt_f16_f32_e32 v3, v3886; GFX7-NEXT:    v_cvt_f32_f16_e32 v1, v1887; GFX7-NEXT:    v_cvt_f32_f16_e32 v0, v0888; GFX7-NEXT:    v_cvt_f32_f16_e32 v2, v2889; GFX7-NEXT:    v_cvt_f32_f16_e32 v3, v3890; GFX7-NEXT:    v_min_legacy_f32_e32 v0, v2, v0891; GFX7-NEXT:    v_min_legacy_f32_e32 v1, v3, v1892; GFX7-NEXT:    s_setpc_b64 s[30:31]893;894; GFX9-LABEL: v_test_fmin_legacy_ule_v2f16_safe:895; GFX9:       ; %bb.0:896; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)897; GFX9-NEXT:    v_lshrrev_b32_e32 v2, 16, v1898; GFX9-NEXT:    v_lshrrev_b32_e32 v3, 16, v0899; GFX9-NEXT:    v_cmp_ngt_f16_e32 vcc, v3, v2900; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc901; GFX9-NEXT:    v_cmp_ngt_f16_e32 vcc, v0, v1902; GFX9-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc903; GFX9-NEXT:    s_mov_b32 s4, 0x5040100904; GFX9-NEXT:    v_perm_b32 v0, v2, v0, s4905; GFX9-NEXT:    s_setpc_b64 s[30:31]906;907; GFX12-TRUE16-LABEL: v_test_fmin_legacy_ule_v2f16_safe:908; GFX12-TRUE16:       ; %bb.0:909; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0910; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0911; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0912; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0913; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0914; GFX12-TRUE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v0.h, v1.h915; GFX12-TRUE16-NEXT:    v_cmp_ngt_f16_e64 s0, v0.l, v1.l916; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)917; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v1.h, v0.h, vcc_lo918; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)919; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)920; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v1.l, v0.l, s0921; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]922;923; GFX12-FAKE16-LABEL: v_test_fmin_legacy_ule_v2f16_safe:924; GFX12-FAKE16:       ; %bb.0:925; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0926; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0927; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0928; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0929; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0930; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v1931; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v0932; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)933; GFX12-FAKE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v3, v2934; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)935; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc_lo936; GFX12-FAKE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v0, v1937; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)938; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo939; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)940; GFX12-FAKE16-NEXT:    v_perm_b32 v0, v2, v0, 0x5040100941; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]942  %cmp = fcmp ule <2 x half> %a, %b943  %val = select <2 x i1> %cmp, <2 x half> %a, <2 x half> %b944  ret <2 x half> %val945}946 947define <2 x half> @v_test_fmin_legacy_ule_v2f16_nnan_flag(<2 x half> %a, <2 x half> %b) {948; GFX7-LABEL: v_test_fmin_legacy_ule_v2f16_nnan_flag:949; GFX7:       ; %bb.0:950; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)951; GFX7-NEXT:    v_cvt_f16_f32_e32 v1, v1952; GFX7-NEXT:    v_cvt_f16_f32_e32 v0, v0953; GFX7-NEXT:    v_cvt_f16_f32_e32 v2, v2954; GFX7-NEXT:    v_cvt_f16_f32_e32 v3, v3955; GFX7-NEXT:    v_cvt_f32_f16_e32 v1, v1956; GFX7-NEXT:    v_cvt_f32_f16_e32 v0, v0957; GFX7-NEXT:    v_cvt_f32_f16_e32 v2, v2958; GFX7-NEXT:    v_cvt_f32_f16_e32 v3, v3959; GFX7-NEXT:    v_min_legacy_f32_e32 v0, v2, v0960; GFX7-NEXT:    v_min_legacy_f32_e32 v1, v3, v1961; GFX7-NEXT:    s_setpc_b64 s[30:31]962;963; GFX9-LABEL: v_test_fmin_legacy_ule_v2f16_nnan_flag:964; GFX9:       ; %bb.0:965; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)966; GFX9-NEXT:    v_lshrrev_b32_e32 v2, 16, v1967; GFX9-NEXT:    v_lshrrev_b32_e32 v3, 16, v0968; GFX9-NEXT:    v_cmp_ngt_f16_e32 vcc, v3, v2969; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc970; GFX9-NEXT:    v_cmp_ngt_f16_e32 vcc, v0, v1971; GFX9-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc972; GFX9-NEXT:    s_mov_b32 s4, 0x5040100973; GFX9-NEXT:    v_perm_b32 v0, v2, v0, s4974; GFX9-NEXT:    s_setpc_b64 s[30:31]975;976; GFX12-TRUE16-LABEL: v_test_fmin_legacy_ule_v2f16_nnan_flag:977; GFX12-TRUE16:       ; %bb.0:978; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0979; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0980; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0981; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0982; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0983; GFX12-TRUE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v0.h, v1.h984; GFX12-TRUE16-NEXT:    v_cmp_ngt_f16_e64 s0, v0.l, v1.l985; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)986; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v1.h, v0.h, vcc_lo987; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)988; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)989; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v1.l, v0.l, s0990; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]991;992; GFX12-FAKE16-LABEL: v_test_fmin_legacy_ule_v2f16_nnan_flag:993; GFX12-FAKE16:       ; %bb.0:994; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0995; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0996; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0997; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0998; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0999; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v11000; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v01001; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)1002; GFX12-FAKE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v3, v21003; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)1004; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc_lo1005; GFX12-FAKE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v0, v11006; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)1007; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo1008; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)1009; GFX12-FAKE16-NEXT:    v_perm_b32 v0, v2, v0, 0x50401001010; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]1011  %cmp = fcmp ule <2 x half> %a, %b1012  %val = select nnan <2 x i1> %cmp, <2 x half> %a, <2 x half> %b1013  ret <2 x half> %val1014}1015 1016define <2 x half> @v_test_fmin_legacy_ule_v2f16_nsz_flag(<2 x half> %a, <2 x half> %b) {1017; GFX7-LABEL: v_test_fmin_legacy_ule_v2f16_nsz_flag:1018; GFX7:       ; %bb.0:1019; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1020; GFX7-NEXT:    v_cvt_f16_f32_e32 v1, v11021; GFX7-NEXT:    v_cvt_f16_f32_e32 v0, v01022; GFX7-NEXT:    v_cvt_f16_f32_e32 v2, v21023; GFX7-NEXT:    v_cvt_f16_f32_e32 v3, v31024; GFX7-NEXT:    v_cvt_f32_f16_e32 v1, v11025; GFX7-NEXT:    v_cvt_f32_f16_e32 v0, v01026; GFX7-NEXT:    v_cvt_f32_f16_e32 v2, v21027; GFX7-NEXT:    v_cvt_f32_f16_e32 v3, v31028; GFX7-NEXT:    v_min_legacy_f32_e32 v0, v2, v01029; GFX7-NEXT:    v_min_legacy_f32_e32 v1, v3, v11030; GFX7-NEXT:    s_setpc_b64 s[30:31]1031;1032; GFX9-LABEL: v_test_fmin_legacy_ule_v2f16_nsz_flag:1033; GFX9:       ; %bb.0:1034; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1035; GFX9-NEXT:    v_lshrrev_b32_e32 v2, 16, v11036; GFX9-NEXT:    v_lshrrev_b32_e32 v3, 16, v01037; GFX9-NEXT:    v_cmp_ngt_f16_e32 vcc, v3, v21038; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc1039; GFX9-NEXT:    v_cmp_ngt_f16_e32 vcc, v0, v11040; GFX9-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc1041; GFX9-NEXT:    s_mov_b32 s4, 0x50401001042; GFX9-NEXT:    v_perm_b32 v0, v2, v0, s41043; GFX9-NEXT:    s_setpc_b64 s[30:31]1044;1045; GFX12-TRUE16-LABEL: v_test_fmin_legacy_ule_v2f16_nsz_flag:1046; GFX12-TRUE16:       ; %bb.0:1047; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x01048; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x01049; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x01050; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x01051; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x01052; GFX12-TRUE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v0.h, v1.h1053; GFX12-TRUE16-NEXT:    v_cmp_ngt_f16_e64 s0, v0.l, v1.l1054; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)1055; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v1.h, v0.h, vcc_lo1056; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)1057; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)1058; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v1.l, v0.l, s01059; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]1060;1061; GFX12-FAKE16-LABEL: v_test_fmin_legacy_ule_v2f16_nsz_flag:1062; GFX12-FAKE16:       ; %bb.0:1063; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x01064; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x01065; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x01066; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x01067; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x01068; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v11069; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v01070; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)1071; GFX12-FAKE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v3, v21072; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)1073; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc_lo1074; GFX12-FAKE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v0, v11075; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)1076; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo1077; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)1078; GFX12-FAKE16-NEXT:    v_perm_b32 v0, v2, v0, 0x50401001079; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]1080  %cmp = fcmp ule <2 x half> %a, %b1081  %val = select nsz <2 x i1> %cmp, <2 x half> %a, <2 x half> %b1082  ret <2 x half> %val1083}1084 1085define <2 x half> @v_test_fmin_legacy_ule_v2f16_nnan_nsz_flag(<2 x half> %a, <2 x half> %b) {1086; GFX7-LABEL: v_test_fmin_legacy_ule_v2f16_nnan_nsz_flag:1087; GFX7:       ; %bb.0:1088; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1089; GFX7-NEXT:    v_cvt_f16_f32_e32 v3, v31090; GFX7-NEXT:    v_cvt_f16_f32_e32 v2, v21091; GFX7-NEXT:    v_cvt_f16_f32_e32 v0, v01092; GFX7-NEXT:    v_cvt_f16_f32_e32 v1, v11093; GFX7-NEXT:    v_cvt_f32_f16_e32 v3, v31094; GFX7-NEXT:    v_cvt_f32_f16_e32 v2, v21095; GFX7-NEXT:    v_cvt_f32_f16_e32 v0, v01096; GFX7-NEXT:    v_cvt_f32_f16_e32 v1, v11097; GFX7-NEXT:    v_min_f32_e32 v0, v0, v21098; GFX7-NEXT:    v_min_f32_e32 v1, v1, v31099; GFX7-NEXT:    s_setpc_b64 s[30:31]1100;1101; GFX9-LABEL: v_test_fmin_legacy_ule_v2f16_nnan_nsz_flag:1102; GFX9:       ; %bb.0:1103; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1104; GFX9-NEXT:    v_pk_min_f16 v0, v0, v11105; GFX9-NEXT:    s_setpc_b64 s[30:31]1106;1107; GFX12-LABEL: v_test_fmin_legacy_ule_v2f16_nnan_nsz_flag:1108; GFX12:       ; %bb.0:1109; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x01110; GFX12-NEXT:    s_wait_expcnt 0x01111; GFX12-NEXT:    s_wait_samplecnt 0x01112; GFX12-NEXT:    s_wait_bvhcnt 0x01113; GFX12-NEXT:    s_wait_kmcnt 0x01114; GFX12-NEXT:    v_pk_min_num_f16 v0, v0, v11115; GFX12-NEXT:    s_setpc_b64 s[30:31]1116  %cmp = fcmp ule <2 x half> %a, %b1117  %val = select nnan nsz <2 x i1> %cmp, <2 x half> %a, <2 x half> %b1118  ret <2 x half> %val1119}1120 1121define <2 x half> @v_test_fmax_legacy_uge_v2f16_safe(<2 x half> %a, <2 x half> %b) {1122; GFX7-LABEL: v_test_fmax_legacy_uge_v2f16_safe:1123; GFX7:       ; %bb.0:1124; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1125; GFX7-NEXT:    v_cvt_f16_f32_e32 v1, v11126; GFX7-NEXT:    v_cvt_f16_f32_e32 v0, v01127; GFX7-NEXT:    v_cvt_f16_f32_e32 v2, v21128; GFX7-NEXT:    v_cvt_f16_f32_e32 v3, v31129; GFX7-NEXT:    v_cvt_f32_f16_e32 v1, v11130; GFX7-NEXT:    v_cvt_f32_f16_e32 v0, v01131; GFX7-NEXT:    v_cvt_f32_f16_e32 v2, v21132; GFX7-NEXT:    v_cvt_f32_f16_e32 v3, v31133; GFX7-NEXT:    v_max_legacy_f32_e32 v0, v2, v01134; GFX7-NEXT:    v_max_legacy_f32_e32 v1, v3, v11135; GFX7-NEXT:    s_setpc_b64 s[30:31]1136;1137; GFX9-LABEL: v_test_fmax_legacy_uge_v2f16_safe:1138; GFX9:       ; %bb.0:1139; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1140; GFX9-NEXT:    v_lshrrev_b32_e32 v2, 16, v11141; GFX9-NEXT:    v_lshrrev_b32_e32 v3, 16, v01142; GFX9-NEXT:    v_cmp_nlt_f16_e32 vcc, v3, v21143; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc1144; GFX9-NEXT:    v_cmp_nlt_f16_e32 vcc, v0, v11145; GFX9-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc1146; GFX9-NEXT:    s_mov_b32 s4, 0x50401001147; GFX9-NEXT:    v_perm_b32 v0, v2, v0, s41148; GFX9-NEXT:    s_setpc_b64 s[30:31]1149;1150; GFX12-TRUE16-LABEL: v_test_fmax_legacy_uge_v2f16_safe:1151; GFX12-TRUE16:       ; %bb.0:1152; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x01153; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x01154; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x01155; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x01156; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x01157; GFX12-TRUE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v0.h, v1.h1158; GFX12-TRUE16-NEXT:    v_cmp_nlt_f16_e64 s0, v0.l, v1.l1159; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)1160; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v1.h, v0.h, vcc_lo1161; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)1162; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)1163; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v1.l, v0.l, s01164; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]1165;1166; GFX12-FAKE16-LABEL: v_test_fmax_legacy_uge_v2f16_safe:1167; GFX12-FAKE16:       ; %bb.0:1168; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x01169; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x01170; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x01171; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x01172; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x01173; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v11174; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v01175; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)1176; GFX12-FAKE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v3, v21177; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)1178; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc_lo1179; GFX12-FAKE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v0, v11180; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)1181; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo1182; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)1183; GFX12-FAKE16-NEXT:    v_perm_b32 v0, v2, v0, 0x50401001184; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]1185  %cmp = fcmp uge <2 x half> %a, %b1186  %val = select <2 x i1> %cmp, <2 x half> %a, <2 x half> %b1187  ret <2 x half> %val1188}1189 1190define <2 x half> @v_test_fmax_legacy_uge_v2f16_nnan_flag(<2 x half> %a, <2 x half> %b) {1191; GFX7-LABEL: v_test_fmax_legacy_uge_v2f16_nnan_flag:1192; GFX7:       ; %bb.0:1193; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1194; GFX7-NEXT:    v_cvt_f16_f32_e32 v1, v11195; GFX7-NEXT:    v_cvt_f16_f32_e32 v0, v01196; GFX7-NEXT:    v_cvt_f16_f32_e32 v2, v21197; GFX7-NEXT:    v_cvt_f16_f32_e32 v3, v31198; GFX7-NEXT:    v_cvt_f32_f16_e32 v1, v11199; GFX7-NEXT:    v_cvt_f32_f16_e32 v0, v01200; GFX7-NEXT:    v_cvt_f32_f16_e32 v2, v21201; GFX7-NEXT:    v_cvt_f32_f16_e32 v3, v31202; GFX7-NEXT:    v_max_legacy_f32_e32 v0, v2, v01203; GFX7-NEXT:    v_max_legacy_f32_e32 v1, v3, v11204; GFX7-NEXT:    s_setpc_b64 s[30:31]1205;1206; GFX9-LABEL: v_test_fmax_legacy_uge_v2f16_nnan_flag:1207; GFX9:       ; %bb.0:1208; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1209; GFX9-NEXT:    v_lshrrev_b32_e32 v2, 16, v11210; GFX9-NEXT:    v_lshrrev_b32_e32 v3, 16, v01211; GFX9-NEXT:    v_cmp_nlt_f16_e32 vcc, v3, v21212; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc1213; GFX9-NEXT:    v_cmp_nlt_f16_e32 vcc, v0, v11214; GFX9-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc1215; GFX9-NEXT:    s_mov_b32 s4, 0x50401001216; GFX9-NEXT:    v_perm_b32 v0, v2, v0, s41217; GFX9-NEXT:    s_setpc_b64 s[30:31]1218;1219; GFX12-TRUE16-LABEL: v_test_fmax_legacy_uge_v2f16_nnan_flag:1220; GFX12-TRUE16:       ; %bb.0:1221; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x01222; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x01223; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x01224; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x01225; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x01226; GFX12-TRUE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v0.h, v1.h1227; GFX12-TRUE16-NEXT:    v_cmp_nlt_f16_e64 s0, v0.l, v1.l1228; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)1229; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v1.h, v0.h, vcc_lo1230; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)1231; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)1232; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v1.l, v0.l, s01233; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]1234;1235; GFX12-FAKE16-LABEL: v_test_fmax_legacy_uge_v2f16_nnan_flag:1236; GFX12-FAKE16:       ; %bb.0:1237; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x01238; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x01239; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x01240; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x01241; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x01242; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v11243; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v01244; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)1245; GFX12-FAKE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v3, v21246; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)1247; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc_lo1248; GFX12-FAKE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v0, v11249; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)1250; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo1251; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)1252; GFX12-FAKE16-NEXT:    v_perm_b32 v0, v2, v0, 0x50401001253; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]1254  %cmp = fcmp uge <2 x half> %a, %b1255  %val = select nnan <2 x i1> %cmp, <2 x half> %a, <2 x half> %b1256  ret <2 x half> %val1257}1258 1259define <2 x half> @v_test_fmax_legacy_uge_v2f16_nsz_flag(<2 x half> %a, <2 x half> %b) {1260; GFX7-LABEL: v_test_fmax_legacy_uge_v2f16_nsz_flag:1261; GFX7:       ; %bb.0:1262; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1263; GFX7-NEXT:    v_cvt_f16_f32_e32 v1, v11264; GFX7-NEXT:    v_cvt_f16_f32_e32 v0, v01265; GFX7-NEXT:    v_cvt_f16_f32_e32 v2, v21266; GFX7-NEXT:    v_cvt_f16_f32_e32 v3, v31267; GFX7-NEXT:    v_cvt_f32_f16_e32 v1, v11268; GFX7-NEXT:    v_cvt_f32_f16_e32 v0, v01269; GFX7-NEXT:    v_cvt_f32_f16_e32 v2, v21270; GFX7-NEXT:    v_cvt_f32_f16_e32 v3, v31271; GFX7-NEXT:    v_max_legacy_f32_e32 v0, v2, v01272; GFX7-NEXT:    v_max_legacy_f32_e32 v1, v3, v11273; GFX7-NEXT:    s_setpc_b64 s[30:31]1274;1275; GFX9-LABEL: v_test_fmax_legacy_uge_v2f16_nsz_flag:1276; GFX9:       ; %bb.0:1277; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1278; GFX9-NEXT:    v_lshrrev_b32_e32 v2, 16, v11279; GFX9-NEXT:    v_lshrrev_b32_e32 v3, 16, v01280; GFX9-NEXT:    v_cmp_nlt_f16_e32 vcc, v3, v21281; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc1282; GFX9-NEXT:    v_cmp_nlt_f16_e32 vcc, v0, v11283; GFX9-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc1284; GFX9-NEXT:    s_mov_b32 s4, 0x50401001285; GFX9-NEXT:    v_perm_b32 v0, v2, v0, s41286; GFX9-NEXT:    s_setpc_b64 s[30:31]1287;1288; GFX12-TRUE16-LABEL: v_test_fmax_legacy_uge_v2f16_nsz_flag:1289; GFX12-TRUE16:       ; %bb.0:1290; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x01291; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x01292; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x01293; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x01294; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x01295; GFX12-TRUE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v0.h, v1.h1296; GFX12-TRUE16-NEXT:    v_cmp_nlt_f16_e64 s0, v0.l, v1.l1297; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)1298; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v1.h, v0.h, vcc_lo1299; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)1300; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)1301; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v1.l, v0.l, s01302; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]1303;1304; GFX12-FAKE16-LABEL: v_test_fmax_legacy_uge_v2f16_nsz_flag:1305; GFX12-FAKE16:       ; %bb.0:1306; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x01307; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x01308; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x01309; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x01310; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x01311; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v11312; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v01313; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)1314; GFX12-FAKE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v3, v21315; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)1316; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc_lo1317; GFX12-FAKE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v0, v11318; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)1319; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo1320; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)1321; GFX12-FAKE16-NEXT:    v_perm_b32 v0, v2, v0, 0x50401001322; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]1323  %cmp = fcmp uge <2 x half> %a, %b1324  %val = select nsz <2 x i1> %cmp, <2 x half> %a, <2 x half> %b1325  ret <2 x half> %val1326}1327 1328define <2 x half> @v_test_fmax_legacy_uge_v2f16_nnan_nsz_flag(<2 x half> %a, <2 x half> %b) {1329; GFX7-LABEL: v_test_fmax_legacy_uge_v2f16_nnan_nsz_flag:1330; GFX7:       ; %bb.0:1331; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1332; GFX7-NEXT:    v_cvt_f16_f32_e32 v3, v31333; GFX7-NEXT:    v_cvt_f16_f32_e32 v2, v21334; GFX7-NEXT:    v_cvt_f16_f32_e32 v0, v01335; GFX7-NEXT:    v_cvt_f16_f32_e32 v1, v11336; GFX7-NEXT:    v_cvt_f32_f16_e32 v3, v31337; GFX7-NEXT:    v_cvt_f32_f16_e32 v2, v21338; GFX7-NEXT:    v_cvt_f32_f16_e32 v0, v01339; GFX7-NEXT:    v_cvt_f32_f16_e32 v1, v11340; GFX7-NEXT:    v_max_f32_e32 v0, v0, v21341; GFX7-NEXT:    v_max_f32_e32 v1, v1, v31342; GFX7-NEXT:    s_setpc_b64 s[30:31]1343;1344; GFX9-LABEL: v_test_fmax_legacy_uge_v2f16_nnan_nsz_flag:1345; GFX9:       ; %bb.0:1346; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1347; GFX9-NEXT:    v_pk_max_f16 v0, v0, v11348; GFX9-NEXT:    s_setpc_b64 s[30:31]1349;1350; GFX12-LABEL: v_test_fmax_legacy_uge_v2f16_nnan_nsz_flag:1351; GFX12:       ; %bb.0:1352; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x01353; GFX12-NEXT:    s_wait_expcnt 0x01354; GFX12-NEXT:    s_wait_samplecnt 0x01355; GFX12-NEXT:    s_wait_bvhcnt 0x01356; GFX12-NEXT:    s_wait_kmcnt 0x01357; GFX12-NEXT:    v_pk_max_num_f16 v0, v0, v11358; GFX12-NEXT:    s_setpc_b64 s[30:31]1359  %cmp = fcmp uge <2 x half> %a, %b1360  %val = select nnan nsz <2 x i1> %cmp, <2 x half> %a, <2 x half> %b1361  ret <2 x half> %val1362}1363 1364define <4 x half> @v_test_fmin_legacy_ule_v4f16_safe(<4 x half> %a, <4 x half> %b) {1365; GFX7-LABEL: v_test_fmin_legacy_ule_v4f16_safe:1366; GFX7:       ; %bb.0:1367; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1368; GFX7-NEXT:    v_cvt_f16_f32_e32 v3, v31369; GFX7-NEXT:    v_cvt_f16_f32_e32 v2, v21370; GFX7-NEXT:    v_cvt_f16_f32_e32 v7, v71371; GFX7-NEXT:    v_cvt_f16_f32_e32 v6, v61372; GFX7-NEXT:    v_cvt_f16_f32_e32 v1, v11373; GFX7-NEXT:    v_cvt_f16_f32_e32 v0, v01374; GFX7-NEXT:    v_cvt_f16_f32_e32 v4, v41375; GFX7-NEXT:    v_cvt_f16_f32_e32 v5, v51376; GFX7-NEXT:    v_cvt_f32_f16_e32 v3, v31377; GFX7-NEXT:    v_cvt_f32_f16_e32 v2, v21378; GFX7-NEXT:    v_cvt_f32_f16_e32 v1, v11379; GFX7-NEXT:    v_cvt_f32_f16_e32 v0, v01380; GFX7-NEXT:    v_cvt_f32_f16_e32 v4, v41381; GFX7-NEXT:    v_cvt_f32_f16_e32 v5, v51382; GFX7-NEXT:    v_cvt_f32_f16_e32 v6, v61383; GFX7-NEXT:    v_cvt_f32_f16_e32 v7, v71384; GFX7-NEXT:    v_min_legacy_f32_e32 v0, v4, v01385; GFX7-NEXT:    v_min_legacy_f32_e32 v1, v5, v11386; GFX7-NEXT:    v_min_legacy_f32_e32 v2, v6, v21387; GFX7-NEXT:    v_min_legacy_f32_e32 v3, v7, v31388; GFX7-NEXT:    s_setpc_b64 s[30:31]1389;1390; GFX9-LABEL: v_test_fmin_legacy_ule_v4f16_safe:1391; GFX9:       ; %bb.0:1392; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1393; GFX9-NEXT:    v_lshrrev_b32_e32 v6, 16, v31394; GFX9-NEXT:    v_lshrrev_b32_e32 v7, 16, v11395; GFX9-NEXT:    v_lshrrev_b32_e32 v4, 16, v21396; GFX9-NEXT:    v_lshrrev_b32_e32 v5, 16, v01397; GFX9-NEXT:    v_cmp_ngt_f16_e32 vcc, v7, v61398; GFX9-NEXT:    v_cndmask_b32_e32 v6, v6, v7, vcc1399; GFX9-NEXT:    v_cmp_ngt_f16_e32 vcc, v5, v41400; GFX9-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc1401; GFX9-NEXT:    v_cmp_ngt_f16_e32 vcc, v1, v31402; GFX9-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc1403; GFX9-NEXT:    v_cmp_ngt_f16_e32 vcc, v0, v21404; GFX9-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc1405; GFX9-NEXT:    s_mov_b32 s4, 0x50401001406; GFX9-NEXT:    v_perm_b32 v0, v4, v0, s41407; GFX9-NEXT:    v_perm_b32 v1, v6, v1, s41408; GFX9-NEXT:    s_setpc_b64 s[30:31]1409;1410; GFX12-TRUE16-LABEL: v_test_fmin_legacy_ule_v4f16_safe:1411; GFX12-TRUE16:       ; %bb.0:1412; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x01413; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x01414; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x01415; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x01416; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x01417; GFX12-TRUE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v1.h, v3.h1418; GFX12-TRUE16-NEXT:    v_cmp_ngt_f16_e64 s0, v0.h, v2.h1419; GFX12-TRUE16-NEXT:    v_cmp_ngt_f16_e64 s1, v0.l, v2.l1420; GFX12-TRUE16-NEXT:    v_cmp_ngt_f16_e64 s2, v1.l, v3.l1421; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)1422; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.h, v3.h, v1.h, vcc_lo1423; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)1424; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v2.h, v0.h, s01425; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v2.l, v0.l, s11426; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.l, v3.l, v1.l, s21427; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]1428;1429; GFX12-FAKE16-LABEL: v_test_fmin_legacy_ule_v4f16_safe:1430; GFX12-FAKE16:       ; %bb.0:1431; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x01432; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x01433; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x01434; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x01435; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x01436; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v4, 16, v31437; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 16, v11438; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v21439; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 16, v01440; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)1441; GFX12-FAKE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v5, v41442; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)1443; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc_lo1444; GFX12-FAKE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v7, v61445; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)1446; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v6, v7, vcc_lo1447; GFX12-FAKE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v0, v21448; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)1449; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo1450; GFX12-FAKE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v1, v31451; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)1452; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc_lo1453; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)1454; GFX12-FAKE16-NEXT:    v_perm_b32 v0, v5, v0, 0x50401001455; GFX12-FAKE16-NEXT:    v_perm_b32 v1, v4, v1, 0x50401001456; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]1457  %cmp = fcmp ule <4 x half> %a, %b1458  %val = select <4 x i1> %cmp, <4 x half> %a, <4 x half> %b1459  ret <4 x half> %val1460}1461 1462define <4 x half> @v_test_fmin_legacy_ule_v4f16_nnan_flag(<4 x half> %a, <4 x half> %b) {1463; GFX7-LABEL: v_test_fmin_legacy_ule_v4f16_nnan_flag:1464; GFX7:       ; %bb.0:1465; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1466; GFX7-NEXT:    v_cvt_f16_f32_e32 v3, v31467; GFX7-NEXT:    v_cvt_f16_f32_e32 v2, v21468; GFX7-NEXT:    v_cvt_f16_f32_e32 v7, v71469; GFX7-NEXT:    v_cvt_f16_f32_e32 v6, v61470; GFX7-NEXT:    v_cvt_f16_f32_e32 v1, v11471; GFX7-NEXT:    v_cvt_f16_f32_e32 v0, v01472; GFX7-NEXT:    v_cvt_f16_f32_e32 v4, v41473; GFX7-NEXT:    v_cvt_f16_f32_e32 v5, v51474; GFX7-NEXT:    v_cvt_f32_f16_e32 v3, v31475; GFX7-NEXT:    v_cvt_f32_f16_e32 v2, v21476; GFX7-NEXT:    v_cvt_f32_f16_e32 v1, v11477; GFX7-NEXT:    v_cvt_f32_f16_e32 v0, v01478; GFX7-NEXT:    v_cvt_f32_f16_e32 v4, v41479; GFX7-NEXT:    v_cvt_f32_f16_e32 v5, v51480; GFX7-NEXT:    v_cvt_f32_f16_e32 v6, v61481; GFX7-NEXT:    v_cvt_f32_f16_e32 v7, v71482; GFX7-NEXT:    v_min_legacy_f32_e32 v0, v4, v01483; GFX7-NEXT:    v_min_legacy_f32_e32 v1, v5, v11484; GFX7-NEXT:    v_min_legacy_f32_e32 v2, v6, v21485; GFX7-NEXT:    v_min_legacy_f32_e32 v3, v7, v31486; GFX7-NEXT:    s_setpc_b64 s[30:31]1487;1488; GFX9-LABEL: v_test_fmin_legacy_ule_v4f16_nnan_flag:1489; GFX9:       ; %bb.0:1490; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1491; GFX9-NEXT:    v_lshrrev_b32_e32 v6, 16, v31492; GFX9-NEXT:    v_lshrrev_b32_e32 v7, 16, v11493; GFX9-NEXT:    v_lshrrev_b32_e32 v4, 16, v21494; GFX9-NEXT:    v_lshrrev_b32_e32 v5, 16, v01495; GFX9-NEXT:    v_cmp_ngt_f16_e32 vcc, v7, v61496; GFX9-NEXT:    v_cndmask_b32_e32 v6, v6, v7, vcc1497; GFX9-NEXT:    v_cmp_ngt_f16_e32 vcc, v5, v41498; GFX9-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc1499; GFX9-NEXT:    v_cmp_ngt_f16_e32 vcc, v1, v31500; GFX9-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc1501; GFX9-NEXT:    v_cmp_ngt_f16_e32 vcc, v0, v21502; GFX9-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc1503; GFX9-NEXT:    s_mov_b32 s4, 0x50401001504; GFX9-NEXT:    v_perm_b32 v0, v4, v0, s41505; GFX9-NEXT:    v_perm_b32 v1, v6, v1, s41506; GFX9-NEXT:    s_setpc_b64 s[30:31]1507;1508; GFX12-TRUE16-LABEL: v_test_fmin_legacy_ule_v4f16_nnan_flag:1509; GFX12-TRUE16:       ; %bb.0:1510; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x01511; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x01512; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x01513; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x01514; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x01515; GFX12-TRUE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v1.h, v3.h1516; GFX12-TRUE16-NEXT:    v_cmp_ngt_f16_e64 s0, v0.h, v2.h1517; GFX12-TRUE16-NEXT:    v_cmp_ngt_f16_e64 s1, v0.l, v2.l1518; GFX12-TRUE16-NEXT:    v_cmp_ngt_f16_e64 s2, v1.l, v3.l1519; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)1520; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.h, v3.h, v1.h, vcc_lo1521; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)1522; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v2.h, v0.h, s01523; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v2.l, v0.l, s11524; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.l, v3.l, v1.l, s21525; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]1526;1527; GFX12-FAKE16-LABEL: v_test_fmin_legacy_ule_v4f16_nnan_flag:1528; GFX12-FAKE16:       ; %bb.0:1529; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x01530; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x01531; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x01532; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x01533; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x01534; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v4, 16, v31535; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 16, v11536; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v21537; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 16, v01538; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)1539; GFX12-FAKE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v5, v41540; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)1541; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc_lo1542; GFX12-FAKE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v7, v61543; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)1544; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v6, v7, vcc_lo1545; GFX12-FAKE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v0, v21546; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)1547; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo1548; GFX12-FAKE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v1, v31549; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)1550; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc_lo1551; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)1552; GFX12-FAKE16-NEXT:    v_perm_b32 v0, v5, v0, 0x50401001553; GFX12-FAKE16-NEXT:    v_perm_b32 v1, v4, v1, 0x50401001554; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]1555  %cmp = fcmp ule <4 x half> %a, %b1556  %val = select nnan <4 x i1> %cmp, <4 x half> %a, <4 x half> %b1557  ret <4 x half> %val1558}1559 1560define <4 x half> @v_test_fmin_legacy_ule_v4f16_nsz_flag(<4 x half> %a, <4 x half> %b) {1561; GFX7-LABEL: v_test_fmin_legacy_ule_v4f16_nsz_flag:1562; GFX7:       ; %bb.0:1563; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1564; GFX7-NEXT:    v_cvt_f16_f32_e32 v3, v31565; GFX7-NEXT:    v_cvt_f16_f32_e32 v2, v21566; GFX7-NEXT:    v_cvt_f16_f32_e32 v7, v71567; GFX7-NEXT:    v_cvt_f16_f32_e32 v6, v61568; GFX7-NEXT:    v_cvt_f16_f32_e32 v1, v11569; GFX7-NEXT:    v_cvt_f16_f32_e32 v0, v01570; GFX7-NEXT:    v_cvt_f16_f32_e32 v4, v41571; GFX7-NEXT:    v_cvt_f16_f32_e32 v5, v51572; GFX7-NEXT:    v_cvt_f32_f16_e32 v3, v31573; GFX7-NEXT:    v_cvt_f32_f16_e32 v2, v21574; GFX7-NEXT:    v_cvt_f32_f16_e32 v1, v11575; GFX7-NEXT:    v_cvt_f32_f16_e32 v0, v01576; GFX7-NEXT:    v_cvt_f32_f16_e32 v4, v41577; GFX7-NEXT:    v_cvt_f32_f16_e32 v5, v51578; GFX7-NEXT:    v_cvt_f32_f16_e32 v6, v61579; GFX7-NEXT:    v_cvt_f32_f16_e32 v7, v71580; GFX7-NEXT:    v_min_legacy_f32_e32 v0, v4, v01581; GFX7-NEXT:    v_min_legacy_f32_e32 v1, v5, v11582; GFX7-NEXT:    v_min_legacy_f32_e32 v2, v6, v21583; GFX7-NEXT:    v_min_legacy_f32_e32 v3, v7, v31584; GFX7-NEXT:    s_setpc_b64 s[30:31]1585;1586; GFX9-LABEL: v_test_fmin_legacy_ule_v4f16_nsz_flag:1587; GFX9:       ; %bb.0:1588; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1589; GFX9-NEXT:    v_lshrrev_b32_e32 v6, 16, v31590; GFX9-NEXT:    v_lshrrev_b32_e32 v7, 16, v11591; GFX9-NEXT:    v_lshrrev_b32_e32 v4, 16, v21592; GFX9-NEXT:    v_lshrrev_b32_e32 v5, 16, v01593; GFX9-NEXT:    v_cmp_ngt_f16_e32 vcc, v7, v61594; GFX9-NEXT:    v_cndmask_b32_e32 v6, v6, v7, vcc1595; GFX9-NEXT:    v_cmp_ngt_f16_e32 vcc, v5, v41596; GFX9-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc1597; GFX9-NEXT:    v_cmp_ngt_f16_e32 vcc, v1, v31598; GFX9-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc1599; GFX9-NEXT:    v_cmp_ngt_f16_e32 vcc, v0, v21600; GFX9-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc1601; GFX9-NEXT:    s_mov_b32 s4, 0x50401001602; GFX9-NEXT:    v_perm_b32 v0, v4, v0, s41603; GFX9-NEXT:    v_perm_b32 v1, v6, v1, s41604; GFX9-NEXT:    s_setpc_b64 s[30:31]1605;1606; GFX12-TRUE16-LABEL: v_test_fmin_legacy_ule_v4f16_nsz_flag:1607; GFX12-TRUE16:       ; %bb.0:1608; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x01609; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x01610; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x01611; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x01612; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x01613; GFX12-TRUE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v1.h, v3.h1614; GFX12-TRUE16-NEXT:    v_cmp_ngt_f16_e64 s0, v0.h, v2.h1615; GFX12-TRUE16-NEXT:    v_cmp_ngt_f16_e64 s1, v0.l, v2.l1616; GFX12-TRUE16-NEXT:    v_cmp_ngt_f16_e64 s2, v1.l, v3.l1617; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)1618; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.h, v3.h, v1.h, vcc_lo1619; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)1620; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v2.h, v0.h, s01621; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v2.l, v0.l, s11622; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.l, v3.l, v1.l, s21623; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]1624;1625; GFX12-FAKE16-LABEL: v_test_fmin_legacy_ule_v4f16_nsz_flag:1626; GFX12-FAKE16:       ; %bb.0:1627; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x01628; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x01629; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x01630; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x01631; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x01632; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v4, 16, v31633; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 16, v11634; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v21635; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 16, v01636; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)1637; GFX12-FAKE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v5, v41638; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)1639; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc_lo1640; GFX12-FAKE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v7, v61641; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)1642; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v6, v7, vcc_lo1643; GFX12-FAKE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v0, v21644; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)1645; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo1646; GFX12-FAKE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v1, v31647; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)1648; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc_lo1649; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)1650; GFX12-FAKE16-NEXT:    v_perm_b32 v0, v5, v0, 0x50401001651; GFX12-FAKE16-NEXT:    v_perm_b32 v1, v4, v1, 0x50401001652; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]1653  %cmp = fcmp ule <4 x half> %a, %b1654  %val = select nsz <4 x i1> %cmp, <4 x half> %a, <4 x half> %b1655  ret <4 x half> %val1656}1657 1658define <4 x half> @v_test_fmin_legacy_ule_v4f16_nnan_nsz_flag(<4 x half> %a, <4 x half> %b) {1659; GFX7-LABEL: v_test_fmin_legacy_ule_v4f16_nnan_nsz_flag:1660; GFX7:       ; %bb.0:1661; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1662; GFX7-NEXT:    v_cvt_f16_f32_e32 v7, v71663; GFX7-NEXT:    v_cvt_f16_f32_e32 v6, v61664; GFX7-NEXT:    v_cvt_f16_f32_e32 v3, v31665; GFX7-NEXT:    v_cvt_f16_f32_e32 v2, v21666; GFX7-NEXT:    v_cvt_f16_f32_e32 v5, v51667; GFX7-NEXT:    v_cvt_f16_f32_e32 v4, v41668; GFX7-NEXT:    v_cvt_f16_f32_e32 v0, v01669; GFX7-NEXT:    v_cvt_f16_f32_e32 v1, v11670; GFX7-NEXT:    v_cvt_f32_f16_e32 v7, v71671; GFX7-NEXT:    v_cvt_f32_f16_e32 v6, v61672; GFX7-NEXT:    v_cvt_f32_f16_e32 v5, v51673; GFX7-NEXT:    v_cvt_f32_f16_e32 v4, v41674; GFX7-NEXT:    v_cvt_f32_f16_e32 v0, v01675; GFX7-NEXT:    v_cvt_f32_f16_e32 v1, v11676; GFX7-NEXT:    v_cvt_f32_f16_e32 v2, v21677; GFX7-NEXT:    v_cvt_f32_f16_e32 v3, v31678; GFX7-NEXT:    v_min_f32_e32 v0, v0, v41679; GFX7-NEXT:    v_min_f32_e32 v1, v1, v51680; GFX7-NEXT:    v_min_f32_e32 v2, v2, v61681; GFX7-NEXT:    v_min_f32_e32 v3, v3, v71682; GFX7-NEXT:    s_setpc_b64 s[30:31]1683;1684; GFX9-LABEL: v_test_fmin_legacy_ule_v4f16_nnan_nsz_flag:1685; GFX9:       ; %bb.0:1686; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1687; GFX9-NEXT:    v_pk_min_f16 v0, v0, v21688; GFX9-NEXT:    v_pk_min_f16 v1, v1, v31689; GFX9-NEXT:    s_setpc_b64 s[30:31]1690;1691; GFX12-LABEL: v_test_fmin_legacy_ule_v4f16_nnan_nsz_flag:1692; GFX12:       ; %bb.0:1693; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x01694; GFX12-NEXT:    s_wait_expcnt 0x01695; GFX12-NEXT:    s_wait_samplecnt 0x01696; GFX12-NEXT:    s_wait_bvhcnt 0x01697; GFX12-NEXT:    s_wait_kmcnt 0x01698; GFX12-NEXT:    v_pk_min_num_f16 v0, v0, v21699; GFX12-NEXT:    v_pk_min_num_f16 v1, v1, v31700; GFX12-NEXT:    s_setpc_b64 s[30:31]1701  %cmp = fcmp ule <4 x half> %a, %b1702  %val = select nnan nsz <4 x i1> %cmp, <4 x half> %a, <4 x half> %b1703  ret <4 x half> %val1704}1705 1706define <4 x half> @v_test_fmax_legacy_uge_v4f16_safe(<4 x half> %a, <4 x half> %b) {1707; GFX7-LABEL: v_test_fmax_legacy_uge_v4f16_safe:1708; GFX7:       ; %bb.0:1709; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1710; GFX7-NEXT:    v_cvt_f16_f32_e32 v3, v31711; GFX7-NEXT:    v_cvt_f16_f32_e32 v2, v21712; GFX7-NEXT:    v_cvt_f16_f32_e32 v7, v71713; GFX7-NEXT:    v_cvt_f16_f32_e32 v6, v61714; GFX7-NEXT:    v_cvt_f16_f32_e32 v1, v11715; GFX7-NEXT:    v_cvt_f16_f32_e32 v0, v01716; GFX7-NEXT:    v_cvt_f16_f32_e32 v4, v41717; GFX7-NEXT:    v_cvt_f16_f32_e32 v5, v51718; GFX7-NEXT:    v_cvt_f32_f16_e32 v3, v31719; GFX7-NEXT:    v_cvt_f32_f16_e32 v2, v21720; GFX7-NEXT:    v_cvt_f32_f16_e32 v1, v11721; GFX7-NEXT:    v_cvt_f32_f16_e32 v0, v01722; GFX7-NEXT:    v_cvt_f32_f16_e32 v4, v41723; GFX7-NEXT:    v_cvt_f32_f16_e32 v5, v51724; GFX7-NEXT:    v_cvt_f32_f16_e32 v6, v61725; GFX7-NEXT:    v_cvt_f32_f16_e32 v7, v71726; GFX7-NEXT:    v_max_legacy_f32_e32 v0, v4, v01727; GFX7-NEXT:    v_max_legacy_f32_e32 v1, v5, v11728; GFX7-NEXT:    v_max_legacy_f32_e32 v2, v6, v21729; GFX7-NEXT:    v_max_legacy_f32_e32 v3, v7, v31730; GFX7-NEXT:    s_setpc_b64 s[30:31]1731;1732; GFX9-LABEL: v_test_fmax_legacy_uge_v4f16_safe:1733; GFX9:       ; %bb.0:1734; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1735; GFX9-NEXT:    v_lshrrev_b32_e32 v6, 16, v31736; GFX9-NEXT:    v_lshrrev_b32_e32 v7, 16, v11737; GFX9-NEXT:    v_lshrrev_b32_e32 v4, 16, v21738; GFX9-NEXT:    v_lshrrev_b32_e32 v5, 16, v01739; GFX9-NEXT:    v_cmp_nlt_f16_e32 vcc, v7, v61740; GFX9-NEXT:    v_cndmask_b32_e32 v6, v6, v7, vcc1741; GFX9-NEXT:    v_cmp_nlt_f16_e32 vcc, v5, v41742; GFX9-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc1743; GFX9-NEXT:    v_cmp_nlt_f16_e32 vcc, v1, v31744; GFX9-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc1745; GFX9-NEXT:    v_cmp_nlt_f16_e32 vcc, v0, v21746; GFX9-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc1747; GFX9-NEXT:    s_mov_b32 s4, 0x50401001748; GFX9-NEXT:    v_perm_b32 v0, v4, v0, s41749; GFX9-NEXT:    v_perm_b32 v1, v6, v1, s41750; GFX9-NEXT:    s_setpc_b64 s[30:31]1751;1752; GFX12-TRUE16-LABEL: v_test_fmax_legacy_uge_v4f16_safe:1753; GFX12-TRUE16:       ; %bb.0:1754; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x01755; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x01756; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x01757; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x01758; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x01759; GFX12-TRUE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v1.h, v3.h1760; GFX12-TRUE16-NEXT:    v_cmp_nlt_f16_e64 s0, v0.h, v2.h1761; GFX12-TRUE16-NEXT:    v_cmp_nlt_f16_e64 s1, v0.l, v2.l1762; GFX12-TRUE16-NEXT:    v_cmp_nlt_f16_e64 s2, v1.l, v3.l1763; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)1764; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.h, v3.h, v1.h, vcc_lo1765; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)1766; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v2.h, v0.h, s01767; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v2.l, v0.l, s11768; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.l, v3.l, v1.l, s21769; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]1770;1771; GFX12-FAKE16-LABEL: v_test_fmax_legacy_uge_v4f16_safe:1772; GFX12-FAKE16:       ; %bb.0:1773; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x01774; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x01775; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x01776; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x01777; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x01778; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v4, 16, v31779; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 16, v11780; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v21781; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 16, v01782; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)1783; GFX12-FAKE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v5, v41784; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)1785; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc_lo1786; GFX12-FAKE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v7, v61787; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)1788; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v6, v7, vcc_lo1789; GFX12-FAKE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v0, v21790; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)1791; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo1792; GFX12-FAKE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v1, v31793; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)1794; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc_lo1795; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)1796; GFX12-FAKE16-NEXT:    v_perm_b32 v0, v5, v0, 0x50401001797; GFX12-FAKE16-NEXT:    v_perm_b32 v1, v4, v1, 0x50401001798; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]1799  %cmp = fcmp uge <4 x half> %a, %b1800  %val = select <4 x i1> %cmp, <4 x half> %a, <4 x half> %b1801  ret <4 x half> %val1802}1803 1804define <4 x half> @v_test_fmax_legacy_uge_v4f16_nnan_flag(<4 x half> %a, <4 x half> %b) {1805; GFX7-LABEL: v_test_fmax_legacy_uge_v4f16_nnan_flag:1806; GFX7:       ; %bb.0:1807; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1808; GFX7-NEXT:    v_cvt_f16_f32_e32 v3, v31809; GFX7-NEXT:    v_cvt_f16_f32_e32 v2, v21810; GFX7-NEXT:    v_cvt_f16_f32_e32 v7, v71811; GFX7-NEXT:    v_cvt_f16_f32_e32 v6, v61812; GFX7-NEXT:    v_cvt_f16_f32_e32 v1, v11813; GFX7-NEXT:    v_cvt_f16_f32_e32 v0, v01814; GFX7-NEXT:    v_cvt_f16_f32_e32 v4, v41815; GFX7-NEXT:    v_cvt_f16_f32_e32 v5, v51816; GFX7-NEXT:    v_cvt_f32_f16_e32 v3, v31817; GFX7-NEXT:    v_cvt_f32_f16_e32 v2, v21818; GFX7-NEXT:    v_cvt_f32_f16_e32 v1, v11819; GFX7-NEXT:    v_cvt_f32_f16_e32 v0, v01820; GFX7-NEXT:    v_cvt_f32_f16_e32 v4, v41821; GFX7-NEXT:    v_cvt_f32_f16_e32 v5, v51822; GFX7-NEXT:    v_cvt_f32_f16_e32 v6, v61823; GFX7-NEXT:    v_cvt_f32_f16_e32 v7, v71824; GFX7-NEXT:    v_max_legacy_f32_e32 v0, v4, v01825; GFX7-NEXT:    v_max_legacy_f32_e32 v1, v5, v11826; GFX7-NEXT:    v_max_legacy_f32_e32 v2, v6, v21827; GFX7-NEXT:    v_max_legacy_f32_e32 v3, v7, v31828; GFX7-NEXT:    s_setpc_b64 s[30:31]1829;1830; GFX9-LABEL: v_test_fmax_legacy_uge_v4f16_nnan_flag:1831; GFX9:       ; %bb.0:1832; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1833; GFX9-NEXT:    v_lshrrev_b32_e32 v6, 16, v31834; GFX9-NEXT:    v_lshrrev_b32_e32 v7, 16, v11835; GFX9-NEXT:    v_lshrrev_b32_e32 v4, 16, v21836; GFX9-NEXT:    v_lshrrev_b32_e32 v5, 16, v01837; GFX9-NEXT:    v_cmp_nlt_f16_e32 vcc, v7, v61838; GFX9-NEXT:    v_cndmask_b32_e32 v6, v6, v7, vcc1839; GFX9-NEXT:    v_cmp_nlt_f16_e32 vcc, v5, v41840; GFX9-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc1841; GFX9-NEXT:    v_cmp_nlt_f16_e32 vcc, v1, v31842; GFX9-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc1843; GFX9-NEXT:    v_cmp_nlt_f16_e32 vcc, v0, v21844; GFX9-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc1845; GFX9-NEXT:    s_mov_b32 s4, 0x50401001846; GFX9-NEXT:    v_perm_b32 v0, v4, v0, s41847; GFX9-NEXT:    v_perm_b32 v1, v6, v1, s41848; GFX9-NEXT:    s_setpc_b64 s[30:31]1849;1850; GFX12-TRUE16-LABEL: v_test_fmax_legacy_uge_v4f16_nnan_flag:1851; GFX12-TRUE16:       ; %bb.0:1852; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x01853; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x01854; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x01855; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x01856; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x01857; GFX12-TRUE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v1.h, v3.h1858; GFX12-TRUE16-NEXT:    v_cmp_nlt_f16_e64 s0, v0.h, v2.h1859; GFX12-TRUE16-NEXT:    v_cmp_nlt_f16_e64 s1, v0.l, v2.l1860; GFX12-TRUE16-NEXT:    v_cmp_nlt_f16_e64 s2, v1.l, v3.l1861; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)1862; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.h, v3.h, v1.h, vcc_lo1863; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)1864; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v2.h, v0.h, s01865; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v2.l, v0.l, s11866; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.l, v3.l, v1.l, s21867; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]1868;1869; GFX12-FAKE16-LABEL: v_test_fmax_legacy_uge_v4f16_nnan_flag:1870; GFX12-FAKE16:       ; %bb.0:1871; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x01872; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x01873; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x01874; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x01875; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x01876; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v4, 16, v31877; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 16, v11878; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v21879; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 16, v01880; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)1881; GFX12-FAKE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v5, v41882; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)1883; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc_lo1884; GFX12-FAKE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v7, v61885; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)1886; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v6, v7, vcc_lo1887; GFX12-FAKE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v0, v21888; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)1889; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo1890; GFX12-FAKE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v1, v31891; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)1892; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc_lo1893; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)1894; GFX12-FAKE16-NEXT:    v_perm_b32 v0, v5, v0, 0x50401001895; GFX12-FAKE16-NEXT:    v_perm_b32 v1, v4, v1, 0x50401001896; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]1897  %cmp = fcmp uge <4 x half> %a, %b1898  %val = select nnan <4 x i1> %cmp, <4 x half> %a, <4 x half> %b1899  ret <4 x half> %val1900}1901 1902define <4 x half> @v_test_fmax_legacy_uge_v4f16_nsz_flag(<4 x half> %a, <4 x half> %b) {1903; GFX7-LABEL: v_test_fmax_legacy_uge_v4f16_nsz_flag:1904; GFX7:       ; %bb.0:1905; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1906; GFX7-NEXT:    v_cvt_f16_f32_e32 v3, v31907; GFX7-NEXT:    v_cvt_f16_f32_e32 v2, v21908; GFX7-NEXT:    v_cvt_f16_f32_e32 v7, v71909; GFX7-NEXT:    v_cvt_f16_f32_e32 v6, v61910; GFX7-NEXT:    v_cvt_f16_f32_e32 v1, v11911; GFX7-NEXT:    v_cvt_f16_f32_e32 v0, v01912; GFX7-NEXT:    v_cvt_f16_f32_e32 v4, v41913; GFX7-NEXT:    v_cvt_f16_f32_e32 v5, v51914; GFX7-NEXT:    v_cvt_f32_f16_e32 v3, v31915; GFX7-NEXT:    v_cvt_f32_f16_e32 v2, v21916; GFX7-NEXT:    v_cvt_f32_f16_e32 v1, v11917; GFX7-NEXT:    v_cvt_f32_f16_e32 v0, v01918; GFX7-NEXT:    v_cvt_f32_f16_e32 v4, v41919; GFX7-NEXT:    v_cvt_f32_f16_e32 v5, v51920; GFX7-NEXT:    v_cvt_f32_f16_e32 v6, v61921; GFX7-NEXT:    v_cvt_f32_f16_e32 v7, v71922; GFX7-NEXT:    v_max_legacy_f32_e32 v0, v4, v01923; GFX7-NEXT:    v_max_legacy_f32_e32 v1, v5, v11924; GFX7-NEXT:    v_max_legacy_f32_e32 v2, v6, v21925; GFX7-NEXT:    v_max_legacy_f32_e32 v3, v7, v31926; GFX7-NEXT:    s_setpc_b64 s[30:31]1927;1928; GFX9-LABEL: v_test_fmax_legacy_uge_v4f16_nsz_flag:1929; GFX9:       ; %bb.0:1930; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1931; GFX9-NEXT:    v_lshrrev_b32_e32 v6, 16, v31932; GFX9-NEXT:    v_lshrrev_b32_e32 v7, 16, v11933; GFX9-NEXT:    v_lshrrev_b32_e32 v4, 16, v21934; GFX9-NEXT:    v_lshrrev_b32_e32 v5, 16, v01935; GFX9-NEXT:    v_cmp_nlt_f16_e32 vcc, v7, v61936; GFX9-NEXT:    v_cndmask_b32_e32 v6, v6, v7, vcc1937; GFX9-NEXT:    v_cmp_nlt_f16_e32 vcc, v5, v41938; GFX9-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc1939; GFX9-NEXT:    v_cmp_nlt_f16_e32 vcc, v1, v31940; GFX9-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc1941; GFX9-NEXT:    v_cmp_nlt_f16_e32 vcc, v0, v21942; GFX9-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc1943; GFX9-NEXT:    s_mov_b32 s4, 0x50401001944; GFX9-NEXT:    v_perm_b32 v0, v4, v0, s41945; GFX9-NEXT:    v_perm_b32 v1, v6, v1, s41946; GFX9-NEXT:    s_setpc_b64 s[30:31]1947;1948; GFX12-TRUE16-LABEL: v_test_fmax_legacy_uge_v4f16_nsz_flag:1949; GFX12-TRUE16:       ; %bb.0:1950; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x01951; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x01952; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x01953; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x01954; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x01955; GFX12-TRUE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v1.h, v3.h1956; GFX12-TRUE16-NEXT:    v_cmp_nlt_f16_e64 s0, v0.h, v2.h1957; GFX12-TRUE16-NEXT:    v_cmp_nlt_f16_e64 s1, v0.l, v2.l1958; GFX12-TRUE16-NEXT:    v_cmp_nlt_f16_e64 s2, v1.l, v3.l1959; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)1960; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.h, v3.h, v1.h, vcc_lo1961; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)1962; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v2.h, v0.h, s01963; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v2.l, v0.l, s11964; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.l, v3.l, v1.l, s21965; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]1966;1967; GFX12-FAKE16-LABEL: v_test_fmax_legacy_uge_v4f16_nsz_flag:1968; GFX12-FAKE16:       ; %bb.0:1969; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x01970; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x01971; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x01972; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x01973; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x01974; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v4, 16, v31975; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 16, v11976; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v21977; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 16, v01978; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)1979; GFX12-FAKE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v5, v41980; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)1981; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc_lo1982; GFX12-FAKE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v7, v61983; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)1984; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v6, v7, vcc_lo1985; GFX12-FAKE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v0, v21986; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)1987; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo1988; GFX12-FAKE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v1, v31989; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)1990; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc_lo1991; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)1992; GFX12-FAKE16-NEXT:    v_perm_b32 v0, v5, v0, 0x50401001993; GFX12-FAKE16-NEXT:    v_perm_b32 v1, v4, v1, 0x50401001994; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]1995  %cmp = fcmp uge <4 x half> %a, %b1996  %val = select nsz <4 x i1> %cmp, <4 x half> %a, <4 x half> %b1997  ret <4 x half> %val1998}1999 2000define <4 x half> @v_test_fmax_legacy_uge_v4f16_nnan_nsz_flag(<4 x half> %a, <4 x half> %b) {2001; GFX7-LABEL: v_test_fmax_legacy_uge_v4f16_nnan_nsz_flag:2002; GFX7:       ; %bb.0:2003; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2004; GFX7-NEXT:    v_cvt_f16_f32_e32 v7, v72005; GFX7-NEXT:    v_cvt_f16_f32_e32 v6, v62006; GFX7-NEXT:    v_cvt_f16_f32_e32 v3, v32007; GFX7-NEXT:    v_cvt_f16_f32_e32 v2, v22008; GFX7-NEXT:    v_cvt_f16_f32_e32 v5, v52009; GFX7-NEXT:    v_cvt_f16_f32_e32 v4, v42010; GFX7-NEXT:    v_cvt_f16_f32_e32 v0, v02011; GFX7-NEXT:    v_cvt_f16_f32_e32 v1, v12012; GFX7-NEXT:    v_cvt_f32_f16_e32 v7, v72013; GFX7-NEXT:    v_cvt_f32_f16_e32 v6, v62014; GFX7-NEXT:    v_cvt_f32_f16_e32 v5, v52015; GFX7-NEXT:    v_cvt_f32_f16_e32 v4, v42016; GFX7-NEXT:    v_cvt_f32_f16_e32 v0, v02017; GFX7-NEXT:    v_cvt_f32_f16_e32 v1, v12018; GFX7-NEXT:    v_cvt_f32_f16_e32 v2, v22019; GFX7-NEXT:    v_cvt_f32_f16_e32 v3, v32020; GFX7-NEXT:    v_max_f32_e32 v0, v0, v42021; GFX7-NEXT:    v_max_f32_e32 v1, v1, v52022; GFX7-NEXT:    v_max_f32_e32 v2, v2, v62023; GFX7-NEXT:    v_max_f32_e32 v3, v3, v72024; GFX7-NEXT:    s_setpc_b64 s[30:31]2025;2026; GFX9-LABEL: v_test_fmax_legacy_uge_v4f16_nnan_nsz_flag:2027; GFX9:       ; %bb.0:2028; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2029; GFX9-NEXT:    v_pk_max_f16 v0, v0, v22030; GFX9-NEXT:    v_pk_max_f16 v1, v1, v32031; GFX9-NEXT:    s_setpc_b64 s[30:31]2032;2033; GFX12-LABEL: v_test_fmax_legacy_uge_v4f16_nnan_nsz_flag:2034; GFX12:       ; %bb.0:2035; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x02036; GFX12-NEXT:    s_wait_expcnt 0x02037; GFX12-NEXT:    s_wait_samplecnt 0x02038; GFX12-NEXT:    s_wait_bvhcnt 0x02039; GFX12-NEXT:    s_wait_kmcnt 0x02040; GFX12-NEXT:    v_pk_max_num_f16 v0, v0, v22041; GFX12-NEXT:    v_pk_max_num_f16 v1, v1, v32042; GFX12-NEXT:    s_setpc_b64 s[30:31]2043  %cmp = fcmp uge <4 x half> %a, %b2044  %val = select nnan nsz <4 x i1> %cmp, <4 x half> %a, <4 x half> %b2045  ret <4 x half> %val2046}2047 2048define float @v_test_fmin_legacy_uge_f32_nsz_flag__nnan_srcs(float %arg0, float %arg1) {2049; GFX7-LABEL: v_test_fmin_legacy_uge_f32_nsz_flag__nnan_srcs:2050; GFX7:       ; %bb.0:2051; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2052; GFX7-NEXT:    v_add_f32_e32 v0, v0, v02053; GFX7-NEXT:    v_add_f32_e32 v1, v1, v12054; GFX7-NEXT:    v_min_f32_e32 v0, v0, v12055; GFX7-NEXT:    s_setpc_b64 s[30:31]2056;2057; GFX9-LABEL: v_test_fmin_legacy_uge_f32_nsz_flag__nnan_srcs:2058; GFX9:       ; %bb.0:2059; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2060; GFX9-NEXT:    v_add_f32_e32 v0, v0, v02061; GFX9-NEXT:    v_add_f32_e32 v1, v1, v12062; GFX9-NEXT:    v_min_f32_e32 v0, v0, v12063; GFX9-NEXT:    s_setpc_b64 s[30:31]2064;2065; GFX12-LABEL: v_test_fmin_legacy_uge_f32_nsz_flag__nnan_srcs:2066; GFX12:       ; %bb.0:2067; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x02068; GFX12-NEXT:    s_wait_expcnt 0x02069; GFX12-NEXT:    s_wait_samplecnt 0x02070; GFX12-NEXT:    s_wait_bvhcnt 0x02071; GFX12-NEXT:    s_wait_kmcnt 0x02072; GFX12-NEXT:    v_dual_add_f32 v0, v0, v0 :: v_dual_add_f32 v1, v1, v12073; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)2074; GFX12-NEXT:    v_min_num_f32_e32 v0, v0, v12075; GFX12-NEXT:    s_setpc_b64 s[30:31]2076  %a = fadd nnan float %arg0, %arg02077  %b = fadd nnan float %arg1, %arg12078  %cmp = fcmp ule float %a, %b2079  %val = select nsz i1 %cmp, float %a, float %b2080  ret float %val2081}2082 2083define float @v_test_fmax_legacy_uge_f32_nsz_flag__nnan_srcs(float %arg0, float %arg1) {2084; GFX7-LABEL: v_test_fmax_legacy_uge_f32_nsz_flag__nnan_srcs:2085; GFX7:       ; %bb.0:2086; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2087; GFX7-NEXT:    v_add_f32_e32 v0, v0, v02088; GFX7-NEXT:    v_add_f32_e32 v1, v1, v12089; GFX7-NEXT:    v_max_f32_e32 v0, v0, v12090; GFX7-NEXT:    s_setpc_b64 s[30:31]2091;2092; GFX9-LABEL: v_test_fmax_legacy_uge_f32_nsz_flag__nnan_srcs:2093; GFX9:       ; %bb.0:2094; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2095; GFX9-NEXT:    v_add_f32_e32 v0, v0, v02096; GFX9-NEXT:    v_add_f32_e32 v1, v1, v12097; GFX9-NEXT:    v_max_f32_e32 v0, v0, v12098; GFX9-NEXT:    s_setpc_b64 s[30:31]2099;2100; GFX12-LABEL: v_test_fmax_legacy_uge_f32_nsz_flag__nnan_srcs:2101; GFX12:       ; %bb.0:2102; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x02103; GFX12-NEXT:    s_wait_expcnt 0x02104; GFX12-NEXT:    s_wait_samplecnt 0x02105; GFX12-NEXT:    s_wait_bvhcnt 0x02106; GFX12-NEXT:    s_wait_kmcnt 0x02107; GFX12-NEXT:    v_dual_add_f32 v0, v0, v0 :: v_dual_add_f32 v1, v1, v12108; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)2109; GFX12-NEXT:    v_max_num_f32_e32 v0, v0, v12110; GFX12-NEXT:    s_setpc_b64 s[30:31]2111  %a = fadd nnan float %arg0, %arg02112  %b = fadd nnan float %arg1, %arg12113  %cmp = fcmp uge float %a, %b2114  %val = select nsz i1 %cmp, float %a, float %b2115  ret float %val2116}2117