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1; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s2; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI,GFX89 %s3; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx900 -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9,GFX89 %s4 5; Test expansion of scalar selects on vectors.6; Evergreen not enabled since it seems to be having problems with doubles.7 8; GCN-LABEL: {{^}}v_select_v2i8:9; SI: v_cndmask_b3210; SI-NOT: cndmask11 12; GFX9: v_cndmask_b3213; GFX9-NOT: cndmask14 15; This is worse when i16 is legal and packed is not because16; SelectionDAGBuilder for some reason changes the select type.17; VI: s_cselect_b6418; VI: v_cndmask_b3219define amdgpu_kernel void @v_select_v2i8(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(4) %b.ptr, i32 %c) #0 {20 %a = load <2 x i8>, ptr addrspace(1) %a.ptr, align 221 %b = load <2 x i8>, ptr addrspace(4) %b.ptr, align 222 %cmp = icmp eq i32 %c, 023 %select = select i1 %cmp, <2 x i8> %a, <2 x i8> %b24 store <2 x i8> %select, ptr addrspace(1) %out, align 225 ret void26}27 28; GCN-LABEL: {{^}}v_select_v4i8:29; GCN: v_cndmask_b32_e3230; GCN-NOT: cndmask31define amdgpu_kernel void @v_select_v4i8(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(4) %b.ptr, i32 %c) #0 {32 %a = load <4 x i8>, ptr addrspace(1) %a.ptr33 %b = load <4 x i8>, ptr addrspace(4) %b.ptr34 %cmp = icmp eq i32 %c, 035 %select = select i1 %cmp, <4 x i8> %a, <4 x i8> %b36 store <4 x i8> %select, ptr addrspace(1) %out, align 437 ret void38}39 40; GCN-LABEL: {{^}}v_select_v8i8:41; GCN: v_cndmask_b32_e3242; GCN: v_cndmask_b32_e3243; GCN-NOT: cndmask44define amdgpu_kernel void @v_select_v8i8(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(4) %b.ptr, i32 %c) #0 {45 %a = load <8 x i8>, ptr addrspace(1) %a.ptr46 %b = load <8 x i8>, ptr addrspace(4) %b.ptr47 %cmp = icmp eq i32 %c, 048 %select = select i1 %cmp, <8 x i8> %a, <8 x i8> %b49 store <8 x i8> %select, ptr addrspace(1) %out, align 450 ret void51}52 53; GCN-LABEL: {{^}}v_select_v16i8:54; GCN: v_cndmask_b32_e3255; GCN: v_cndmask_b32_e3256; GCN: v_cndmask_b32_e3257; GCN: v_cndmask_b32_e3258; GCN-NOT: cndmask59define amdgpu_kernel void @v_select_v16i8(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(4) %b.ptr, i32 %c) #0 {60 %a = load <16 x i8>, ptr addrspace(1) %a.ptr61 %b = load <16 x i8>, ptr addrspace(4) %b.ptr62 %cmp = icmp eq i32 %c, 063 %select = select i1 %cmp, <16 x i8> %a, <16 x i8> %b64 store <16 x i8> %select, ptr addrspace(1) %out, align 465 ret void66}67 68; GCN-LABEL: {{^}}select_v4i8:69; GFX89: s_cselect_b3270; GFX89-NOT: s_cselect_b3271 72; SI: s_cselect_b3273; SI-NOT: cndmask74define amdgpu_kernel void @select_v4i8(ptr addrspace(1) %out, <4 x i8> %a, <4 x i8> %b, i8 %c) #0 {75 %cmp = icmp eq i8 %c, 076 %select = select i1 %cmp, <4 x i8> %a, <4 x i8> %b77 store <4 x i8> %select, ptr addrspace(1) %out, align 478 ret void79}80 81; GCN-LABEL: {{^}}select_v2i16:82; GFX89: s_load_dwordx483; GFX89: s_cselect_b3284; GFX89-NOT: s_cselect_b3285 86; SI: s_cselect_b3287; SI-NOT: v_cndmask_b32e88define amdgpu_kernel void @select_v2i16(ptr addrspace(1) %out, <2 x i16> %a, <2 x i16> %b, i32 %c) #0 {89 %cmp = icmp eq i32 %c, 090 %select = select i1 %cmp, <2 x i16> %a, <2 x i16> %b91 store <2 x i16> %select, ptr addrspace(1) %out, align 492 ret void93}94 95; GCN-LABEL: {{^}}v_select_v2i16:96; GCN: {{buffer|flat|global}}_load_dword v97; GCN: {{buffer|flat|global}}_load_dword v98; GCN: v_cndmask_b3299; GCN-NOT: cndmask100define amdgpu_kernel void @v_select_v2i16(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(4) %b.ptr, i32 %c) #0 {101 %id = call i32 @llvm.amdgcn.workitem.id.x()102 %gep.a = getelementptr <2 x i16>, ptr addrspace(1) %a.ptr, i32 %id103 %gep.b = getelementptr <2 x i16>, ptr addrspace(4) %b.ptr, i32 %id104 %a = load <2 x i16>, ptr addrspace(1) %gep.a105 %b = load <2 x i16>, ptr addrspace(4) %gep.b106 %cmp = icmp eq i32 %c, 0107 %select = select i1 %cmp, <2 x i16> %a, <2 x i16> %b108 store <2 x i16> %select, ptr addrspace(1) %out, align 4109 ret void110}111 112; GCN-LABEL: {{^}}v_select_v3i16:113; SI: v_cndmask_b32_e32114; SI: cndmask115; SI-NOT: cndmask116 117; VI: s_cselect_b64118; GFX9: cndmask119; GFX9: cndmask120define amdgpu_kernel void @v_select_v3i16(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(4) %b.ptr, i32 %c) #0 {121 %a = load <3 x i16>, ptr addrspace(1) %a.ptr122 %b = load <3 x i16>, ptr addrspace(4) %b.ptr123 %cmp = icmp eq i32 %c, 0124 %select = select i1 %cmp, <3 x i16> %a, <3 x i16> %b125 store <3 x i16> %select, ptr addrspace(1) %out, align 4126 ret void127}128 129; GCN-LABEL: {{^}}v_select_v4i16:130; GCN: v_cndmask_b32_e32131; GCN: v_cndmask_b32_e32132; GCN-NOT: cndmask133define amdgpu_kernel void @v_select_v4i16(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(4) %b.ptr, i32 %c) #0 {134 %a = load <4 x i16>, ptr addrspace(1) %a.ptr135 %b = load <4 x i16>, ptr addrspace(4) %b.ptr136 %cmp = icmp eq i32 %c, 0137 %select = select i1 %cmp, <4 x i16> %a, <4 x i16> %b138 store <4 x i16> %select, ptr addrspace(1) %out, align 4139 ret void140}141 142; GCN-LABEL: {{^}}v_select_v8i16:143; GCN: v_cndmask_b32_e32144; GCN: v_cndmask_b32_e32145; GCN: v_cndmask_b32_e32146; GCN: v_cndmask_b32_e32147; GCN-NOT: cndmask148define amdgpu_kernel void @v_select_v8i16(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(4) %b.ptr, i32 %c) #0 {149 %a = load <8 x i16>, ptr addrspace(1) %a.ptr150 %b = load <8 x i16>, ptr addrspace(4) %b.ptr151 %cmp = icmp eq i32 %c, 0152 %select = select i1 %cmp, <8 x i16> %a, <8 x i16> %b153 store <8 x i16> %select, ptr addrspace(1) %out, align 4154 ret void155}156 157; GCN-LABEL: {{^}}v_select_v16i16:158; GCN: v_cndmask_b32_e32159; GCN: v_cndmask_b32_e32160; GCN: v_cndmask_b32_e32161; GCN: v_cndmask_b32_e32162; GCN: v_cndmask_b32_e32163; GCN: v_cndmask_b32_e32164; GCN: v_cndmask_b32_e32165; GCN: v_cndmask_b32_e32166; GCN-NOT: cndmask167define amdgpu_kernel void @v_select_v16i16(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(4) %b.ptr, i32 %c) #0 {168 %a = load <16 x i16>, ptr addrspace(1) %a.ptr169 %b = load <16 x i16>, ptr addrspace(4) %b.ptr170 %cmp = icmp eq i32 %c, 0171 %select = select i1 %cmp, <16 x i16> %a, <16 x i16> %b172 store <16 x i16> %select, ptr addrspace(1) %out, align 4173 ret void174}175 176; GCN-LABEL: {{^}}v_select_v32i16:177; GCN: v_cndmask_b32_e32178; GCN: v_cndmask_b32_e32179; GCN: v_cndmask_b32_e32180; GCN: v_cndmask_b32_e32181; GCN: v_cndmask_b32_e32182; GCN: v_cndmask_b32_e32183; GCN: v_cndmask_b32_e32184; GCN: v_cndmask_b32_e32185; GCN: v_cndmask_b32_e32186; GCN: v_cndmask_b32_e32187; GCN: v_cndmask_b32_e32188; GCN: v_cndmask_b32_e32189; GCN: v_cndmask_b32_e32190; GCN: v_cndmask_b32_e32191; GCN: v_cndmask_b32_e32192; GCN: v_cndmask_b32_e32193; GCN-NOT: cndmask194define amdgpu_kernel void @v_select_v32i16(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(4) %b.ptr, i32 %c) #0 {195 %a = load <32 x i16>, ptr addrspace(1) %a.ptr196 %b = load <32 x i16>, ptr addrspace(4) %b.ptr197 %cmp = icmp eq i32 %c, 0198 %select = select i1 %cmp, <32 x i16> %a, <32 x i16> %b199 store <32 x i16> %select, ptr addrspace(1) %out, align 4200 ret void201}202 203; FIXME: Expansion with bitwise operations may be better if doing a204; vector select with SGPR inputs.205 206; GCN-LABEL: {{^}}s_select_v2i32:207; GCN: s_cselect_b32208; GCN: s_cselect_b32209; GCN: buffer_store_dwordx2210define amdgpu_kernel void @s_select_v2i32(ptr addrspace(1) %out, <2 x i32> %a, <2 x i32> %b, i32 %c) #0 {211 %cmp = icmp eq i32 %c, 0212 %select = select i1 %cmp, <2 x i32> %a, <2 x i32> %b213 store <2 x i32> %select, ptr addrspace(1) %out, align 8214 ret void215}216 217; GCN-LABEL: {{^}}s_select_v4i32:218; GCN: s_cselect_b32219; GCN: s_cselect_b32220; GCN: s_cselect_b32221; GCN: s_cselect_b32222; GCN: buffer_store_dwordx4223define amdgpu_kernel void @s_select_v4i32(ptr addrspace(1) %out, <4 x i32> %a, <4 x i32> %b, i32 %c) #0 {224 %cmp = icmp eq i32 %c, 0225 %select = select i1 %cmp, <4 x i32> %a, <4 x i32> %b226 store <4 x i32> %select, ptr addrspace(1) %out, align 16227 ret void228}229 230; GCN-LABEL: {{^}}v_select_v4i32:231; GCN: buffer_load_dwordx4232; GCN: s_cmp_lt_u32 s{{[0-9]+}}, 32233; GCN: s_cselect_b64 vcc, -1, 0234; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, 0, v{{[0-9]+}}, vcc235; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, 0, v{{[0-9]+}}, vcc236; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, 0, v{{[0-9]+}}, vcc237; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, 0, v{{[0-9]+}}, vcc238; GCN: buffer_store_dwordx4239define amdgpu_kernel void @v_select_v4i32(ptr addrspace(1) %out, ptr addrspace(1) %in, i32 %cond) #0 {240bb:241 %tmp2 = icmp ult i32 %cond, 32242 %val = load <4 x i32>, ptr addrspace(1) %in243 %tmp3 = select i1 %tmp2, <4 x i32> %val, <4 x i32> zeroinitializer244 store <4 x i32> %tmp3, ptr addrspace(1) %out, align 16245 ret void246}247 248; GCN-LABEL: {{^}}select_v8i32:249; GCN: s_cselect_b32250; GCN: s_cselect_b32251; GCN: s_cselect_b32252; GCN: s_cselect_b32253; GCN: s_cselect_b32254; GCN: s_cselect_b32255; GCN: s_cselect_b32256; GCN: s_cselect_b32257define amdgpu_kernel void @select_v8i32(ptr addrspace(1) %out, <8 x i32> %a, <8 x i32> %b, i32 %c) #0 {258 %cmp = icmp eq i32 %c, 0259 %select = select i1 %cmp, <8 x i32> %a, <8 x i32> %b260 store <8 x i32> %select, ptr addrspace(1) %out, align 16261 ret void262}263 264; GCN-LABEL: {{^}}s_select_v2f32:265; GCN-DAG: s_cmp_eq_u32 s{{[0-9]+}}, 0{{$}}266; GCN-DAG: s_cselect_b32267; GCN-DAG: s_cselect_b32268; GCN: buffer_store_dwordx2269define amdgpu_kernel void @s_select_v2f32(ptr addrspace(1) %out, <2 x float> %a, <2 x float> %b, i32 %c) #0 {270 %cmp = icmp eq i32 %c, 0271 %select = select i1 %cmp, <2 x float> %a, <2 x float> %b272 store <2 x float> %select, ptr addrspace(1) %out, align 16273 ret void274}275 276; GCN-LABEL: {{^}}s_select_v3f32:277; GCN: s_cmp_eq_u32 s{{[0-9]+}}, 0{{$}}278 279; GCN: s_cselect_b32280; GCN: s_cselect_b32281; GCN: s_cselect_b32282 283; GCN: buffer_store_dwordx284define amdgpu_kernel void @s_select_v3f32(ptr addrspace(1) %out, <3 x float> %a, <3 x float> %b, i32 %c) #0 {285 %cmp = icmp eq i32 %c, 0286 %select = select i1 %cmp, <3 x float> %a, <3 x float> %b287 store <3 x float> %select, ptr addrspace(1) %out, align 16288 ret void289}290 291; GCN-LABEL: {{^}}s_select_v4f32:292; GCN: s_load_dwordx8293; GCN: s_cmp_eq_u32 s{{[0-9]+}}, 0{{$}}294 295; GCN: s_cselect_b32296; GCN: s_cselect_b32297; GCN: s_cselect_b32298; GCN: s_cselect_b32299 300; GCN: buffer_store_dwordx4301define amdgpu_kernel void @s_select_v4f32(ptr addrspace(1) %out, <4 x float> %a, <4 x float> %b, i32 %c) #0 {302 %cmp = icmp eq i32 %c, 0303 %select = select i1 %cmp, <4 x float> %a, <4 x float> %b304 store <4 x float> %select, ptr addrspace(1) %out, align 16305 ret void306}307 308; GCN-LABEL: {{^}}v_select_v4f32:309; GCN: buffer_load_dwordx4310; GCN: s_cmp_lt_u32 s{{[0-9]+}}, 32311; GCN: s_cselect_b64 vcc, -1, 0312; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, 0, v{{[0-9]+}}, vcc313; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, 0, v{{[0-9]+}}, vcc314; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, 0, v{{[0-9]+}}, vcc315; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, 0, v{{[0-9]+}}, vcc316; GCN: buffer_store_dwordx4317define amdgpu_kernel void @v_select_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %in, i32 %cond) #0 {318bb:319 %tmp2 = icmp ult i32 %cond, 32320 %val = load <4 x float>, ptr addrspace(1) %in321 %tmp3 = select i1 %tmp2, <4 x float> %val, <4 x float> zeroinitializer322 store <4 x float> %tmp3, ptr addrspace(1) %out, align 16323 ret void324}325 326; GCN-LABEL: {{^}}s_select_v5f32:327; GCN: s_cmp_eq_u32 s{{[0-9]+}}, 0{{$}}328 329; GCN: s_cselect_b32330; GCN: s_cselect_b32331; GCN: s_cselect_b32332; GCN: s_cselect_b32333; GCN: s_cselect_b32334 335; GCN: buffer_store_dwordx336define amdgpu_kernel void @s_select_v5f32(ptr addrspace(1) %out, <5 x float> %a, <5 x float> %b, i32 %c) #0 {337 %cmp = icmp eq i32 %c, 0338 %select = select i1 %cmp, <5 x float> %a, <5 x float> %b339 call void asm "; use $0", "s"(<5 x float> %a)340 store <5 x float> %select, ptr addrspace(1) %out, align 16341 ret void342}343 344; GCN-LABEL: {{^}}select_v8f32:345; GCN: v_cndmask_b32_e32346; GCN: v_cndmask_b32_e32347; GCN: v_cndmask_b32_e32348; GCN: v_cndmask_b32_e32349; GCN: v_cndmask_b32_e32350; GCN: v_cndmask_b32_e32351; GCN: v_cndmask_b32_e32352; GCN: v_cndmask_b32_e32353define amdgpu_kernel void @select_v8f32(ptr addrspace(1) %out, <8 x float> %a, <8 x float> %b, i32 %c) #0 {354 %cmp = icmp eq i32 %c, 0355 %select = select i1 %cmp, <8 x float> %a, <8 x float> %b356 store <8 x float> %select, ptr addrspace(1) %out, align 16357 ret void358}359 360; GCN-LABEL: {{^}}select_v2f64:361; GCN: s_cselect_b32362; GCN: s_cselect_b32363; GCN: s_cselect_b32364; GCN: s_cselect_b32365define amdgpu_kernel void @select_v2f64(ptr addrspace(1) %out, <2 x double> %a, <2 x double> %b, i32 %c) #0 {366 %cmp = icmp eq i32 %c, 0367 %select = select i1 %cmp, <2 x double> %a, <2 x double> %b368 store <2 x double> %select, ptr addrspace(1) %out, align 16369 ret void370}371 372; GCN-LABEL: {{^}}select_v4f64:373; GCN: s_cselect_b32374; GCN: s_cselect_b32375; GCN: s_cselect_b32376; GCN: s_cselect_b32377; GCN: s_cselect_b32378; GCN: s_cselect_b32379; GCN: s_cselect_b32380; GCN: s_cselect_b32381define amdgpu_kernel void @select_v4f64(ptr addrspace(1) %out, <4 x double> %a, <4 x double> %b, i32 %c) #0 {382 %cmp = icmp eq i32 %c, 0383 %select = select i1 %cmp, <4 x double> %a, <4 x double> %b384 store <4 x double> %select, ptr addrspace(1) %out, align 16385 ret void386}387 388; GCN-LABEL: {{^}}select_v8f64:389; GCN: s_cselect_b32390; GCN: s_cselect_b32391; GCN: s_cselect_b32392; GCN: s_cselect_b32393; GCN: s_cselect_b32394; GCN: s_cselect_b32395; GCN: s_cselect_b32396; GCN: s_cselect_b32397; GCN: s_cselect_b32398; GCN: s_cselect_b32399; GCN: s_cselect_b32400; GCN: s_cselect_b32401; GCN: s_cselect_b32402; GCN: s_cselect_b32403; GCN: s_cselect_b32404; GCN: s_cselect_b32405define amdgpu_kernel void @select_v8f64(ptr addrspace(1) %out, <8 x double> %a, <8 x double> %b, i32 %c) #0 {406 %cmp = icmp eq i32 %c, 0407 call void asm "; use $0", "s"(<8 x double> %a)408 %select = select i1 %cmp, <8 x double> %a, <8 x double> %b409 store <8 x double> %select, ptr addrspace(1) %out, align 16410 ret void411}412 413; GCN-LABEL: {{^}}v_select_v2f16:414; GCN: v_cndmask_b32415; GCN-NOT: cndmask416define amdgpu_kernel void @v_select_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(4) %b.ptr, i32 %c) #0 {417 %a = load <2 x half>, ptr addrspace(1) %a.ptr418 %b = load <2 x half>, ptr addrspace(4) %b.ptr419 %cmp = icmp eq i32 %c, 0420 %select = select i1 %cmp, <2 x half> %a, <2 x half> %b421 store <2 x half> %select, ptr addrspace(1) %out, align 4422 ret void423}424 425; GCN-LABEL: {{^}}v_select_v3f16:426; GCN: v_cndmask_b32_e32427; GCN: v_cndmask_b32_e32428; GCN-NOT: cndmask429define amdgpu_kernel void @v_select_v3f16(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(4) %b.ptr, i32 %c) #0 {430 %a = load <3 x half>, ptr addrspace(1) %a.ptr431 %b = load <3 x half>, ptr addrspace(4) %b.ptr432 %cmp = icmp eq i32 %c, 0433 %select = select i1 %cmp, <3 x half> %a, <3 x half> %b434 store <3 x half> %select, ptr addrspace(1) %out, align 4435 ret void436}437 438; GCN-LABEL: {{^}}v_select_v4f16:439; GCN: v_cndmask_b32_e32440; GCN: v_cndmask_b32_e32441; GCN-NOT: cndmask442define amdgpu_kernel void @v_select_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(4) %b.ptr, i32 %c) #0 {443 %a = load <4 x half>, ptr addrspace(1) %a.ptr444 %b = load <4 x half>, ptr addrspace(4) %b.ptr445 %cmp = icmp eq i32 %c, 0446 %select = select i1 %cmp, <4 x half> %a, <4 x half> %b447 store <4 x half> %select, ptr addrspace(1) %out, align 4448 ret void449}450 451; Function Attrs: nounwind readnone452declare i32 @llvm.amdgcn.workitem.id.x() #1453 454attributes #0 = { nounwind }455attributes #1 = { nounwind readnone }456