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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=r600 -mcpu=redwood | FileCheck %s3 4; Test a selectcc with i32 LHS/RHS and float True/False5 6define amdgpu_kernel void @test(ptr addrspace(1) %out, ptr addrspace(1) %in) {7; CHECK-LABEL: test:8; CHECK: ; %bb.0: ; %entry9; CHECK-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]10; CHECK-NEXT: TEX 0 @611; CHECK-NEXT: ALU 3, @9, KC0[CB0:0-32], KC1[]12; CHECK-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 113; CHECK-NEXT: CF_END14; CHECK-NEXT: PAD15; CHECK-NEXT: Fetch clause starting at 6:16; CHECK-NEXT: VTX_READ_32 T0.X, T0.X, 0, #117; CHECK-NEXT: ALU clause starting at 8:18; CHECK-NEXT: MOV * T0.X, KC0[2].Z,19; CHECK-NEXT: ALU clause starting at 9:20; CHECK-NEXT: SETGT_INT * T0.W, 0.0, T0.X,21; CHECK-NEXT: CNDE_INT T0.X, PV.W, literal.x, 0.0,22; CHECK-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,23; CHECK-NEXT: 1065353216(1.000000e+00), 2(2.802597e-45)24entry:25 %0 = load i32, ptr addrspace(1) %in26 %1 = icmp sge i32 %0, 027 %2 = select i1 %1, float 1.0, float 0.028 store float %2, ptr addrspace(1) %out29 ret void30}31