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1; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s2; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s3; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s4 5 6; FUNC-LABEL: {{^}}test_a:7; EG-NOT: CND8; EG: SET{{[NEQGTL]+}}_DX109 10define amdgpu_kernel void @test_a(ptr addrspace(1) %out, float %in) {11entry:12 %0 = fcmp olt float %in, 0.000000e+0013 %1 = select i1 %0, float 1.000000e+00, float 0.000000e+0014 %2 = fneg float %115 %3 = fptosi float %2 to i3216 %4 = bitcast i32 %3 to float17 %5 = bitcast float %4 to i3218 %6 = icmp ne i32 %5, 019 br i1 %6, label %IF, label %ENDIF20 21IF:22 %7 = getelementptr i32, ptr addrspace(1) %out, i32 123 store i32 0, ptr addrspace(1) %724 br label %ENDIF25 26ENDIF:27 store i32 0, ptr addrspace(1) %out28 ret void29}30 31; Same as test_a, but the branch labels are swapped to produce the inverse cc32; for the icmp instruction33 34; EG-LABEL: {{^}}test_b:35; EG: SET{{[GTEQN]+}}_DX1036; EG-NEXT: 0(0.000000e+00), 0(0.000000e+00)37; EG-NEXT: PRED_38; EG-NEXT: ALU clause starting39define amdgpu_kernel void @test_b(ptr addrspace(1) %out, float %in) {40entry:41 %0 = fcmp olt float %in, 0.042 %1 = select i1 %0, float 1.000000e+00, float 0.000000e+0043 %2 = fneg float %144 %3 = fptosi float %2 to i3245 %4 = bitcast i32 %3 to float46 %5 = bitcast float %4 to i3247 %6 = icmp ne i32 %5, 048 br i1 %6, label %ENDIF, label %IF49 50IF:51 %7 = getelementptr i32, ptr addrspace(1) %out, i32 152 store i32 0, ptr addrspace(1) %753 br label %ENDIF54 55ENDIF:56 store i32 0, ptr addrspace(1) %out57 ret void58}59 60; Test a CND*_INT instruction with float true/false values61; EG-LABEL: {{^}}test_c:62; EG: CND{{[GTE]+}}_INT63define amdgpu_kernel void @test_c(ptr addrspace(1) %out, i32 %in) {64entry:65 %0 = icmp sgt i32 %in, 066 %1 = select i1 %0, float 2.0, float 3.067 store float %1, ptr addrspace(1) %out68 ret void69}70 71; FUNC-LABEL: {{^}}selectcc_bool:72; SI: s_cmp_lg_u3273; SI: v_cndmask_b32_e6474; SI-NOT: cmp75; SI-NOT: cndmask76define amdgpu_kernel void @selectcc_bool(ptr addrspace(1) %out, i32 %a, i32 %b) nounwind {77 %icmp0 = icmp ne i32 %a, %b78 %ext = select i1 %icmp0, i32 -1, i32 079 store i32 %ext, ptr addrspace(1) %out80 ret void81}82