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1; RUN: llc < %s -mtriple=r600 -mcpu=redwood | FileCheck %s2 3; These tests check that floating point comparisons which are used by select4; to store integer true (-1) and false (0) values are lowered to one of the5; SET*DX10 instructions.6 7; CHECK: {{^}}fcmp_une_select_fptosi:8; CHECK: LSHR9; CHECK-NEXT: SETNE_DX10 * {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.y,10; CHECK-NEXT: 1084227584(5.000000e+00)11define amdgpu_kernel void @fcmp_une_select_fptosi(ptr addrspace(1) %out, float %in) {12entry:13 %0 = fcmp une float %in, 5.014 %1 = select i1 %0, float 1.000000e+00, float 0.000000e+0015 %2 = fneg float %116 %3 = fptosi float %2 to i3217 store i32 %3, ptr addrspace(1) %out18 ret void19}20 21; CHECK: {{^}}fcmp_une_select_i32:22; CHECK: LSHR23; CHECK-NEXT: SETNE_DX10 * {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.y,24; CHECK-NEXT: 1084227584(5.000000e+00)25define amdgpu_kernel void @fcmp_une_select_i32(ptr addrspace(1) %out, float %in) {26entry:27 %0 = fcmp une float %in, 5.028 %1 = select i1 %0, i32 -1, i32 029 store i32 %1, ptr addrspace(1) %out30 ret void31}32 33; CHECK: {{^}}fcmp_oeq_select_fptosi:34; CHECK: LSHR35; CHECK-NEXT: SETE_DX10 * {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.y,36; CHECK-NEXT: 1084227584(5.000000e+00)37define amdgpu_kernel void @fcmp_oeq_select_fptosi(ptr addrspace(1) %out, float %in) {38entry:39 %0 = fcmp oeq float %in, 5.040 %1 = select i1 %0, float 1.000000e+00, float 0.000000e+0041 %2 = fneg float %142 %3 = fptosi float %2 to i3243 store i32 %3, ptr addrspace(1) %out44 ret void45}46 47; CHECK: {{^}}fcmp_oeq_select_i32:48; CHECK: LSHR49; CHECK-NEXT: SETE_DX10 * {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.y,50; CHECK-NEXT: 1084227584(5.000000e+00)51define amdgpu_kernel void @fcmp_oeq_select_i32(ptr addrspace(1) %out, float %in) {52entry:53 %0 = fcmp oeq float %in, 5.054 %1 = select i1 %0, i32 -1, i32 055 store i32 %1, ptr addrspace(1) %out56 ret void57}58 59; CHECK: {{^}}fcmp_ogt_select_fptosi:60; CHECK: LSHR61; CHECK-NEXT: SETGT_DX10 * {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.y,62; CHECK-NEXT: 1084227584(5.000000e+00)63define amdgpu_kernel void @fcmp_ogt_select_fptosi(ptr addrspace(1) %out, float %in) {64entry:65 %0 = fcmp ogt float %in, 5.066 %1 = select i1 %0, float 1.000000e+00, float 0.000000e+0067 %2 = fneg float %168 %3 = fptosi float %2 to i3269 store i32 %3, ptr addrspace(1) %out70 ret void71}72 73; CHECK: {{^}}fcmp_ogt_select_i32:74; CHECK: LSHR75; CHECK-NEXT: SETGT_DX10 * {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.y,76; CHECK-NEXT: 1084227584(5.000000e+00)77define amdgpu_kernel void @fcmp_ogt_select_i32(ptr addrspace(1) %out, float %in) {78entry:79 %0 = fcmp ogt float %in, 5.080 %1 = select i1 %0, i32 -1, i32 081 store i32 %1, ptr addrspace(1) %out82 ret void83}84 85; CHECK: {{^}}fcmp_oge_select_fptosi:86; CHECK: LSHR87; CHECK-NEXT: SETGE_DX10 * {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.y,88; CHECK-NEXT: 1084227584(5.000000e+00)89define amdgpu_kernel void @fcmp_oge_select_fptosi(ptr addrspace(1) %out, float %in) {90entry:91 %0 = fcmp oge float %in, 5.092 %1 = select i1 %0, float 1.000000e+00, float 0.000000e+0093 %2 = fneg float %194 %3 = fptosi float %2 to i3295 store i32 %3, ptr addrspace(1) %out96 ret void97}98 99; CHECK: {{^}}fcmp_oge_select_i32:100; CHECK: LSHR101; CHECK-NEXT: SETGE_DX10 * {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.y,102; CHECK-NEXT: 1084227584(5.000000e+00)103define amdgpu_kernel void @fcmp_oge_select_i32(ptr addrspace(1) %out, float %in) {104entry:105 %0 = fcmp oge float %in, 5.0106 %1 = select i1 %0, i32 -1, i32 0107 store i32 %1, ptr addrspace(1) %out108 ret void109}110 111; CHECK: {{^}}fcmp_ole_select_fptosi:112; CHECK: LSHR113; CHECK-NEXT: SETGE_DX10 * {{\** *}}T{{[0-9]+\.[XYZW]}}, literal.y, KC0[2].Z,114; CHECK-NEXT: 1084227584(5.000000e+00)115define amdgpu_kernel void @fcmp_ole_select_fptosi(ptr addrspace(1) %out, float %in) {116entry:117 %0 = fcmp ole float %in, 5.0118 %1 = select i1 %0, float 1.000000e+00, float 0.000000e+00119 %2 = fneg float %1120 %3 = fptosi float %2 to i32121 store i32 %3, ptr addrspace(1) %out122 ret void123}124 125; CHECK: {{^}}fcmp_ole_select_i32:126; CHECK: LSHR127; CHECK-NEXT: SETGE_DX10 * {{\** *}}T{{[0-9]+\.[XYZW]}}, literal.y, KC0[2].Z,128; CHECK-NEXT: 1084227584(5.000000e+00)129define amdgpu_kernel void @fcmp_ole_select_i32(ptr addrspace(1) %out, float %in) {130entry:131 %0 = fcmp ole float %in, 5.0132 %1 = select i1 %0, i32 -1, i32 0133 store i32 %1, ptr addrspace(1) %out134 ret void135}136 137; CHECK: {{^}}fcmp_olt_select_fptosi:138; CHECK: LSHR139; CHECK-NEXT: SETGT_DX10 * {{\** *}}T{{[0-9]+\.[XYZW]}}, literal.y, KC0[2].Z,140; CHECK-NEXT: 1084227584(5.000000e+00)141define amdgpu_kernel void @fcmp_olt_select_fptosi(ptr addrspace(1) %out, float %in) {142entry:143 %0 = fcmp olt float %in, 5.0144 %1 = select i1 %0, float 1.000000e+00, float 0.000000e+00145 %2 = fneg float %1146 %3 = fptosi float %2 to i32147 store i32 %3, ptr addrspace(1) %out148 ret void149}150 151; CHECK: {{^}}fcmp_olt_select_i32:152; CHECK: LSHR153; CHECK-NEXT: SETGT_DX10 * {{\** *}}T{{[0-9]+\.[XYZW]}}, literal.y, KC0[2].Z,154; CHECK-NEXT: 1084227584(5.000000e+00)155define amdgpu_kernel void @fcmp_olt_select_i32(ptr addrspace(1) %out, float %in) {156entry:157 %0 = fcmp olt float %in, 5.0158 %1 = select i1 %0, i32 -1, i32 0159 store i32 %1, ptr addrspace(1) %out160 ret void161}162