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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck %s -check-prefix=GCN3 4define amdgpu_cs void @if_then(ptr addrspace(8) inreg %input, ptr addrspace(8) inreg %output, <3 x i32> %LocalInvocationId) {5; GCN-LABEL: if_then:6; GCN: ; %bb.0: ; %.entry7; GCN-NEXT: v_mov_b32_e32 v3, 08; GCN-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v09; GCN-NEXT: s_and_saveexec_b32 s0, vcc_lo10; GCN-NEXT: ; %bb.1: ; %.bb011; GCN-NEXT: v_mov_b32_e32 v3, 112; GCN-NEXT: ; %bb.2: ; %.merge13; GCN-NEXT: s_or_b32 exec_lo, exec_lo, s014; GCN-NEXT: v_cmp_lt_u32_e32 vcc_lo, 3, v015; GCN-NEXT: s_and_saveexec_b32 s0, vcc_lo16; GCN-NEXT: s_cbranch_execz .LBB0_417; GCN-NEXT: ; %bb.3: ; %.then18; GCN-NEXT: s_or_saveexec_b32 s1, -119; GCN-NEXT: v_cndmask_b32_e64 v1, 0, v3, s120; GCN-NEXT: v_mov_b32_e32 v2, 021; GCN-NEXT: v_mov_b32_dpp v2, v1 row_shr:1 row_mask:0xf bank_mask:0xf22; GCN-NEXT: s_mov_b32 exec_lo, s123; GCN-NEXT: v_mov_b32_e32 v0, v224; GCN-NEXT: v_mov_b32_e32 v4, -125; GCN-NEXT: v_mov_b32_e32 v3, 026; GCN-NEXT: buffer_store_dword v4, v0, s[4:7], 0 offen27; GCN-NEXT: .LBB0_4: ; %.end28; GCN-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)29; GCN-NEXT: s_or_b32 exec_lo, exec_lo, s030; GCN-NEXT: v_mov_b32_e32 v0, -131; GCN-NEXT: buffer_store_dword v0, v3, s[4:7], 0 offen32; GCN-NEXT: s_endpgm33.entry:34 %LocalInvocationId.i0 = extractelement <3 x i32> %LocalInvocationId, i32 035 %.not10002 = icmp eq i32 %LocalInvocationId.i0, 036 br i1 %.not10002, label %.merge, label %.bb037 38.bb0:39 br label %.merge40 41.merge:42 %src = phi i32 [ 0, %.entry ], [ 1, %.bb0 ]43 %i530 = icmp ult i32 %LocalInvocationId.i0, 444 br i1 %i530, label %.end, label %.then45 46.then:47 %i562 = call i32 @llvm.amdgcn.set.inactive.i32(i32 %src, i32 0)48 %i563 = call i32 @llvm.amdgcn.update.dpp.i32(i32 0, i32 %i562, i32 273, i32 15, i32 15, i1 false)49 %i564 = call i32 @llvm.amdgcn.strict.wwm.i32(i32 %i563)50 call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 -1, ptr addrspace(8) %output, i32 %i564, i32 0, i32 0)51 br label %.end52 53.end:54 %idx = phi i32 [ 0, %.then ], [ %src, %.merge ]55 call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 -1, ptr addrspace(8) %output, i32 %idx, i32 0, i32 0)56 ret void57}58 59 60define amdgpu_cs void @if_else_vgpr_opt(ptr addrspace(8) inreg %input, ptr addrspace(8) inreg %output, <3 x i32> %LocalInvocationId) {61; GCN-LABEL: if_else_vgpr_opt:62; GCN: ; %bb.0: ; %.entry63; GCN-NEXT: v_mov_b32_e32 v3, 064; GCN-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v065; GCN-NEXT: s_and_saveexec_b32 s0, vcc_lo66; GCN-NEXT: ; %bb.1: ; %.bb067; GCN-NEXT: v_mov_b32_e32 v3, 168; GCN-NEXT: ; %bb.2: ; %.merge69; GCN-NEXT: s_or_b32 exec_lo, exec_lo, s070; GCN-NEXT: v_cmp_lt_u32_e32 vcc_lo, 3, v071; GCN-NEXT: s_and_saveexec_b32 s0, vcc_lo72; GCN-NEXT: s_xor_b32 s0, exec_lo, s073; GCN-NEXT: s_cbranch_execnz .LBB1_574; GCN-NEXT: ; %bb.3: ; %Flow75; GCN-NEXT: s_andn2_saveexec_b32 s0, s076; GCN-NEXT: s_cbranch_execnz .LBB1_677; GCN-NEXT: .LBB1_4: ; %.end78; GCN-NEXT: s_endpgm79; GCN-NEXT: .LBB1_5: ; %.else80; GCN-NEXT: s_or_saveexec_b32 s1, -181; GCN-NEXT: v_mov_b32_e32 v1, 082; GCN-NEXT: v_cndmask_b32_e64 v2, 0, v3, s183; GCN-NEXT: v_mov_b32_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf84; GCN-NEXT: s_mov_b32 exec_lo, s185; GCN-NEXT: v_mov_b32_e32 v0, v186; GCN-NEXT: v_mov_b32_e32 v3, -187; GCN-NEXT: buffer_store_dword v3, v0, s[4:7], 0 offen88; GCN-NEXT: ; implicit-def: $vgpr389; GCN-NEXT: s_andn2_saveexec_b32 s0, s090; GCN-NEXT: s_cbranch_execz .LBB1_491; GCN-NEXT: .LBB1_6: ; %.then92; GCN-NEXT: v_mov_b32_e32 v0, -193; GCN-NEXT: buffer_store_dword v0, v3, s[4:7], 0 offen94; GCN-NEXT: s_endpgm95.entry:96 %LocalInvocationId.i0 = extractelement <3 x i32> %LocalInvocationId, i32 097 %.not10002 = icmp eq i32 %LocalInvocationId.i0, 098 br i1 %.not10002, label %.merge, label %.bb099 100.bb0:101 br label %.merge102 103.merge:104 %src = phi i32 [ 0, %.entry ], [ 1, %.bb0 ]105 %i530 = icmp ult i32 %LocalInvocationId.i0, 4106 br i1 %i530, label %.then, label %.else107 108.then:109 call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 -1, ptr addrspace(8) %output, i32 %src, i32 0, i32 0)110 br label %.end111 112.else:113 %i562 = call i32 @llvm.amdgcn.set.inactive.i32(i32 %src, i32 0)114 %i563 = call i32 @llvm.amdgcn.update.dpp.i32(i32 0, i32 %i562, i32 273, i32 15, i32 15, i1 false)115 %i564 = call i32 @llvm.amdgcn.strict.wwm.i32(i32 %i563)116 call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 -1, ptr addrspace(8) %output, i32 %i564, i32 0, i32 0)117 br label %.end118 119.end:120 ret void121}122 123declare i32 @llvm.amdgcn.set.inactive.i32(i32, i32) #0124declare i32 @llvm.amdgcn.update.dpp.i32(i32, i32, i32, i32, i32, i1) #0125declare i32 @llvm.amdgcn.strict.wwm.i32(i32) #1126declare void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32, ptr addrspace(8), i32, i32 immarg, i32 immarg) #2127 128attributes #0 = { convergent nounwind readnone willreturn }129attributes #1 = { convergent nounwind readnone speculatable willreturn }130attributes #2 = { nounwind willreturn writeonly }131 132