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1; RUN: llc -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=GCN %s2 3; Test fcmp pred (fneg x), c -> fcmp (swapped pred) x, -c combine.4 5; GCN-LABEL: {{^}}multi_use_fneg_src:6; GCN: buffer_load_dword [[A:v[0-9]+]]7; GCN: buffer_load_dword [[B:v[0-9]+]]8; GCN: buffer_load_dword [[C:v[0-9]+]]9 10; GCN: v_mul_f32_e32 [[MUL:v[0-9]+]], [[A]], [[B]]11; GCN: v_cmp_eq_f32_e32 vcc, -4.0, [[MUL]]12; GCN: buffer_store_dword [[MUL]]13define amdgpu_kernel void @multi_use_fneg_src() #0 {14 %a = load volatile float, ptr addrspace(1) poison15 %b = load volatile float, ptr addrspace(1) poison16 %x = load volatile i32, ptr addrspace(1) poison17 %y = load volatile i32, ptr addrspace(1) poison18 19 %mul = fmul float %a, %b20 %neg.mul = fsub float -0.0, %mul21 %cmp = fcmp oeq float %neg.mul, 4.022 %select = select i1 %cmp, i32 %x, i32 %y23 store volatile i32 %select, ptr addrspace(1) poison24 store volatile float %mul, ptr addrspace(1) poison25 ret void26}27 28; GCN-LABEL: {{^}}multi_foldable_use_fneg_src:29; GCN: buffer_load_dword [[A:v[0-9]+]]30; GCN: buffer_load_dword [[B:v[0-9]+]]31; GCN: buffer_load_dword [[C:v[0-9]+]]32 33; GCN: v_mul_f32_e32 [[MUL:v[0-9]+]], [[A]], [[B]]34; GCN: v_cmp_eq_f32_e32 vcc, -4.0, [[A]]35; GCN: v_mul_f32_e64 [[USE1:v[0-9]+]], [[MUL]], -[[MUL]]36define amdgpu_kernel void @multi_foldable_use_fneg_src() #0 {37 %a = load volatile float, ptr addrspace(1) poison38 %b = load volatile float, ptr addrspace(1) poison39 %x = load volatile i32, ptr addrspace(1) poison40 %y = load volatile i32, ptr addrspace(1) poison41 42 %mul = fmul float %a, %b43 %neg.mul = fsub float -0.0, %mul44 %use1 = fmul float %mul, %neg.mul45 %cmp = fcmp oeq float %neg.mul, 4.046 %select = select i1 %cmp, i32 %x, i32 %y47 48 store volatile i32 %select, ptr addrspace(1) poison49 store volatile float %use1, ptr addrspace(1) poison50 ret void51}52 53; GCN-LABEL: {{^}}multi_use_fneg:54; GCN: buffer_load_dword [[A:v[0-9]+]]55; GCN: buffer_load_dword [[B:v[0-9]+]]56; GCN: buffer_load_dword [[C:v[0-9]+]]57 58; GCN: v_mul_f32_e64 [[MUL:v[0-9]+]], [[A]], -[[B]]59; GCN-NEXT: v_cmp_eq_f32_e32 vcc, 4.0, [[MUL]]60; GCN-NOT: xor61; GCN: buffer_store_dword [[MUL]]62define amdgpu_kernel void @multi_use_fneg() #0 {63 %a = load volatile float, ptr addrspace(1) poison64 %b = load volatile float, ptr addrspace(1) poison65 %x = load volatile i32, ptr addrspace(1) poison66 %y = load volatile i32, ptr addrspace(1) poison67 68 %mul = fmul float %a, %b69 %neg.mul = fsub float -0.0, %mul70 %cmp = fcmp oeq float %neg.mul, 4.071 %select = select i1 %cmp, i32 %x, i32 %y72 store volatile i32 %select, ptr addrspace(1) poison73 store volatile float %neg.mul, ptr addrspace(1) poison74 ret void75}76 77; GCN-LABEL: {{^}}multi_foldable_use_fneg:78; GCN: buffer_load_dword [[A:v[0-9]+]]79; GCN: buffer_load_dword [[B:v[0-9]+]]80 81; GCN: v_mul_f32_e32 [[MUL0:v[0-9]+]], [[A]], [[B]]82; GCN: v_cmp_eq_f32_e32 vcc, -4.0, [[MUL0]]83; GCN: v_mul_f32_e64 [[MUL1:v[0-9]+]], -[[MUL0]], [[MUL0]]84; GCN: buffer_store_dword [[MUL1]]85define amdgpu_kernel void @multi_foldable_use_fneg() #0 {86 %a = load volatile float, ptr addrspace(1) poison87 %b = load volatile float, ptr addrspace(1) poison88 %x = load volatile i32, ptr addrspace(1) poison89 %y = load volatile i32, ptr addrspace(1) poison90 %z = load volatile i32, ptr addrspace(1) poison91 92 %mul = fmul float %a, %b93 %neg.mul = fsub float -0.0, %mul94 %cmp = fcmp oeq float %neg.mul, 4.095 %select = select i1 %cmp, i32 %x, i32 %y96 %use1 = fmul float %neg.mul, %mul97 store volatile i32 %select, ptr addrspace(1) poison98 store volatile float %use1, ptr addrspace(1) poison99 ret void100}101 102; GCN-LABEL: {{^}}test_setcc_fneg_oeq_posk_f32:103; GCN: v_cmp_eq_f32_e32 vcc, -4.0, v{{[0-9]+}}104define amdgpu_kernel void @test_setcc_fneg_oeq_posk_f32() #0 {105 %a = load volatile float, ptr addrspace(1) poison106 %x = load volatile i32, ptr addrspace(1) poison107 %y = load volatile i32, ptr addrspace(1) poison108 %neg.a = fsub float -0.0, %a109 %cmp = fcmp oeq float %neg.a, 4.0110 %select = select i1 %cmp, i32 %x, i32 %y111 store volatile i32 %select, ptr addrspace(1) poison112 ret void113}114 115; GCN-LABEL: {{^}}test_setcc_fneg_ogt_posk_f32:116; GCN: v_cmp_gt_f32_e32 vcc, -4.0, v{{[0-9]+}}117define amdgpu_kernel void @test_setcc_fneg_ogt_posk_f32() #0 {118 %a = load volatile float, ptr addrspace(1) poison119 %x = load volatile i32, ptr addrspace(1) poison120 %y = load volatile i32, ptr addrspace(1) poison121 %neg.a = fsub float -0.0, %a122 %cmp = fcmp ogt float %neg.a, 4.0123 %select = select i1 %cmp, i32 %x, i32 %y124 store volatile i32 %select, ptr addrspace(1) poison125 ret void126}127 128; GCN-LABEL: {{^}}test_setcc_fneg_oge_posk_f32:129; GCN: v_cmp_ge_f32_e32 vcc, -4.0, v{{[0-9]+}}130define amdgpu_kernel void @test_setcc_fneg_oge_posk_f32() #0 {131 %a = load volatile float, ptr addrspace(1) poison132 %x = load volatile i32, ptr addrspace(1) poison133 %y = load volatile i32, ptr addrspace(1) poison134 %neg.a = fsub float -0.0, %a135 %cmp = fcmp oge float %neg.a, 4.0136 %select = select i1 %cmp, i32 %x, i32 %y137 store volatile i32 %select, ptr addrspace(1) poison138 ret void139}140 141; GCN-LABEL: {{^}}test_setcc_fneg_olt_posk_f32:142; GCN: v_cmp_lt_f32_e32 vcc, -4.0, v{{[0-9]+}}143define amdgpu_kernel void @test_setcc_fneg_olt_posk_f32() #0 {144 %a = load volatile float, ptr addrspace(1) poison145 %x = load volatile i32, ptr addrspace(1) poison146 %y = load volatile i32, ptr addrspace(1) poison147 %neg.a = fsub float -0.0, %a148 %cmp = fcmp olt float %neg.a, 4.0149 %select = select i1 %cmp, i32 %x, i32 %y150 store volatile i32 %select, ptr addrspace(1) poison151 ret void152}153 154; GCN-LABEL: {{^}}test_setcc_fneg_ole_posk_f32:155; GCN: v_cmp_le_f32_e32 vcc, -4.0, v{{[0-9]+}}156define amdgpu_kernel void @test_setcc_fneg_ole_posk_f32() #0 {157 %a = load volatile float, ptr addrspace(1) poison158 %x = load volatile i32, ptr addrspace(1) poison159 %y = load volatile i32, ptr addrspace(1) poison160 %neg.a = fsub float -0.0, %a161 %cmp = fcmp ole float %neg.a, 4.0162 %select = select i1 %cmp, i32 %x, i32 %y163 store volatile i32 %select, ptr addrspace(1) poison164 ret void165}166 167; GCN-LABEL: {{^}}test_setcc_fneg_one_posk_f32:168; GCN: v_cmp_lg_f32_e32 vcc, -4.0, v{{[0-9]+}}169define amdgpu_kernel void @test_setcc_fneg_one_posk_f32() #0 {170 %a = load volatile float, ptr addrspace(1) poison171 %x = load volatile i32, ptr addrspace(1) poison172 %y = load volatile i32, ptr addrspace(1) poison173 %neg.a = fsub float -0.0, %a174 %cmp = fcmp one float %neg.a, 4.0175 %select = select i1 %cmp, i32 %x, i32 %y176 store volatile i32 %select, ptr addrspace(1) poison177 ret void178}179 180; GCN-LABEL: {{^}}test_setcc_fneg_ueq_posk_f32:181; GCN: v_cmp_nlg_f32_e32 vcc, -4.0, v{{[0-9]+}}182define amdgpu_kernel void @test_setcc_fneg_ueq_posk_f32() #0 {183 %a = load volatile float, ptr addrspace(1) poison184 %x = load volatile i32, ptr addrspace(1) poison185 %y = load volatile i32, ptr addrspace(1) poison186 %neg.a = fsub float -0.0, %a187 %cmp = fcmp ueq float %neg.a, 4.0188 %select = select i1 %cmp, i32 %x, i32 %y189 store volatile i32 %select, ptr addrspace(1) poison190 ret void191}192 193; GCN-LABEL: {{^}}test_setcc_fneg_ugt_posk_f32:194; GCN: v_cmp_nle_f32_e32 vcc, -4.0, v{{[0-9]+}}195define amdgpu_kernel void @test_setcc_fneg_ugt_posk_f32() #0 {196 %a = load volatile float, ptr addrspace(1) poison197 %x = load volatile i32, ptr addrspace(1) poison198 %y = load volatile i32, ptr addrspace(1) poison199 %neg.a = fsub float -0.0, %a200 %cmp = fcmp ugt float %neg.a, 4.0201 %select = select i1 %cmp, i32 %x, i32 %y202 store volatile i32 %select, ptr addrspace(1) poison203 ret void204}205 206; GCN-LABEL: {{^}}test_setcc_fneg_uge_posk_f32:207; GCN: v_cmp_nlt_f32_e32 vcc, -4.0, v{{[0-9]+}}208define amdgpu_kernel void @test_setcc_fneg_uge_posk_f32() #0 {209 %a = load volatile float, ptr addrspace(1) poison210 %x = load volatile i32, ptr addrspace(1) poison211 %y = load volatile i32, ptr addrspace(1) poison212 %neg.a = fsub float -0.0, %a213 %cmp = fcmp uge float %neg.a, 4.0214 %select = select i1 %cmp, i32 %x, i32 %y215 store volatile i32 %select, ptr addrspace(1) poison216 ret void217}218 219; GCN-LABEL: {{^}}test_setcc_fneg_ult_posk_f32:220; GCN: v_cmp_nge_f32_e32 vcc, -4.0, v{{[0-9]+}}221define amdgpu_kernel void @test_setcc_fneg_ult_posk_f32() #0 {222 %a = load volatile float, ptr addrspace(1) poison223 %x = load volatile i32, ptr addrspace(1) poison224 %y = load volatile i32, ptr addrspace(1) poison225 %neg.a = fsub float -0.0, %a226 %cmp = fcmp ult float %neg.a, 4.0227 %select = select i1 %cmp, i32 %x, i32 %y228 store volatile i32 %select, ptr addrspace(1) poison229 ret void230}231 232; GCN-LABEL: {{^}}test_setcc_fneg_ule_posk_f32:233; GCN: v_cmp_ngt_f32_e32 vcc, -4.0, v{{[0-9]+}}234define amdgpu_kernel void @test_setcc_fneg_ule_posk_f32() #0 {235 %a = load volatile float, ptr addrspace(1) poison236 %x = load volatile i32, ptr addrspace(1) poison237 %y = load volatile i32, ptr addrspace(1) poison238 %neg.a = fsub float -0.0, %a239 %cmp = fcmp ule float %neg.a, 4.0240 %select = select i1 %cmp, i32 %x, i32 %y241 store volatile i32 %select, ptr addrspace(1) poison242 ret void243}244 245; GCN-LABEL: {{^}}test_setcc_fneg_une_posk_f32:246; GCN: v_cmp_neq_f32_e32 vcc, -4.0, v{{[0-9]+}}247define amdgpu_kernel void @test_setcc_fneg_une_posk_f32() #0 {248 %a = load volatile float, ptr addrspace(1) poison249 %x = load volatile i32, ptr addrspace(1) poison250 %y = load volatile i32, ptr addrspace(1) poison251 %neg.a = fsub float -0.0, %a252 %cmp = fcmp une float %neg.a, 4.0253 %select = select i1 %cmp, i32 %x, i32 %y254 store volatile i32 %select, ptr addrspace(1) poison255 ret void256}257 258attributes #0 = { nounwind }259