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1; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=GCN %s2 3; GCN-LABEL: {{^}}setcc_sgt_true_sext:4; GCN: v_cmp_le_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}5; GCN-NEXT: s_and_saveexec_b64 {{[^,]+}}, [[CC]]6; GCN-NOT: v_cndmask_7 8define amdgpu_kernel void @setcc_sgt_true_sext(ptr addrspace(1) nocapture %arg) {9bb:10 %x = tail call i32 @llvm.amdgcn.workitem.id.x()11 %y = tail call i32 @llvm.amdgcn.workitem.id.y()12 %cmp = icmp ugt i32 %x, %y13 %ext = sext i1 %cmp to i3214 %cond = icmp sgt i32 %ext, -115 br i1 %cond, label %then, label %endif16 17then:18 store i32 1, ptr addrspace(1) %arg, align 419 br label %endif20 21endif:22 ret void23}24 25; GCN-LABEL: {{^}}setcc_sgt_true_sext_swap:26; GCN: v_cmp_le_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}27; GCN-NEXT: s_and_saveexec_b64 {{[^,]+}}, [[CC]]28; GCN-NOT: v_cndmask_29 30define amdgpu_kernel void @setcc_sgt_true_sext_swap(ptr addrspace(1) nocapture %arg) {31bb:32 %x = tail call i32 @llvm.amdgcn.workitem.id.x()33 %y = tail call i32 @llvm.amdgcn.workitem.id.y()34 %cmp = icmp ugt i32 %x, %y35 %ext = sext i1 %cmp to i3236 %cond = icmp slt i32 -1, %ext37 br i1 %cond, label %then, label %endif38 39then:40 store i32 1, ptr addrspace(1) %arg, align 441 br label %endif42 43endif:44 ret void45}46 47; GCN-LABEL: {{^}}setcc_ne_true_sext:48; GCN: v_cmp_le_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}49; GCN-NEXT: s_and_saveexec_b64 {{[^,]+}}, [[CC]]50; GCN-NOT: v_cndmask_51 52define amdgpu_kernel void @setcc_ne_true_sext(ptr addrspace(1) nocapture %arg) {53bb:54 %x = tail call i32 @llvm.amdgcn.workitem.id.x()55 %y = tail call i32 @llvm.amdgcn.workitem.id.y()56 %cmp = icmp ugt i32 %x, %y57 %ext = sext i1 %cmp to i3258 %cond = icmp ne i32 %ext, -159 br i1 %cond, label %then, label %endif60 61then:62 store i32 1, ptr addrspace(1) %arg, align 463 br label %endif64 65endif:66 ret void67}68 69; GCN-LABEL: {{^}}setcc_ult_true_sext:70; GCN: v_cmp_le_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}71; GCN-NEXT: s_and_saveexec_b64 {{[^,]+}}, [[CC]]72; GCN-NOT: v_cndmask_73 74define amdgpu_kernel void @setcc_ult_true_sext(ptr addrspace(1) nocapture %arg) {75bb:76 %x = tail call i32 @llvm.amdgcn.workitem.id.x()77 %y = tail call i32 @llvm.amdgcn.workitem.id.y()78 %cmp = icmp ugt i32 %x, %y79 %ext = sext i1 %cmp to i3280 %cond = icmp ult i32 %ext, -181 br i1 %cond, label %then, label %endif82 83then:84 store i32 1, ptr addrspace(1) %arg, align 485 br label %endif86 87endif:88 ret void89}90 91; GCN-LABEL: {{^}}setcc_eq_true_sext:92; GCN: v_cmp_gt_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}93; GCN-NEXT: s_and_saveexec_b64 {{[^,]+}}, [[CC]]94; GCN-NOT: v_cndmask_95 96define amdgpu_kernel void @setcc_eq_true_sext(ptr addrspace(1) nocapture %arg) {97bb:98 %x = tail call i32 @llvm.amdgcn.workitem.id.x()99 %y = tail call i32 @llvm.amdgcn.workitem.id.y()100 %cmp = icmp ugt i32 %x, %y101 %ext = sext i1 %cmp to i32102 %cond = icmp eq i32 %ext, -1103 br i1 %cond, label %then, label %endif104 105then:106 store i32 1, ptr addrspace(1) %arg, align 4107 br label %endif108 109endif:110 ret void111}112 113; GCN-LABEL: {{^}}setcc_sle_true_sext:114; GCN: v_cmp_gt_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}115; GCN-NEXT: s_and_saveexec_b64 {{[^,]+}}, [[CC]]116; GCN-NOT: v_cndmask_117 118define amdgpu_kernel void @setcc_sle_true_sext(ptr addrspace(1) nocapture %arg) {119bb:120 %x = tail call i32 @llvm.amdgcn.workitem.id.x()121 %y = tail call i32 @llvm.amdgcn.workitem.id.y()122 %cmp = icmp ugt i32 %x, %y123 %ext = sext i1 %cmp to i32124 %cond = icmp sle i32 %ext, -1125 br i1 %cond, label %then, label %endif126 127then:128 store i32 1, ptr addrspace(1) %arg, align 4129 br label %endif130 131endif:132 ret void133}134 135; GCN-LABEL: {{^}}setcc_uge_true_sext:136; GCN: v_cmp_gt_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}137; GCN-NEXT: s_and_saveexec_b64 {{[^,]+}}, [[CC]]138; GCN-NOT: v_cndmask_139 140define amdgpu_kernel void @setcc_uge_true_sext(ptr addrspace(1) nocapture %arg) {141bb:142 %x = tail call i32 @llvm.amdgcn.workitem.id.x()143 %y = tail call i32 @llvm.amdgcn.workitem.id.y()144 %cmp = icmp ugt i32 %x, %y145 %ext = sext i1 %cmp to i32146 %cond = icmp uge i32 %ext, -1147 br i1 %cond, label %then, label %endif148 149then:150 store i32 1, ptr addrspace(1) %arg, align 4151 br label %endif152 153endif:154 ret void155}156 157; GCN-LABEL: {{^}}setcc_eq_false_sext:158; GCN: v_cmp_le_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}159; GCN-NEXT: s_and_saveexec_b64 {{[^,]+}}, [[CC]]160; GCN-NOT: v_cndmask_161 162define amdgpu_kernel void @setcc_eq_false_sext(ptr addrspace(1) nocapture %arg) {163bb:164 %x = tail call i32 @llvm.amdgcn.workitem.id.x()165 %y = tail call i32 @llvm.amdgcn.workitem.id.y()166 %cmp = icmp ugt i32 %x, %y167 %ext = sext i1 %cmp to i32168 %cond = icmp eq i32 %ext, 0169 br i1 %cond, label %then, label %endif170 171then:172 store i32 1, ptr addrspace(1) %arg, align 4173 br label %endif174 175endif:176 ret void177}178 179; GCN-LABEL: {{^}}setcc_sge_false_sext:180; GCN: v_cmp_le_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}181; GCN-NEXT: s_and_saveexec_b64 {{[^,]+}}, [[CC]]182; GCN-NOT: v_cndmask_183 184define amdgpu_kernel void @setcc_sge_false_sext(ptr addrspace(1) nocapture %arg) {185bb:186 %x = tail call i32 @llvm.amdgcn.workitem.id.x()187 %y = tail call i32 @llvm.amdgcn.workitem.id.y()188 %cmp = icmp ugt i32 %x, %y189 %ext = sext i1 %cmp to i32190 %cond = icmp sge i32 %ext, 0191 br i1 %cond, label %then, label %endif192 193then:194 store i32 1, ptr addrspace(1) %arg, align 4195 br label %endif196 197endif:198 ret void199}200 201; GCN-LABEL: {{^}}setcc_ule_false_sext:202; GCN: v_cmp_le_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}203; GCN-NEXT: s_and_saveexec_b64 {{[^,]+}}, [[CC]]204; GCN-NOT: v_cndmask_205 206define amdgpu_kernel void @setcc_ule_false_sext(ptr addrspace(1) nocapture %arg) {207bb:208 %x = tail call i32 @llvm.amdgcn.workitem.id.x()209 %y = tail call i32 @llvm.amdgcn.workitem.id.y()210 %cmp = icmp ugt i32 %x, %y211 %ext = sext i1 %cmp to i32212 %cond = icmp ule i32 %ext, 0213 br i1 %cond, label %then, label %endif214 215then:216 store i32 1, ptr addrspace(1) %arg, align 4217 br label %endif218 219endif:220 ret void221}222 223; GCN-LABEL: {{^}}setcc_ne_false_sext:224; GCN: v_cmp_gt_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}225; GCN-NEXT: s_and_saveexec_b64 {{[^,]+}}, [[CC]]226; GCN-NOT: v_cndmask_227 228define amdgpu_kernel void @setcc_ne_false_sext(ptr addrspace(1) nocapture %arg) {229bb:230 %x = tail call i32 @llvm.amdgcn.workitem.id.x()231 %y = tail call i32 @llvm.amdgcn.workitem.id.y()232 %cmp = icmp ugt i32 %x, %y233 %ext = sext i1 %cmp to i32234 %cond = icmp ne i32 %ext, 0235 br i1 %cond, label %then, label %endif236 237then:238 store i32 1, ptr addrspace(1) %arg, align 4239 br label %endif240 241endif:242 ret void243}244; GCN-LABEL: {{^}}setcc_ugt_false_sext:245; GCN: v_cmp_gt_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}246; GCN-NEXT: s_and_saveexec_b64 {{[^,]+}}, [[CC]]247; GCN-NOT: v_cndmask_248 249define amdgpu_kernel void @setcc_ugt_false_sext(ptr addrspace(1) nocapture %arg) {250bb:251 %x = tail call i32 @llvm.amdgcn.workitem.id.x()252 %y = tail call i32 @llvm.amdgcn.workitem.id.y()253 %cmp = icmp ugt i32 %x, %y254 %ext = sext i1 %cmp to i32255 %cond = icmp ugt i32 %ext, 0256 br i1 %cond, label %then, label %endif257 258then:259 store i32 1, ptr addrspace(1) %arg, align 4260 br label %endif261 262endif:263 ret void264}265; GCN-LABEL: {{^}}setcc_slt_false_sext:266; GCN: v_cmp_gt_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}267; GCN-NEXT: s_and_saveexec_b64 {{[^,]+}}, [[CC]]268; GCN-NOT: v_cndmask_269 270define amdgpu_kernel void @setcc_slt_false_sext(ptr addrspace(1) nocapture %arg) {271bb:272 %x = tail call i32 @llvm.amdgcn.workitem.id.x()273 %y = tail call i32 @llvm.amdgcn.workitem.id.y()274 %cmp = icmp ugt i32 %x, %y275 %ext = sext i1 %cmp to i32276 %cond = icmp slt i32 %ext, 0277 br i1 %cond, label %then, label %endif278 279then:280 store i32 1, ptr addrspace(1) %arg, align 4281 br label %endif282 283endif:284 ret void285}286 287 288declare i32 @llvm.amdgcn.workitem.id.x() #0289 290declare i32 @llvm.amdgcn.workitem.id.y() #0291 292attributes #0 = { nounwind readnone speculatable }293