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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -enable-var-scope --check-prefixes=GFX11-TRUE16 %s3; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -enable-var-scope --check-prefixes=GFX11-FAKE16 %s4 5define amdgpu_kernel void @v_sext_in_reg_i8_i16_shuffle_vector(ptr addrspace(1) %out, ptr addrspace(1) %ptr) #0 {6;7; GFX11-TRUE16-LABEL: v_sext_in_reg_i8_i16_shuffle_vector:8; GFX11-TRUE16: ; %bb.0:9; GFX11-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x2410; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0x3ff, v011; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)12; GFX11-TRUE16-NEXT: global_load_b64 v[1:2], v0, s[2:3]13; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)14; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v2.h15; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v1.h16; GFX11-TRUE16-NEXT: v_bfe_i32 v7, v2, 0, 817; GFX11-TRUE16-NEXT: v_ashrrev_i32_e32 v5, 24, v218; GFX11-TRUE16-NEXT: v_ashrrev_i32_e32 v6, 24, v119; GFX11-TRUE16-NEXT: v_bfe_i32 v8, v3, 0, 820; GFX11-TRUE16-NEXT: v_ashrrev_i16 v0.l, 8, v1.l21; GFX11-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 822; GFX11-TRUE16-NEXT: v_ashrrev_i16 v0.h, 8, v2.l23; GFX11-TRUE16-NEXT: v_bfe_i32 v3, v4, 0, 824; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.l25; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v8.l26; GFX11-TRUE16-NEXT: v_cvt_f16_i16_e32 v0.l, v0.l27; GFX11-TRUE16-NEXT: v_cvt_f16_i16_e32 v0.h, v0.h28; GFX11-TRUE16-NEXT: v_cvt_f16_i16_e32 v2.h, v6.l29; GFX11-TRUE16-NEXT: v_cvt_f16_i16_e32 v4.h, v5.l30; GFX11-TRUE16-NEXT: v_cvt_f16_i16_e32 v1.l, v1.l31; GFX11-TRUE16-NEXT: v_cvt_f16_i16_e32 v1.h, v2.l32; GFX11-TRUE16-NEXT: v_cvt_f16_i16_e32 v2.l, v3.l33; GFX11-TRUE16-NEXT: v_cvt_f16_i16_e32 v4.l, v4.l34; GFX11-TRUE16-NEXT: v_mov_b32_e32 v5, 035; GFX11-TRUE16-NEXT: v_pack_b32_f16 v3, v0.l, v1.l36; GFX11-TRUE16-NEXT: v_pack_b32_f16 v1, v0.h, v1.h37; GFX11-TRUE16-NEXT: v_pack_b32_f16 v2, v2.h, v2.l38; GFX11-TRUE16-NEXT: v_pack_b32_f16 v0, v4.h, v4.l39; GFX11-TRUE16-NEXT: global_store_b128 v5, v[0:3], s[0:1]40; GFX11-TRUE16-NEXT: s_endpgm41;42; GFX11-FAKE16-LABEL: v_sext_in_reg_i8_i16_shuffle_vector:43; GFX11-FAKE16: ; %bb.0:44; GFX11-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x2445; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0x3ff, v046; GFX11-FAKE16-NEXT: v_mov_b32_e32 v10, 047; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)48; GFX11-FAKE16-NEXT: global_load_b64 v[0:1], v0, s[2:3]49; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)50; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v151; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v052; GFX11-FAKE16-NEXT: v_ashrrev_i32_e32 v3, 24, v153; GFX11-FAKE16-NEXT: v_ashrrev_i32_e32 v5, 24, v054; GFX11-FAKE16-NEXT: v_ashrrev_i16 v6, 8, v155; GFX11-FAKE16-NEXT: v_bfe_i32 v7, v0, 0, 856; GFX11-FAKE16-NEXT: v_ashrrev_i16 v0, 8, v057; GFX11-FAKE16-NEXT: v_bfe_i32 v1, v1, 0, 858; GFX11-FAKE16-NEXT: v_bfe_i32 v2, v2, 0, 859; GFX11-FAKE16-NEXT: v_bfe_i32 v4, v4, 0, 860; GFX11-FAKE16-NEXT: v_cvt_f16_i16_e32 v7, v761; GFX11-FAKE16-NEXT: v_cvt_f16_i16_e32 v0, v062; GFX11-FAKE16-NEXT: v_cvt_f16_i16_e32 v1, v163; GFX11-FAKE16-NEXT: v_cvt_f16_i16_e32 v6, v664; GFX11-FAKE16-NEXT: v_cvt_f16_i16_e32 v5, v565; GFX11-FAKE16-NEXT: v_cvt_f16_i16_e32 v8, v366; GFX11-FAKE16-NEXT: v_cvt_f16_i16_e32 v4, v467; GFX11-FAKE16-NEXT: v_cvt_f16_i16_e32 v9, v268; GFX11-FAKE16-NEXT: v_pack_b32_f16 v3, v0, v769; GFX11-FAKE16-NEXT: v_pack_b32_f16 v1, v6, v170; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)71; GFX11-FAKE16-NEXT: v_pack_b32_f16 v2, v5, v472; GFX11-FAKE16-NEXT: v_pack_b32_f16 v0, v8, v973; GFX11-FAKE16-NEXT: global_store_b128 v10, v[0:3], s[0:1]74; GFX11-FAKE16-NEXT: s_endpgm75 %tid = call i32 @llvm.amdgcn.workitem.id.x()76 %in.gep = getelementptr <{ [0 x i8] }>, ptr addrspace(1) %ptr, i64 0, i32 0, i32 %tid77 %load = load <8 x i8>, ptr addrspace(1) %in.gep78 %shuff = shufflevector <8 x i8> %load, <8 x i8> poison, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>79 %cast = sitofp <8 x i8> %shuff to <8 x half>80 store <8 x half> %cast, ptr addrspace(1) %out81 ret void82}83 84declare i32 @llvm.amdgcn.workitem.id.x() #185 86attributes #0 = { nounwind }87attributes #1 = { nounwind readnone }88