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1; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck %s2; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck %s3 4; CHECK-LABEL: {{^}}phi1:5; CHECK: s_buffer_load_dword [[DST:s[0-9]]], {{s\[[0-9]+:[0-9]+\]}}, 0x06; CHECK: ; %bb.1: ; %ELSE7; CHECK: s_xor_b32 s{{[0-9]}}, [[DST]]8define amdgpu_ps void @phi1(ptr addrspace(4) inreg %arg, ptr addrspace(4) inreg %arg1, ptr addrspace(4) inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #0 {9main_body:10 %tmp20 = load <4 x i32>, ptr addrspace(4) %arg, !tbaa !011 %tmp21 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 0, i32 0)12 %tmp22 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 16, i32 0)13 %tmp23 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 32, i32 0)14 %tmp24 = fptosi float %tmp22 to i3215 %tmp25 = icmp ne i32 %tmp24, 016 br i1 %tmp25, label %ENDIF, label %ELSE17 18ELSE: ; preds = %main_body19 %tmp26 = fsub float -0.000000e+00, %tmp2120 br label %ENDIF21 22ENDIF: ; preds = %ELSE, %main_body23 %temp.0 = phi float [ %tmp26, %ELSE ], [ %tmp21, %main_body ]24 %tmp27 = fadd float %temp.0, %tmp2325 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %tmp27, float %tmp27, float 0.000000e+00, float 1.000000e+00, i1 true, i1 true) #026 ret void27}28 29; Make sure this program doesn't crash30; CHECK-LABEL: {{^}}phi2:31define amdgpu_ps void @phi2(ptr addrspace(4) inreg %arg, ptr addrspace(4) inreg %arg1, ptr addrspace(4) inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #1 {32main_body:33 %tmp20 = load <4 x i32>, ptr addrspace(4) %arg, !tbaa !034 %tmp21 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 16, i32 0)35 %tmp22 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 32, i32 0)36 %tmp23 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 36, i32 0)37 %tmp24 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 40, i32 0)38 %tmp25 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 48, i32 0)39 %tmp26 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 52, i32 0)40 %tmp27 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 56, i32 0)41 %tmp28 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 64, i32 0)42 %tmp29 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 68, i32 0)43 %tmp30 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 72, i32 0)44 %tmp31 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 76, i32 0)45 %tmp32 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 80, i32 0)46 %tmp33 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 84, i32 0)47 %tmp34 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 88, i32 0)48 %tmp35 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 92, i32 0)49 %tmp37 = load <8 x i32>, ptr addrspace(4) %arg2, !tbaa !050 %tmp39 = load <4 x i32>, ptr addrspace(4) %arg1, !tbaa !051 %i.i = extractelement <2 x i32> %arg5, i32 052 %j.i = extractelement <2 x i32> %arg5, i32 153 %i.f.i = bitcast i32 %i.i to float54 %j.f.i = bitcast i32 %j.i to float55 %p1.i = call float @llvm.amdgcn.interp.p1(float %i.f.i, i32 0, i32 0, i32 %arg3) #156 %p2.i = call float @llvm.amdgcn.interp.p2(float %p1.i, float %j.f.i, i32 0, i32 0, i32 %arg3) #157 %i.i19 = extractelement <2 x i32> %arg5, i32 058 %j.i20 = extractelement <2 x i32> %arg5, i32 159 %i.f.i21 = bitcast i32 %i.i19 to float60 %j.f.i22 = bitcast i32 %j.i20 to float61 %p1.i23 = call float @llvm.amdgcn.interp.p1(float %i.f.i21, i32 1, i32 0, i32 %arg3) #162 %p2.i24 = call float @llvm.amdgcn.interp.p2(float %p1.i23, float %j.f.i22, i32 1, i32 0, i32 %arg3) #163 %i.i13 = extractelement <2 x i32> %arg5, i32 064 %j.i14 = extractelement <2 x i32> %arg5, i32 165 %i.f.i15 = bitcast i32 %i.i13 to float66 %j.f.i16 = bitcast i32 %j.i14 to float67 %p1.i17 = call float @llvm.amdgcn.interp.p1(float %i.f.i15, i32 0, i32 1, i32 %arg3) #168 %p2.i18 = call float @llvm.amdgcn.interp.p2(float %p1.i17, float %j.f.i16, i32 0, i32 1, i32 %arg3) #169 %i.i7 = extractelement <2 x i32> %arg5, i32 070 %j.i8 = extractelement <2 x i32> %arg5, i32 171 %i.f.i9 = bitcast i32 %i.i7 to float72 %j.f.i10 = bitcast i32 %j.i8 to float73 %p1.i11 = call float @llvm.amdgcn.interp.p1(float %i.f.i9, i32 1, i32 1, i32 %arg3) #174 %p2.i12 = call float @llvm.amdgcn.interp.p2(float %p1.i11, float %j.f.i10, i32 1, i32 1, i32 %arg3) #175 %i.i1 = extractelement <2 x i32> %arg5, i32 076 %j.i2 = extractelement <2 x i32> %arg5, i32 177 %i.f.i3 = bitcast i32 %i.i1 to float78 %j.f.i4 = bitcast i32 %j.i2 to float79 %p1.i5 = call float @llvm.amdgcn.interp.p1(float %i.f.i3, i32 2, i32 1, i32 %arg3) #180 %p2.i6 = call float @llvm.amdgcn.interp.p2(float %p1.i5, float %j.f.i4, i32 2, i32 1, i32 %arg3) #181 %tmp39.bc = bitcast <4 x i32> %tmp39 to <4 x i32>82 %tmp1 = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float %p2.i, float %p2.i24, <8 x i32> %tmp37, <4 x i32> %tmp39.bc, i1 0, i32 0, i32 0)83 %tmp50 = extractelement <4 x float> %tmp1, i32 284 %tmp51 = call float @llvm.fabs.f32(float %tmp50)85 %tmp52 = fmul float %p2.i18, %p2.i1886 %tmp53 = fmul float %p2.i12, %p2.i1287 %tmp54 = fadd float %tmp53, %tmp5288 %tmp55 = fmul float %p2.i6, %p2.i689 %tmp56 = fadd float %tmp54, %tmp5590 %tmp57 = call float @llvm.amdgcn.rsq.f32(float %tmp56)91 %tmp58 = fmul float %p2.i18, %tmp5792 %tmp59 = fmul float %p2.i12, %tmp5793 %tmp60 = fmul float %p2.i6, %tmp5794 %tmp61 = fmul float %tmp58, %tmp2295 %tmp62 = fmul float %tmp59, %tmp2396 %tmp63 = fadd float %tmp62, %tmp6197 %tmp64 = fmul float %tmp60, %tmp2498 %tmp65 = fadd float %tmp63, %tmp6499 %tmp66 = fsub float -0.000000e+00, %tmp25100 %tmp67 = fmul float %tmp65, %tmp51101 %tmp68 = fadd float %tmp67, %tmp66102 %tmp69 = fmul float %tmp26, %tmp68103 %tmp70 = fmul float %tmp27, %tmp68104 %tmp71 = call float @llvm.fabs.f32(float %tmp69)105 %tmp72 = fcmp olt float 0x3EE4F8B580000000, %tmp71106 %tmp73 = sext i1 %tmp72 to i32107 %tmp74 = bitcast i32 %tmp73 to float108 %tmp75 = bitcast float %tmp74 to i32109 %tmp76 = icmp ne i32 %tmp75, 0110 br i1 %tmp76, label %IF, label %ENDIF111 112IF: ; preds = %main_body113 %tmp77 = fsub float -0.000000e+00, %tmp69114 %tmp78 = call float @llvm.exp2.f32(float %tmp77)115 %tmp79 = fsub float -0.000000e+00, %tmp78116 %tmp80 = fadd float 1.000000e+00, %tmp79117 %tmp81 = fdiv float 1.000000e+00, %tmp69118 %tmp82 = fmul float %tmp80, %tmp81119 %tmp83 = fmul float %tmp31, %tmp82120 br label %ENDIF121 122ENDIF: ; preds = %IF, %main_body123 %temp4.0 = phi float [ %tmp83, %IF ], [ %tmp31, %main_body ]124 %tmp84 = call float @llvm.fabs.f32(float %tmp70)125 %tmp85 = fcmp olt float 0x3EE4F8B580000000, %tmp84126 %tmp86 = sext i1 %tmp85 to i32127 %tmp87 = bitcast i32 %tmp86 to float128 %tmp88 = bitcast float %tmp87 to i32129 %tmp89 = icmp ne i32 %tmp88, 0130 br i1 %tmp89, label %IF25, label %ENDIF24131 132IF25: ; preds = %ENDIF133 %tmp90 = fsub float -0.000000e+00, %tmp70134 %tmp91 = call float @llvm.exp2.f32(float %tmp90)135 %tmp92 = fsub float -0.000000e+00, %tmp91136 %tmp93 = fadd float 1.000000e+00, %tmp92137 %tmp94 = fdiv float 1.000000e+00, %tmp70138 %tmp95 = fmul float %tmp93, %tmp94139 %tmp96 = fmul float %tmp35, %tmp95140 br label %ENDIF24141 142ENDIF24: ; preds = %IF25, %ENDIF143 %temp8.0 = phi float [ %tmp96, %IF25 ], [ %tmp35, %ENDIF ]144 %tmp97 = fmul float %tmp28, %temp4.0145 %tmp98 = fmul float %tmp29, %temp4.0146 %tmp99 = fmul float %tmp30, %temp4.0147 %tmp100 = fmul float %tmp32, %temp8.0148 %tmp101 = fadd float %tmp100, %tmp97149 %tmp102 = fmul float %tmp33, %temp8.0150 %tmp103 = fadd float %tmp102, %tmp98151 %tmp104 = fmul float %tmp34, %temp8.0152 %tmp105 = fadd float %tmp104, %tmp99153 %tmp106 = call float @llvm.pow.f32(float %tmp51, float %tmp21)154 %tmp107 = fsub float -0.000000e+00, %tmp101155 %tmp108 = fmul float %tmp107, %tmp106156 %tmp109 = fsub float -0.000000e+00, %tmp103157 %tmp110 = fmul float %tmp109, %tmp106158 %tmp111 = fsub float -0.000000e+00, %tmp105159 %tmp112 = fmul float %tmp111, %tmp106160 %tmp113 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %tmp108, float %tmp110)161 %tmp115 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %tmp112, float 1.000000e+00)162 call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> %tmp113, <2 x half> %tmp115, i1 true, i1 true) #0163 ret void164}165 166; We just want to make sure the program doesn't crash167; CHECK-LABEL: {{^}}loop:168define amdgpu_ps void @loop(ptr addrspace(4) inreg %arg, ptr addrspace(4) inreg %arg1, ptr addrspace(4) inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #0 {169main_body:170 %tmp20 = load <4 x i32>, ptr addrspace(4) %arg, !tbaa !0171 %tmp21 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 0, i32 0)172 %tmp22 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 4, i32 0)173 %tmp23 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 8, i32 0)174 %tmp24 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 12, i32 0)175 %tmp25 = fptosi float %tmp24 to i32176 %tmp26 = bitcast i32 %tmp25 to float177 %tmp27 = bitcast float %tmp26 to i32178 br label %LOOP179 180LOOP: ; preds = %ENDIF, %main_body181 %temp4.0 = phi float [ %tmp21, %main_body ], [ %temp5.0, %ENDIF ]182 %temp5.0 = phi float [ %tmp22, %main_body ], [ %temp6.0, %ENDIF ]183 %temp6.0 = phi float [ %tmp23, %main_body ], [ %temp4.0, %ENDIF ]184 %temp8.0 = phi float [ 0.000000e+00, %main_body ], [ %tmp36, %ENDIF ]185 %tmp28 = bitcast float %temp8.0 to i32186 %tmp29 = icmp sge i32 %tmp28, %tmp27187 %tmp30 = sext i1 %tmp29 to i32188 %tmp31 = bitcast i32 %tmp30 to float189 %tmp32 = bitcast float %tmp31 to i32190 %tmp33 = icmp ne i32 %tmp32, 0191 br i1 %tmp33, label %IF, label %ENDIF192 193IF: ; preds = %LOOP194 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %temp4.0, float %temp5.0, float %temp6.0, float 1.000000e+00, i1 true, i1 true) #0195 ret void196 197ENDIF: ; preds = %LOOP198 %tmp34 = bitcast float %temp8.0 to i32199 %tmp35 = add i32 %tmp34, 1200 %tmp36 = bitcast i32 %tmp35 to float201 br label %LOOP202}203 204; This checks for a bug in the FixSGPRCopies pass where VReg96205; registers were being identified as an SGPR regclass which was causing206; an assertion failure.207 208; CHECK-LABEL: {{^}}sample_v3:209; CHECK: v_mov_b32_e32 v[[SAMPLE_LO:[0-9]+]], 5210; CHECK: v_mov_b32_e32 v[[SAMPLE_HI:[0-9]+]], 7211; CHECK: s_cbranch212 213; CHECK: BB{{[0-9]+_[0-9]+}}:214; CHECK-DAG: v_mov_b32_e32 v[[SAMPLE_LO:[0-9]+]], 11215; CHECK-DAG: v_mov_b32_e32 v[[SAMPLE_HI:[0-9]+]], 13216 217; CHECK: image_sample v{{\[[0-9]+:[0-9]+\]}}, v[[[SAMPLE_LO]]:[[SAMPLE_HI]]]218; CHECK: exp219; CHECK: s_endpgm220define amdgpu_ps void @sample_v3(ptr addrspace(4) inreg %arg, ptr addrspace(4) inreg %arg1, ptr addrspace(4) inreg %arg2, float inreg %arg3, i32 inreg %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, float %arg20) #0 {221entry:222 %tmp21 = load <4 x i32>, ptr addrspace(4) %arg, !tbaa !0223 %tmp22 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 16, i32 0)224 %tmp24 = load <8 x i32>, ptr addrspace(4) %arg2, !tbaa !0225 %tmp26 = load <4 x i32>, ptr addrspace(4) %arg1, !tbaa !0226 %tmp27 = fcmp oeq float %tmp22, 0.000000e+00227 %tmp26.bc = bitcast <4 x i32> %tmp26 to <4 x i32>228 br i1 %tmp27, label %if, label %else229 230if: ; preds = %entry231 %tmp1 = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float 0x36D6000000000000, float 0x36DA000000000000, <8 x i32> %tmp24, <4 x i32> %tmp26.bc, i1 0, i32 0, i32 0)232 %val.if.0 = extractelement <4 x float> %tmp1, i32 0233 %val.if.1 = extractelement <4 x float> %tmp1, i32 1234 %val.if.2 = extractelement <4 x float> %tmp1, i32 2235 br label %endif236 237else: ; preds = %entry238 %tmp2 = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float 0x36C4000000000000, float 0x36CC000000000000, <8 x i32> %tmp24, <4 x i32> %tmp26.bc, i1 0, i32 0, i32 0)239 %val.else.0 = extractelement <4 x float> %tmp2, i32 0240 %val.else.1 = extractelement <4 x float> %tmp2, i32 1241 %val.else.2 = extractelement <4 x float> %tmp2, i32 2242 br label %endif243 244endif: ; preds = %else, %if245 %val.0 = phi float [ %val.if.0, %if ], [ %val.else.0, %else ]246 %val.1 = phi float [ %val.if.1, %if ], [ %val.else.1, %else ]247 %val.2 = phi float [ %val.if.2, %if ], [ %val.else.2, %else ]248 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %val.0, float %val.1, float %val.2, float 0.000000e+00, i1 true, i1 true) #0249 ret void250}251 252; CHECK-LABEL: {{^}}copy1:253; CHECK: buffer_load_dword254; CHECK: v_add255; CHECK: s_endpgm256define amdgpu_kernel void @copy1(ptr addrspace(1) %out, ptr addrspace(1) %in0) {257entry:258 %tmp = load float, ptr addrspace(1) %in0259 %tmp1 = fcmp one float %tmp, 0.000000e+00260 br i1 %tmp1, label %if0, label %endif261 262if0: ; preds = %entry263 %tmp2 = bitcast float %tmp to i32264 %tmp3 = fcmp olt float %tmp, 0.000000e+00265 br i1 %tmp3, label %if1, label %endif266 267if1: ; preds = %if0268 %tmp4 = add i32 %tmp2, 1269 br label %endif270 271endif: ; preds = %if1, %if0, %entry272 %tmp5 = phi i32 [ 0, %entry ], [ %tmp2, %if0 ], [ %tmp4, %if1 ]273 %tmp6 = bitcast i32 %tmp5 to float274 store float %tmp6, ptr addrspace(1) %out275 ret void276}277 278; This test is just checking that we don't crash / assertion fail.279; CHECK-LABEL: {{^}}copy2:280; CHECK: s_endpgm281define amdgpu_ps void @copy2(ptr addrspace(4) inreg %arg, ptr addrspace(4) inreg %arg1, ptr addrspace(4) inreg %arg2, float inreg %arg3, i32 inreg %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, float %arg20) #0 {282entry:283 br label %LOOP68284 285LOOP68: ; preds = %ENDIF69, %entry286 %temp4.7 = phi float [ 0.000000e+00, %entry ], [ %v, %ENDIF69 ]287 %t = phi i32 [ 20, %entry ], [ %x, %ENDIF69 ]288 %g = icmp eq i32 0, %t289 %l = bitcast float %temp4.7 to i32290 br i1 %g, label %IF70, label %ENDIF69291 292IF70: ; preds = %LOOP68293 %q = icmp ne i32 %l, 13294 %temp.8 = select i1 %q, float 1.000000e+00, float 0.000000e+00295 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %temp.8, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00, i1 true, i1 true) #0296 ret void297 298ENDIF69: ; preds = %LOOP68299 %u = add i32 %l, %t300 %v = bitcast i32 %u to float301 %x = add i32 %t, -1302 br label %LOOP68303}304 305; This test checks that image_sample resource descriptors aren't loaded into306; vgprs. The verifier will fail if this happens.307; CHECK-LABEL:{{^}}sample_rsrc308 309; CHECK: s_cmp_eq_u32310; CHECK: s_cbranch_scc1 [[END:.LBB[0-9]+_[0-9]+]]311 312; CHECK: image_sample v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}313; CHECK: s_endpgm314 315; [[END]]:316; CHECK: v_add_{{[iu]}}32_e32 v[[ADD:[0-9]+]], vcc, 1, v{{[0-9]+}}317; CHECK: image_sample v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+}}:[[ADD]]]318; CHECK: s_branch319define amdgpu_ps void @sample_rsrc(ptr addrspace(4) inreg %arg, ptr addrspace(4) inreg %arg1, ptr addrspace(4) inreg %arg2, ptr addrspace(4) inreg %arg3, float inreg %arg4, i32 inreg %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, <2 x i32> %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, i32 %arg19, float %arg20, float %arg21) #0 {320bb:321 %tmp22 = load <4 x i32>, ptr addrspace(4) %arg1, !tbaa !3322 %tmp23 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp22, i32 16, i32 0)323 %tmp26 = load <8 x i32>, ptr addrspace(4) %arg3, !tbaa !3324 %tmp28 = load <4 x i32>, ptr addrspace(4) %arg2, !tbaa !3325 %i.i = extractelement <2 x i32> %arg7, i32 0326 %j.i = extractelement <2 x i32> %arg7, i32 1327 %i.f.i = bitcast i32 %i.i to float328 %j.f.i = bitcast i32 %j.i to float329 %p1.i = call float @llvm.amdgcn.interp.p1(float %i.f.i, i32 0, i32 0, i32 %arg5) #0330 %p2.i = call float @llvm.amdgcn.interp.p2(float %p1.i, float %j.f.i, i32 0, i32 0, i32 %arg5) #0331 %i.i1 = extractelement <2 x i32> %arg7, i32 0332 %j.i2 = extractelement <2 x i32> %arg7, i32 1333 %i.f.i3 = bitcast i32 %i.i1 to float334 %j.f.i4 = bitcast i32 %j.i2 to float335 %p1.i5 = call float @llvm.amdgcn.interp.p1(float %i.f.i3, i32 1, i32 0, i32 %arg5) #0336 %p2.i6 = call float @llvm.amdgcn.interp.p2(float %p1.i5, float %j.f.i4, i32 1, i32 0, i32 %arg5) #0337 %tmp31 = bitcast float %tmp23 to i32338 %tmp36 = icmp ne i32 %tmp31, 0339 br i1 %tmp36, label %bb38, label %bb80340 341bb38: ; preds = %bb342 %tmp56 = bitcast <8 x i32> %tmp26 to <8 x i32>343 %tmp2 = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float %p2.i, float %p2.i6, <8 x i32> %tmp56, <4 x i32> %tmp28, i1 0, i32 0, i32 0)344 br label %bb71345 346bb80: ; preds = %bb347 %tmp81 = bitcast float %p2.i to i32348 %tmp82 = bitcast float %p2.i6 to i32349 %tmp82.2 = add i32 %tmp82, 1350 %tmp83 = bitcast i32 %tmp81 to float351 %tmp84 = bitcast i32 %tmp82.2 to float352 %tmp85 = bitcast <8 x i32> %tmp26 to <8 x i32>353 %tmp3 = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float %tmp83, float %tmp84, <8 x i32> %tmp85, <4 x i32> %tmp28, i1 0, i32 0, i32 0)354 br label %bb71355 356bb71: ; preds = %bb80, %bb38357 %tmp72 = phi <4 x float> [ %tmp2, %bb38 ], [ %tmp3, %bb80 ]358 %tmp88 = extractelement <4 x float> %tmp72, i32 0359 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %tmp88, float %tmp88, float %tmp88, float %tmp88, i1 true, i1 true) #0360 ret void361}362 363; Check the resource descriptor is stored in an sgpr.364; CHECK-LABEL: {{^}}mimg_srsrc_sgpr:365; CHECK: image_sample v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] dmask:0x1366define amdgpu_ps void @mimg_srsrc_sgpr(ptr addrspace(4) inreg %arg) #0 {367bb:368 %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0369 %tmp7 = getelementptr [34 x <8 x i32>], ptr addrspace(4) %arg, i32 0, i32 %tid370 %tmp8 = load <8 x i32>, ptr addrspace(4) %tmp7, align 32, !tbaa !0371 %tmp = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float 7.500000e-01, float 2.500000e-01, <8 x i32> %tmp8, <4 x i32> poison, i1 0, i32 0, i32 0)372 %tmp10 = extractelement <4 x float> %tmp, i32 0373 %tmp12 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float poison, float %tmp10)374 call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> %tmp12, <2 x half> poison, i1 true, i1 true) #0375 ret void376}377 378; Check the sampler is stored in an sgpr.379; CHECK-LABEL: {{^}}mimg_ssamp_sgpr:380; CHECK: image_sample v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] dmask:0x1381define amdgpu_ps void @mimg_ssamp_sgpr(ptr addrspace(4) inreg %arg) #0 {382bb:383 %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0384 %tmp7 = getelementptr [17 x <4 x i32>], ptr addrspace(4) %arg, i32 0, i32 %tid385 %tmp8 = load <4 x i32>, ptr addrspace(4) %tmp7, align 16, !tbaa !0386 %tmp = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float 7.500000e-01, float 2.500000e-01, <8 x i32> poison, <4 x i32> %tmp8, i1 0, i32 0, i32 0)387 %tmp10 = extractelement <4 x float> %tmp, i32 0388 %tmp12 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %tmp10, float poison)389 call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> %tmp12, <2 x half> poison, i1 true, i1 true) #0390 ret void391}392 393declare float @llvm.fabs.f32(float) #1394declare float @llvm.amdgcn.rsq.f32(float) #1395declare float @llvm.exp2.f32(float) #1396declare float @llvm.pow.f32(float, float) #1397declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #1398declare float @llvm.amdgcn.interp.p1(float, i32, i32, i32) #1399declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32) #1400declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0401declare void @llvm.amdgcn.exp.compr.v2f16(i32, i32, <2 x half>, <2 x half>, i1, i1) #0402declare <2 x half> @llvm.amdgcn.cvt.pkrtz(float, float) #1403declare <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #2404declare float @llvm.amdgcn.s.buffer.load.f32(<4 x i32>, i32, i32) #1405 406attributes #0 = { nounwind }407attributes #1 = { nounwind readnone }408attributes #2 = { nounwind readonly }409 410!0 = !{!1, !1, i64 0, i32 1}411!1 = !{!"const", !2}412!2 = !{!"tbaa root"}413!3 = !{!1, !1, i64 0}414