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1; REQUIRES: asserts2 3; RUN: llc -verify-machineinstrs=0 -mtriple=amdgcn-amd-amdhsa -debug-pass=Structure -filetype=null %s 2>&1 | FileCheck -check-prefix=DEFAULT %s4; RUN: llc -verify-machineinstrs=0 -sgpr-regalloc=greedy -wwm-regalloc=greedy -vgpr-regalloc=greedy -mtriple=amdgcn-amd-amdhsa -debug-pass=Structure -filetype=null %s 2>&1 | FileCheck -check-prefix=DEFAULT %s5 6; RUN: llc -verify-machineinstrs=0 -O0 -mtriple=amdgcn-amd-amdhsa -debug-pass=Structure -filetype=null %s 2>&1 | FileCheck -check-prefix=O0 %s7 8; RUN: llc -verify-machineinstrs=0 -wwm-regalloc=basic -vgpr-regalloc=basic -mtriple=amdgcn-amd-amdhsa -debug-pass=Structure -filetype=null %s 2>&1 | FileCheck -check-prefix=DEFAULT-BASIC %s9; RUN: llc -verify-machineinstrs=0 -sgpr-regalloc=basic -mtriple=amdgcn-amd-amdhsa -debug-pass=Structure -filetype=null %s 2>&1 | FileCheck -check-prefix=BASIC-DEFAULT %s10; RUN: llc -verify-machineinstrs=0 -sgpr-regalloc=basic -wwm-regalloc=basic -vgpr-regalloc=basic -mtriple=amdgcn-amd-amdhsa -debug-pass=Structure -filetype=null %s 2>&1 | FileCheck -check-prefix=BASIC-BASIC %s11 12; RUN: not llc -verify-machineinstrs=0 -regalloc=basic -mtriple=amdgcn-amd-amdhsa -debug-pass=Structure -filetype=null %s 2>&1 | FileCheck -check-prefix=REGALLOC %s13; RUN: not llc -verify-machineinstrs=0 -regalloc=fast -O0 -mtriple=amdgcn-amd-amdhsa -debug-pass=Structure -filetype=null %s 2>&1 | FileCheck -check-prefix=REGALLOC %s14 15 16; REGALLOC: -regalloc not supported with amdgcn. Use -sgpr-regalloc, -wwm-regalloc, and -vgpr-regalloc17 18; DEFAULT: Greedy Register Allocator19; DEFAULT-NEXT: Virtual Register Rewriter20; DEFAULT-NEXT: Stack Slot Coloring21; DEFAULT-NEXT: SI lower SGPR spill instructions22; DEFAULT-NEXT: Virtual Register Map23; DEFAULT-NEXT: Live Register Matrix24; DEFAULT-NEXT: SI Pre-allocate WWM Registers25; DEFAULT-NEXT: Live Stack Slot Analysis26; DEFAULT-NEXT: Greedy Register Allocator27; DEFAULT-NEXT: SI Lower WWM Copies28; DEFAULT-NEXT: Virtual Register Rewriter29; DEFAULT-NEXT: AMDGPU Reserve WWM Registers30; DEFAULT-NEXT: Virtual Register Map31; DEFAULT-NEXT: Live Register Matrix32; DEFAULT-NEXT: Greedy Register Allocator33; DEFAULT-NEXT: GCN NSA Reassign34; DEFAULT-NEXT: AMDGPU Rewrite AGPR-Copy-MFMA35; DEFAULT-NEXT: Virtual Register Rewriter36; DEFAULT-NEXT: AMDGPU Mark Last Scratch Load37; DEFAULT-NEXT: Stack Slot Coloring38 39; O0: Fast Register Allocator40; O0-NEXT: SI lower SGPR spill instructions41; O0-NEXT: Slot index numbering42; O0-NEXT: Live Interval Analysis43; O0-NEXT: Virtual Register Map44; O0-NEXT: Live Register Matrix45; O0-NEXT: SI Pre-allocate WWM Registers46; O0-NEXT: Fast Register Allocator47; O0-NEXT: SI Lower WWM Copies48; O0-NEXT: AMDGPU Reserve WWM Registers49; O0-NEXT: Fast Register Allocator50; O0-NEXT: SI Fix VGPR copies51 52 53 54 55; BASIC-DEFAULT: Debug Variable Analysis56; BASIC-DEFAULT-NEXT: Live Stack Slot Analysis57; BASIC-DEFAULT-NEXT: Machine Natural Loop Construction58; BASIC-DEFAULT-NEXT: Machine Block Frequency Analysis59; BASIC-DEFAULT-NEXT: Virtual Register Map60; BASIC-DEFAULT-NEXT: Live Register Matrix61; BASIC-DEFAULT-NEXT: Basic Register Allocator62; BASIC-DEFAULT-NEXT: Virtual Register Rewriter63; BASIC-DEFAULT-NEXT: Stack Slot Coloring64; BASIC-DEFAULT-NEXT: SI lower SGPR spill instructions65; BASIC-DEFAULT-NEXT: Virtual Register Map66; BASIC-DEFAULT-NEXT: Live Register Matrix67; BASIC-DEFAULT-NEXT: SI Pre-allocate WWM Registers68; BASIC-DEFAULT-NEXT: Live Stack Slot Analysis69; BASIC-DEFAULT-NEXT: Bundle Machine CFG Edges70; BASIC-DEFAULT-NEXT: Spill Code Placement Analysis71; BASIC-DEFAULT-NEXT: Lazy Machine Block Frequency Analysis72; BASIC-DEFAULT-NEXT: Machine Optimization Remark Emitter73; BASIC-DEFAULT-NEXT: Greedy Register Allocator74; BASIC-DEFAULT-NEXT: SI Lower WWM Copies75; BASIC-DEFAULT-NEXT: Virtual Register Rewriter76; BASIC-DEFAULT-NEXT: AMDGPU Reserve WWM Registers77; BASIC-DEFAULT-NEXT: Virtual Register Map78; BASIC-DEFAULT-NEXT: Live Register Matrix79; BASIC-DEFAULT-NEXT: Greedy Register Allocator80; BASIC-DEFAULT-NEXT: GCN NSA Reassign81; BASIC-DEFAULT-NEXT: AMDGPU Rewrite AGPR-Copy-MFMA82; BASIC-DEFAULT-NEXT: Virtual Register Rewriter83; BASIC-DEFAULT-NEXT: AMDGPU Mark Last Scratch Load84; BASIC-DEFAULT-NEXT: Stack Slot Coloring85 86 87 88; DEFAULT-BASIC: Greedy Register Allocator89; DEFAULT-BASIC-NEXT: Virtual Register Rewriter90; DEFAULT-BASIC-NEXT: Stack Slot Coloring91; DEFAULT-BASIC-NEXT: SI lower SGPR spill instructions92; DEFAULT-BASIC-NEXT: Virtual Register Map93; DEFAULT-BASIC-NEXT: Live Register Matrix94; DEFAULT-BASIC-NEXT: SI Pre-allocate WWM Registers95; DEFAULT-BASIC-NEXT: Live Stack Slot Analysis96; DEFAULT-BASIC-NEXT: Basic Register Allocator97; DEFAULT-BASIC-NEXT: SI Lower WWM Copies98; DEFAULT-BASIC-NEXT: Virtual Register Rewriter99; DEFAULT-BASIC-NEXT: AMDGPU Reserve WWM Registers100; DEFAULT-BASIC-NEXT: Virtual Register Map101; DEFAULT-BASIC-NEXT: Live Register Matrix102; DEFAULT-BASIC-NEXT: Basic Register Allocator103; DEFAULT-BASIC-NEXT: GCN NSA Reassign104; DEFAULT-BASIC-NEXT: AMDGPU Rewrite AGPR-Copy-MFMA105; DEFAULT-BASIC-NEXT: Virtual Register Rewriter106; DEFAULT-BASIC-NEXT: AMDGPU Mark Last Scratch Load107; DEFAULT-BASIC-NEXT: Stack Slot Coloring108 109 110 111; BASIC-BASIC: Debug Variable Analysis112; BASIC-BASIC-NEXT: Live Stack Slot Analysis113; BASIC-BASIC-NEXT: Machine Natural Loop Construction114; BASIC-BASIC-NEXT: Machine Block Frequency Analysis115; BASIC-BASIC-NEXT: Virtual Register Map116; BASIC-BASIC-NEXT: Live Register Matrix117; BASIC-BASIC-NEXT: Basic Register Allocator118; BASIC-BASIC-NEXT: Virtual Register Rewriter119; BASIC-BASIC-NEXT: Stack Slot Coloring120; BASIC-BASIC-NEXT: SI lower SGPR spill instructions121; BASIC-BASIC-NEXT: Virtual Register Map122; BASIC-BASIC-NEXT: Live Register Matrix123; BASIC-BASIC-NEXT: SI Pre-allocate WWM Registers124; BASIC-BASIC-NEXT: Live Stack Slot Analysis125; BASIC-BASIC-NEXT: Basic Register Allocator126; BASIC-BASIC-NEXT: SI Lower WWM Copies127; BASIC-BASIC-NEXT: Virtual Register Rewriter128; BASIC-BASIC-NEXT: AMDGPU Reserve WWM Registers129; BASIC-BASIC-NEXT: Virtual Register Map130; BASIC-BASIC-NEXT: Live Register Matrix131; BASIC-BASIC-NEXT: Basic Register Allocator132; BASIC-BASIC-NEXT: GCN NSA Reassign133; BASIC-BASIC-NEXT: AMDGPU Rewrite AGPR-Copy-MFMA134; BASIC-BASIC-NEXT: Virtual Register Rewriter135; BASIC-BASIC-NEXT: AMDGPU Mark Last Scratch Load136; BASIC-BASIC-NEXT: Stack Slot Coloring137 138 139declare void @bar()140 141; Something with some CSR SGPR spills142define void @foo() {143 call void asm sideeffect "; clobber", "~{s33}"()144 call void @bar()145 ret void146}147 148; Block live out spills with fast regalloc149define amdgpu_kernel void @control_flow(i1 %cond) {150 %s33 = call i32 asm sideeffect "; clobber", "={s33}"()151 br i1 %cond, label %bb0, label %bb1152 153bb0:154 call void asm sideeffect "; use %0", "s"(i32 %s33)155 br label %bb1156 157bb1:158 ret void159}160