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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs -run-pass=si-lower-sgpr-spills -o - %s | FileCheck %s3#4# Check for liveness errors when spilling partially defined super registers.5 6---7name: sgpr_spill_s64_undef_high328tracksRegLiveness: true9machineFunctionInfo:10 isEntryFunction: true11 hasSpilledSGPRs: true12 scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99'13 stackPtrOffsetReg: '$sgpr32'14 15stack:16 - { id: 0, type: spill-slot, size: 8, alignment: 4, stack-id: sgpr-spill }17 18body: |19 bb.0:20 liveins: $sgpr421 22 ; CHECK-LABEL: name: sgpr_spill_s64_undef_high3223 ; CHECK: liveins: $sgpr424 ; CHECK-NEXT: {{ $}}25 ; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF26 ; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr4, 0, [[DEF]], implicit-def $sgpr4_sgpr5, implicit $sgpr4_sgpr527 ; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr5, 1, [[DEF]], implicit $sgpr4_sgpr528 SI_SPILL_S64_SAVE renamable $sgpr4_sgpr5, %stack.0, implicit $exec, implicit $sgpr96_sgpr97_sgpr98_sgpr99, implicit $sgpr32 :: (store (s64) into %stack.0, align 4, addrspace 5)29 30...31 32---33name: sgpr_spill_s64_undef_low3234tracksRegLiveness: true35machineFunctionInfo:36 isEntryFunction: true37 hasSpilledSGPRs: true38 scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99'39 stackPtrOffsetReg: '$sgpr32'40 41stack:42 - { id: 0, type: spill-slot, size: 8, alignment: 4, stack-id: sgpr-spill }43 44body: |45 bb.0:46 liveins: $sgpr547 48 ; CHECK-LABEL: name: sgpr_spill_s64_undef_low3249 ; CHECK: liveins: $sgpr550 ; CHECK-NEXT: {{ $}}51 ; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF52 ; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr4, 0, [[DEF]], implicit-def $sgpr4_sgpr5, implicit $sgpr4_sgpr553 ; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr5, 1, [[DEF]], implicit $sgpr4_sgpr554 SI_SPILL_S64_SAVE renamable $sgpr4_sgpr5, %stack.0, implicit $exec, implicit $sgpr96_sgpr97_sgpr98_sgpr99, implicit $sgpr32 :: (store (s64) into %stack.0, align 4, addrspace 5)55 56...57 58---59name: sgpr_spill_s32_undef60tracksRegLiveness: true61machineFunctionInfo:62 isEntryFunction: true63 hasSpilledSGPRs: true64 scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99'65 stackPtrOffsetReg: '$sgpr32'66stack:67 - { id: 0, type: spill-slot, size: 4, alignment: 4, stack-id: sgpr-spill }68body: |69 bb.0:70 ; CHECK-LABEL: name: sgpr_spill_s32_undef71 ; CHECK: body:72 ; CHECK-NEXT: bb.0:73 ; CHECK-NOT: {{.+}}74 ; CHECK: ...75 SI_SPILL_S32_SAVE undef $sgpr8, %stack.0, implicit $exec, implicit $sgpr96_sgpr97_sgpr98_sgpr99, implicit $sgpr32 :: (store (s32) into %stack.0, align 4, addrspace 5)76 77...78 79---80name: sgpr_spill_s64_undef81tracksRegLiveness: true82machineFunctionInfo:83 isEntryFunction: true84 hasSpilledSGPRs: true85 scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99'86 stackPtrOffsetReg: '$sgpr32'87stack:88 - { id: 0, type: spill-slot, size: 8, alignment: 4, stack-id: sgpr-spill }89body: |90 bb.0:91 ; CHECK-LABEL: name: sgpr_spill_s64_undef92 ; CHECK: body:93 ; CHECK-NEXT: bb.0:94 ; CHECK-NOT: {{.+}}95 ; CHECK: ...96 SI_SPILL_S64_SAVE undef $sgpr8_sgpr9, %stack.0, implicit $exec, implicit $sgpr96_sgpr97_sgpr98_sgpr99, implicit $sgpr32 :: (store (s64) into %stack.0, align 4, addrspace 5)97 98...99