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1; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx600 <%s | FileCheck -enable-var-scope -check-prefixes=GCN,SICI,SI %s2; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx700 <%s | FileCheck -enable-var-scope -check-prefixes=GCN,SICI,CI %s3 4; Check that an addrspace(1) (const) load with various combinations of5; uniform, nonuniform and constant address components all load with an6; addr64 mubuf with no readfirstlane.7 8@indexable = internal unnamed_addr addrspace(1) constant [6 x <3 x float>] [<3 x float> <float 1.000000e+00, float 0.000000e+00, float 0.000000e+00>, <3 x float> <float 0.000000e+00, float 1.000000e+00, float 0.000000e+00>, <3 x float> <float 0.000000e+00, float 0.000000e+00, float 1.000000e+00>, <3 x float> <float 0.000000e+00, float 1.000000e+00, float 1.000000e+00>, <3 x float> <float 1.000000e+00, float 0.000000e+00, float 1.000000e+00>, <3 x float> <float 1.000000e+00, float 1.000000e+00, float 0.000000e+00>]9 10; GCN-LABEL: {{^}}nonuniform_uniform:11; GCN-NOT: readfirstlane12; SI: buffer_load_dwordx4 {{.*}} addr6413; CI: buffer_load_dwordx3 {{.*}} addr6414 15define amdgpu_ps float @nonuniform_uniform(i32 %arg18) {16.entry:17 %tmp31 = sext i32 %arg18 to i6418 %tmp32 = getelementptr [6 x <3 x float>], ptr addrspace(1) @indexable, i64 0, i64 %tmp3119 %tmp33 = load <3 x float>, ptr addrspace(1) %tmp32, align 1620 %tmp34 = extractelement <3 x float> %tmp33, i32 021 ret float %tmp3422}23 24; GCN-LABEL: {{^}}uniform_nonuniform:25; GCN-NOT: readfirstlane26; SI: buffer_load_dwordx4 {{.*}} addr6427; CI: buffer_load_dwordx3 {{.*}} addr6428 29define amdgpu_ps float @uniform_nonuniform(i32 inreg %offset, i32 %arg18) {30.entry:31 %tmp1 = zext i32 %arg18 to i6432 %tmp2 = inttoptr i64 %tmp1 to ptr addrspace(1)33 %tmp32 = getelementptr [6 x <3 x float>], ptr addrspace(1) %tmp2, i32 0, i32 %offset34 %tmp33 = load <3 x float>, ptr addrspace(1) %tmp32, align 1635 %tmp34 = extractelement <3 x float> %tmp33, i32 036 ret float %tmp3437}38 39; GCN-LABEL: {{^}}const_nonuniform:40; GCN-NOT: readfirstlane41; SI: buffer_load_dwordx4 {{.*}} addr6442; CI: buffer_load_dwordx3 {{.*}} addr6443 44define amdgpu_ps float @const_nonuniform(i32 %arg18) {45.entry:46 %tmp1 = zext i32 %arg18 to i6447 %tmp2 = inttoptr i64 %tmp1 to ptr addrspace(1)48 %tmp32 = getelementptr [6 x <3 x float>], ptr addrspace(1) %tmp2, i32 0, i32 149 %tmp33 = load <3 x float>, ptr addrspace(1) %tmp32, align 1650 %tmp34 = extractelement <3 x float> %tmp33, i32 051 ret float %tmp3452}53 54; GCN-LABEL: {{^}}nonuniform_nonuniform:55; GCN-NOT: readfirstlane56; SI: buffer_load_dwordx4 {{.*}} addr6457; CI: buffer_load_dwordx3 {{.*}} addr6458 59define amdgpu_ps float @nonuniform_nonuniform(i32 %offset, i32 %arg18) {60.entry:61 %tmp1 = zext i32 %arg18 to i6462 %tmp2 = inttoptr i64 %tmp1 to ptr addrspace(1)63 %tmp32 = getelementptr [6 x <3 x float>], ptr addrspace(1) %tmp2, i32 0, i32 %offset64 %tmp33 = load <3 x float>, ptr addrspace(1) %tmp32, align 1665 %tmp34 = extractelement <3 x float> %tmp33, i32 066 ret float %tmp3467}68 69; GCN-LABEL: {{^}}nonuniform_uniform_const:70; GCN-NOT: readfirstlane71; SICI: buffer_load_dword {{.*}} addr6472 73define amdgpu_ps float @nonuniform_uniform_const(i32 %arg18) {74.entry:75 %tmp31 = sext i32 %arg18 to i6476 %tmp32 = getelementptr [6 x <3 x float>], ptr addrspace(1) @indexable, i64 0, i64 %tmp31, i64 177 %tmp33 = load float, ptr addrspace(1) %tmp32, align 478 ret float %tmp3379}80 81; GCN-LABEL: {{^}}uniform_nonuniform_const:82; GCN-NOT: readfirstlane83; SICI: buffer_load_dword {{.*}} addr6484 85define amdgpu_ps float @uniform_nonuniform_const(i32 inreg %offset, i32 %arg18) {86.entry:87 %tmp1 = zext i32 %arg18 to i6488 %tmp2 = inttoptr i64 %tmp1 to ptr addrspace(1)89 %tmp32 = getelementptr [6 x <3 x float>], ptr addrspace(1) %tmp2, i32 0, i32 %offset, i32 190 %tmp33 = load float, ptr addrspace(1) %tmp32, align 491 ret float %tmp3392}93 94; GCN-LABEL: {{^}}nonuniform_nonuniform_const:95; GCN-NOT: readfirstlane96; SICI: buffer_load_dword {{.*}} addr6497 98define amdgpu_ps float @nonuniform_nonuniform_const(i32 %offset, i32 %arg18) {99.entry:100 %tmp1 = zext i32 %arg18 to i64101 %tmp2 = inttoptr i64 %tmp1 to ptr addrspace(1)102 %tmp32 = getelementptr [6 x <3 x float>], ptr addrspace(1) %tmp2, i32 0, i32 %offset, i32 1103 %tmp33 = load float, ptr addrspace(1) %tmp32, align 4104 ret float %tmp33105}106 107 108 109 110