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1; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=GCN %s2; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=bonaire < %s | FileCheck -check-prefix=GCN %s3 4 5; lshr (i64 x), c: c > 32 => reg_sequence lshr (i32 hi_32(x)), (c - 32), 06; GCN-LABEL: {{^}}lshr_i64_35:7; GCN-DAG: buffer_load_dword [[VAL:v[0-9]+]]8; GCN-DAG: v_lshrrev_b32_e32 v[[LO:[0-9]+]], 3, [[VAL]]9; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}}10; GCN: buffer_store_dwordx2 v[[[LO]]:[[HI]]]11define amdgpu_kernel void @lshr_i64_35(ptr addrspace(1) %out, ptr addrspace(1) %in) {12 %val = load i64, ptr addrspace(1) %in13 %shl = lshr i64 %val, 3514 store i64 %shl, ptr addrspace(1) %out15 ret void16}17 18; GCN-LABEL: {{^}}lshr_i64_63:19; GCN-DAG: buffer_load_dword [[VAL:v[0-9]+]]20; GCN-DAG: v_lshrrev_b32_e32 v[[LO:[0-9]+]], 31, [[VAL]]21; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}}22; GCN: buffer_store_dwordx2 v[[[LO]]:[[HI]]]23define amdgpu_kernel void @lshr_i64_63(ptr addrspace(1) %out, ptr addrspace(1) %in) {24 %val = load i64, ptr addrspace(1) %in25 %shl = lshr i64 %val, 6326 store i64 %shl, ptr addrspace(1) %out27 ret void28}29 30; GCN-LABEL: {{^}}lshr_i64_33:31; GCN-DAG: buffer_load_dword [[VAL:v[0-9]+]]32; GCN-DAG: v_lshrrev_b32_e32 v[[LO:[0-9]+]], 1, [[VAL]]33; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}}34; GCN: buffer_store_dwordx2 v[[[LO]]:[[HI]]]35define amdgpu_kernel void @lshr_i64_33(ptr addrspace(1) %out, ptr addrspace(1) %in) {36 %val = load i64, ptr addrspace(1) %in37 %shl = lshr i64 %val, 3338 store i64 %shl, ptr addrspace(1) %out39 ret void40}41 42; GCN-LABEL: {{^}}lshr_i64_32:43; GCN-DAG: buffer_load_dword v[[LO:[0-9]+]]44; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}}45; GCN: buffer_store_dwordx2 v[[[LO]]:[[HI]]]46define amdgpu_kernel void @lshr_i64_32(ptr addrspace(1) %out, ptr addrspace(1) %in) {47 %val = load i64, ptr addrspace(1) %in48 %shl = lshr i64 %val, 3249 store i64 %shl, ptr addrspace(1) %out50 ret void51}52 53; Make sure the and of the constant doesn't prevent bfe from forming54; after 64-bit shift is split.55 56; GCN-LABEL: {{^}}lshr_and_i64_35:57; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}}58; GCN-DAG: buffer_load_dword v[[LO:[0-9]+]]59; GCN: v_bfe_u32 v[[BFE:[0-9]+]], v[[LO]], 8, 2360; GCN: buffer_store_dwordx2 v[[[BFE]]:[[ZERO]]]61define amdgpu_kernel void @lshr_and_i64_35(ptr addrspace(1) %out, ptr addrspace(1) %in) {62 %val = load i64, ptr addrspace(1) %in63 %and = and i64 %val, 9223372036854775807 ; 0x7fffffffffffffff64 %shl = lshr i64 %and, 4065 store i64 %shl, ptr addrspace(1) %out66 ret void67}68 69; lshl (i64 x), c: c > 32 => reg_sequence lshl 0, (i32 lo_32(x)), (c - 32)70 71; GCN-LABEL: {{^}}shl_i64_const_35:72; GCN: buffer_load_dword [[VAL:v[0-9]+]]73; GCN: v_lshlrev_b32_e32 v[[HI:[0-9]+]], 3, [[VAL]]74; GCN: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}}75; GCN: buffer_store_dwordx2 v[[[LO]]:[[HI]]]76define amdgpu_kernel void @shl_i64_const_35(ptr addrspace(1) %out, ptr addrspace(1) %in) {77 %val = load i64, ptr addrspace(1) %in78 %shl = shl i64 %val, 3579 store i64 %shl, ptr addrspace(1) %out80 ret void81}82 83; GCN-LABEL: {{^}}shl_i64_const_32:84; GCN-DAG: buffer_load_dword v[[HI:[0-9]+]]85; GCN-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}}86; GCN: buffer_store_dwordx2 v[[[LO]]:[[HI]]]87define amdgpu_kernel void @shl_i64_const_32(ptr addrspace(1) %out, ptr addrspace(1) %in) {88 %val = load i64, ptr addrspace(1) %in89 %shl = shl i64 %val, 3290 store i64 %shl, ptr addrspace(1) %out91 ret void92}93 94; GCN-LABEL: {{^}}shl_i64_const_63:95; GCN: buffer_load_dword [[VAL:v[0-9]+]]96; GCN: v_lshlrev_b32_e32 v[[HI:[0-9]+]], 31, [[VAL]]97; GCN: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}}98; GCN: buffer_store_dwordx2 v[[[LO]]:[[HI]]]99define amdgpu_kernel void @shl_i64_const_63(ptr addrspace(1) %out, ptr addrspace(1) %in) {100 %val = load i64, ptr addrspace(1) %in101 %shl = shl i64 %val, 63102 store i64 %shl, ptr addrspace(1) %out103 ret void104}105 106; ashr (i64 x), 63 => (ashr lo(x), 31), lo(x)107 108; GCN-LABEL: {{^}}ashr_i64_const_32:109define amdgpu_kernel void @ashr_i64_const_32(ptr addrspace(1) %out, ptr addrspace(1) %in) {110 %val = load i64, ptr addrspace(1) %in111 %shl = ashr i64 %val, 32112 store i64 %shl, ptr addrspace(1) %out113 ret void114}115 116; GCN-LABEL: {{^}}ashr_i64_const_63:117define amdgpu_kernel void @ashr_i64_const_63(ptr addrspace(1) %out, ptr addrspace(1) %in) {118 %val = load i64, ptr addrspace(1) %in119 %shl = ashr i64 %val, 63120 store i64 %shl, ptr addrspace(1) %out121 ret void122}123 124; GCN-LABEL: {{^}}trunc_shl_31_i32_i64:125; GCN: buffer_load_dword [[VAL:v[0-9]+]]126; GCN: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 31, [[VAL]]127; GCN: buffer_store_dword [[SHL]]128define amdgpu_kernel void @trunc_shl_31_i32_i64(ptr addrspace(1) %out, ptr addrspace(1) %in) {129 %val = load i64, ptr addrspace(1) %in130 %shl = shl i64 %val, 31131 %trunc = trunc i64 %shl to i32132 store i32 %trunc, ptr addrspace(1) %out133 ret void134}135 136; GCN-LABEL: {{^}}trunc_shl_15_i16_i64:137; GCN: buffer_load_dword [[VAL:v[0-9]+]]138; GCN: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 15, [[VAL]]139; GCN: buffer_store_short [[SHL]]140define amdgpu_kernel void @trunc_shl_15_i16_i64(ptr addrspace(1) %out, ptr addrspace(1) %in) {141 %val = load i64, ptr addrspace(1) %in142 %shl = shl i64 %val, 15143 %trunc = trunc i64 %shl to i16144 store i16 %trunc, ptr addrspace(1) %out145 ret void146}147 148; GCN-LABEL: {{^}}trunc_shl_15_i16_i32:149; GCN: buffer_load_dword [[VAL:v[0-9]+]]150; GCN: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 15, [[VAL]]151; GCN: buffer_store_short [[SHL]]152define amdgpu_kernel void @trunc_shl_15_i16_i32(ptr addrspace(1) %out, ptr addrspace(1) %in) {153 %val = load i32, ptr addrspace(1) %in154 %shl = shl i32 %val, 15155 %trunc = trunc i32 %shl to i16156 store i16 %trunc, ptr addrspace(1) %out157 ret void158}159 160; GCN-LABEL: {{^}}trunc_shl_7_i8_i64:161; GCN: buffer_load_dword [[VAL:v[0-9]+]]162; GCN: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 7, [[VAL]]163; GCN: buffer_store_byte [[SHL]]164define amdgpu_kernel void @trunc_shl_7_i8_i64(ptr addrspace(1) %out, ptr addrspace(1) %in) {165 %val = load i64, ptr addrspace(1) %in166 %shl = shl i64 %val, 7167 %trunc = trunc i64 %shl to i8168 store i8 %trunc, ptr addrspace(1) %out169 ret void170}171 172; GCN-LABEL: {{^}}trunc_shl_1_i2_i64:173; GCN: buffer_load_dword [[VAL:v[0-9]+]]174; GCN: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 1, [[VAL]]175; GCN: v_and_b32_e32 [[AND:v[0-9]+]], 2, [[SHL]]176; GCN: buffer_store_byte [[AND]]177define amdgpu_kernel void @trunc_shl_1_i2_i64(ptr addrspace(1) %out, ptr addrspace(1) %in) {178 %val = load i64, ptr addrspace(1) %in179 %shl = shl i64 %val, 1180 %trunc = trunc i64 %shl to i2181 store i2 %trunc, ptr addrspace(1) %out182 ret void183}184 185; GCN-LABEL: {{^}}trunc_shl_1_i32_i64:186; GCN: buffer_load_dword [[VAL:v[0-9]+]]187; GCN: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 1, [[VAL]]188; GCN: buffer_store_dword [[SHL]]189define amdgpu_kernel void @trunc_shl_1_i32_i64(ptr addrspace(1) %out, ptr addrspace(1) %in) {190 %val = load i64, ptr addrspace(1) %in191 %shl = shl i64 %val, 1192 %trunc = trunc i64 %shl to i32193 store i32 %trunc, ptr addrspace(1) %out194 ret void195}196 197; GCN-LABEL: {{^}}trunc_shl_16_i32_i64:198; GCN: buffer_load_dword [[VAL:v[0-9]+]]199; GCN: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 16, [[VAL]]200; GCN: buffer_store_dword [[SHL]]201define amdgpu_kernel void @trunc_shl_16_i32_i64(ptr addrspace(1) %out, ptr addrspace(1) %in) {202 %val = load i64, ptr addrspace(1) %in203 %shl = shl i64 %val, 16204 %trunc = trunc i64 %shl to i32205 store i32 %trunc, ptr addrspace(1) %out206 ret void207}208 209; GCN-LABEL: {{^}}trunc_shl_33_i32_i64:210; GCN: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0{{$}}211; GCN: buffer_store_dword [[ZERO]]212define amdgpu_kernel void @trunc_shl_33_i32_i64(ptr addrspace(1) %out, ptr addrspace(1) %in) {213 %val = load i64, ptr addrspace(1) %in214 %shl = shl i64 %val, 33215 %trunc = trunc i64 %shl to i32216 store i32 %trunc, ptr addrspace(1) %out217 ret void218}219 220; GCN-LABEL: {{^}}trunc_shl_16_v2i32_v2i64:221; GCN: buffer_load_dwordx4 v[[[LO:[0-9]+]]:[[HI:[0-9]+]]]222; GCN-DAG: v_lshlrev_b32_e32 v[[RESHI:[0-9]+]], 16, v{{[0-9]+}}223; GCN-DAG: v_lshlrev_b32_e32 v[[RESLO:[0-9]+]], 16, v[[LO]]224; GCN: buffer_store_dwordx2 v[[[RESLO]]:[[RESHI]]]225define amdgpu_kernel void @trunc_shl_16_v2i32_v2i64(ptr addrspace(1) %out, ptr addrspace(1) %in) {226 %val = load <2 x i64>, ptr addrspace(1) %in227 %shl = shl <2 x i64> %val, <i64 16, i64 16>228 %trunc = trunc <2 x i64> %shl to <2 x i32>229 store <2 x i32> %trunc, ptr addrspace(1) %out230 ret void231}232 233; GCN-LABEL: {{^}}trunc_shl_31_i32_i64_multi_use:234; GCN: buffer_load_dwordx2 [[VAL:v\[[0-9]+:[0-9]+\]]]235; GCN: v_lshl_b64 v[[[RESLO:[0-9]+]]:[[RESHI:[0-9]+]]], [[VAL]], 31236; GCN: buffer_store_dword v[[RESLO]]237; GCN: buffer_store_dwordx2 v[[[RESLO]]:[[RESHI]]]238define amdgpu_kernel void @trunc_shl_31_i32_i64_multi_use(ptr addrspace(1) %out, ptr addrspace(1) %in) {239 %val = load i64, ptr addrspace(1) %in240 %shl = shl i64 %val, 31241 %trunc = trunc i64 %shl to i32242 store volatile i32 %trunc, ptr addrspace(1) %out243 store volatile i64 %shl, ptr addrspace(1) %in244 ret void245}246 247; GCN-LABEL: {{^}}trunc_shl_and31:248; GCN: v_lshlrev_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}249; GCN-NOT: v_lshl_b64250; GCN-NOT: v_lshlrev_b64251define amdgpu_kernel void @trunc_shl_and31(ptr addrspace(1) nocapture readonly %arg, ptr addrspace(1) nocapture %arg1, i32 %arg2) {252bb:253 %tmp = load i64, ptr addrspace(1) %arg, align 8254 %tmp3 = and i32 %arg2, 31255 %tmp4 = zext i32 %tmp3 to i64256 %tmp5 = shl i64 %tmp, %tmp4257 %tmp6 = trunc i64 %tmp5 to i32258 store i32 %tmp6, ptr addrspace(1) %arg1, align 4259 ret void260}261 262; GCN-LABEL: {{^}}trunc_shl_and30:263; GCN: s_and_b32 s[[AMT:[0-9]+]], s{{[0-9]+}}, 30264; GCN: v_lshlrev_b32_e32 v{{[0-9]+}}, s[[AMT]], v{{[0-9]+}}265; GCN-NOT: v_lshl_b64266; GCN-NOT: v_lshlrev_b64267define amdgpu_kernel void @trunc_shl_and30(ptr addrspace(1) nocapture readonly %arg, ptr addrspace(1) nocapture %arg1, i32 %arg2) {268bb:269 %tmp = load i64, ptr addrspace(1) %arg, align 8270 %tmp3 = and i32 %arg2, 30271 %tmp4 = zext i32 %tmp3 to i64272 %tmp5 = shl i64 %tmp, %tmp4273 %tmp6 = trunc i64 %tmp5 to i32274 store i32 %tmp6, ptr addrspace(1) %arg1, align 4275 ret void276}277 278; GCN-LABEL: {{^}}trunc_shl_wrong_and63:279; Negative test, wrong constant280; GCN: v_lshl_b64281define amdgpu_kernel void @trunc_shl_wrong_and63(ptr addrspace(1) nocapture readonly %arg, ptr addrspace(1) nocapture %arg1, i32 %arg2) {282bb:283 %tmp = load i64, ptr addrspace(1) %arg, align 8284 %tmp3 = and i32 %arg2, 63285 %tmp4 = zext i32 %tmp3 to i64286 %tmp5 = shl i64 %tmp, %tmp4287 %tmp6 = trunc i64 %tmp5 to i32288 store i32 %tmp6, ptr addrspace(1) %arg1, align 4289 ret void290}291 292; GCN-LABEL: {{^}}trunc_shl_no_and:293; Negative test, shift can be full 64 bit294; GCN: v_lshl_b64295define amdgpu_kernel void @trunc_shl_no_and(ptr addrspace(1) nocapture readonly %arg, ptr addrspace(1) nocapture %arg1, i32 %arg2) {296bb:297 %tmp = load i64, ptr addrspace(1) %arg, align 8298 %tmp4 = zext i32 %arg2 to i64299 %tmp5 = shl i64 %tmp, %tmp4300 %tmp6 = trunc i64 %tmp5 to i32301 store i32 %tmp6, ptr addrspace(1) %arg1, align 4302 ret void303}304 305; GCN-LABEL: {{^}}trunc_shl_vec_vec:306; GCN-DAG: v_lshl_b64 v[{{[0-9:]+}}], v[{{[0-9:]+}}], 3307; GCN-DAG: v_lshl_b64 v[{{[0-9:]+}}], v[{{[0-9:]+}}], 4308; GCN-DAG: v_lshl_b64 v[{{[0-9:]+}}], v[{{[0-9:]+}}], 5309; GCN-DAG: v_lshl_b64 v[{{[0-9:]+}}], v[{{[0-9:]+}}], 6310define amdgpu_kernel void @trunc_shl_vec_vec(ptr addrspace(1) %arg) {311bb:312 %v = load <4 x i64>, ptr addrspace(1) %arg, align 32313 %shl = shl <4 x i64> %v, <i64 3, i64 4, i64 5, i64 6>314 store <4 x i64> %shl, ptr addrspace(1) %arg, align 32315 ret void316}317