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1; RUN: llc -mtriple=amdgcn -mcpu=fiji < %s | FileCheck %s2 3; Check transformation shl (or|add x, c2), c1 => or|add (shl x, c1), (c2 << c1)4; Only one shift if expected, GEP shall not produce a separate shift5 6; CHECK-LABEL: {{^}}add_const_offset:7; CHECK: v_lshlrev_b32_e32 v[[SHL:[0-9]+]], 4, v08; CHECK: v_add_u32_e32 v[[ADD:[0-9]+]], vcc, 0xc80, v[[SHL]]9; CHECK-NOT: v_lshl10; CHECK: v_add_u32_e32 v[[ADDRLO:[0-9]+]], vcc, s{{[0-9]+}}, v[[ADD]]11; CHECK: load_dword v{{[0-9]+}}, v[[[ADDRLO]]:12define amdgpu_kernel void @add_const_offset(ptr addrspace(1) nocapture %arg) {13bb:14 %id = tail call i32 @llvm.amdgcn.workitem.id.x()15 %add = add i32 %id, 20016 %shl = shl i32 %add, 217 %ptr = getelementptr inbounds i32, ptr addrspace(1) %arg, i32 %shl18 %val = load i32, ptr addrspace(1) %ptr, align 419 store i32 %val, ptr addrspace(1) %arg, align 420 ret void21}22 23; CHECK-LABEL: {{^}}or_const_offset:24; CHECK: v_lshlrev_b32_e32 v[[SHL:[0-9]+]], 4, v025; CHECK: v_or_b32_e32 v[[OR:[0-9]+]], 0x1000, v[[SHL]]26; CHECK-NOT: v_lshl27; CHECK: v_add_u32_e32 v[[ADDRLO:[0-9]+]], vcc, s{{[0-9]+}}, v[[OR]]28; CHECK: load_dword v{{[0-9]+}}, v[[[ADDRLO]]:29define amdgpu_kernel void @or_const_offset(ptr addrspace(1) nocapture %arg) {30bb:31 %id = tail call i32 @llvm.amdgcn.workitem.id.x()32 %add = or i32 %id, 25633 %shl = shl i32 %add, 234 %ptr = getelementptr inbounds i32, ptr addrspace(1) %arg, i32 %shl35 %val = load i32, ptr addrspace(1) %ptr, align 436 store i32 %val, ptr addrspace(1) %arg, align 437 ret void38}39 40declare i32 @llvm.amdgcn.workitem.id.x()41