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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-- -mcpu=verde | FileCheck %s --check-prefixes=SI3; RUN: llc < %s -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global | FileCheck %s -check-prefixes=VI4; RUN: llc < %s -amdgpu-scalarize-global-loads=false -mtriple=r600-- -mcpu=redwood | FileCheck %s --check-prefixes=EG5 6declare i32 @llvm.amdgcn.workitem.id.x() #07 8declare i32 @llvm.amdgcn.workgroup.id.x() #09 10define amdgpu_kernel void @shl_v2i32(ptr addrspace(1) %out, ptr addrspace(1) %in) {11; SI-LABEL: shl_v2i32:12; SI: ; %bb.0:13; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x914; SI-NEXT: s_mov_b32 s7, 0xf00015; SI-NEXT: s_mov_b32 s6, -116; SI-NEXT: s_mov_b32 s10, s617; SI-NEXT: s_mov_b32 s11, s718; SI-NEXT: s_waitcnt lgkmcnt(0)19; SI-NEXT: s_mov_b32 s8, s220; SI-NEXT: s_mov_b32 s9, s321; SI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 022; SI-NEXT: s_mov_b32 s4, s023; SI-NEXT: s_mov_b32 s5, s124; SI-NEXT: s_waitcnt vmcnt(0)25; SI-NEXT: v_lshl_b32_e32 v1, v1, v326; SI-NEXT: v_lshl_b32_e32 v0, v0, v227; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 028; SI-NEXT: s_endpgm29;30; VI-LABEL: shl_v2i32:31; VI: ; %bb.0:32; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2433; VI-NEXT: s_waitcnt lgkmcnt(0)34; VI-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x035; VI-NEXT: s_mov_b32 s3, 0xf00036; VI-NEXT: s_mov_b32 s2, -137; VI-NEXT: s_waitcnt lgkmcnt(0)38; VI-NEXT: s_lshl_b32 s5, s5, s739; VI-NEXT: s_lshl_b32 s4, s4, s640; VI-NEXT: v_mov_b32_e32 v0, s441; VI-NEXT: v_mov_b32_e32 v1, s542; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 043; VI-NEXT: s_endpgm44;45; EG-LABEL: shl_v2i32:46; EG: ; %bb.0:47; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]48; EG-NEXT: TEX 0 @649; EG-NEXT: ALU 3, @9, KC0[CB0:0-32], KC1[]50; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 151; EG-NEXT: CF_END52; EG-NEXT: PAD53; EG-NEXT: Fetch clause starting at 6:54; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #155; EG-NEXT: ALU clause starting at 8:56; EG-NEXT: MOV * T0.X, KC0[2].Z,57; EG-NEXT: ALU clause starting at 9:58; EG-NEXT: LSHL * T0.Y, T0.Y, T0.W,59; EG-NEXT: LSHL T0.X, T0.X, T0.Z,60; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,61; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)62 %b_ptr = getelementptr <2 x i32>, ptr addrspace(1) %in, i32 163 %a = load <2 x i32>, ptr addrspace(1) %in64 %b = load <2 x i32>, ptr addrspace(1) %b_ptr65 %result = shl <2 x i32> %a, %b66 store <2 x i32> %result, ptr addrspace(1) %out67 ret void68}69 70define amdgpu_kernel void @shl_v4i32(ptr addrspace(1) %out, ptr addrspace(1) %in) {71; SI-LABEL: shl_v4i32:72; SI: ; %bb.0:73; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x974; SI-NEXT: s_mov_b32 s7, 0xf00075; SI-NEXT: s_mov_b32 s6, -176; SI-NEXT: s_mov_b32 s10, s677; SI-NEXT: s_mov_b32 s11, s778; SI-NEXT: s_waitcnt lgkmcnt(0)79; SI-NEXT: s_mov_b32 s8, s280; SI-NEXT: s_mov_b32 s9, s381; SI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 082; SI-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:1683; SI-NEXT: s_mov_b32 s4, s084; SI-NEXT: s_mov_b32 s5, s185; SI-NEXT: s_waitcnt vmcnt(0)86; SI-NEXT: v_lshl_b32_e32 v3, v3, v787; SI-NEXT: v_lshl_b32_e32 v2, v2, v688; SI-NEXT: v_lshl_b32_e32 v1, v1, v589; SI-NEXT: v_lshl_b32_e32 v0, v0, v490; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 091; SI-NEXT: s_endpgm92;93; VI-LABEL: shl_v4i32:94; VI: ; %bb.0:95; VI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x2496; VI-NEXT: s_waitcnt lgkmcnt(0)97; VI-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x098; VI-NEXT: s_mov_b32 s11, 0xf00099; VI-NEXT: s_mov_b32 s10, -1100; VI-NEXT: s_waitcnt lgkmcnt(0)101; VI-NEXT: s_lshl_b32 s3, s3, s7102; VI-NEXT: s_lshl_b32 s2, s2, s6103; VI-NEXT: s_lshl_b32 s1, s1, s5104; VI-NEXT: s_lshl_b32 s0, s0, s4105; VI-NEXT: v_mov_b32_e32 v0, s0106; VI-NEXT: v_mov_b32_e32 v1, s1107; VI-NEXT: v_mov_b32_e32 v2, s2108; VI-NEXT: v_mov_b32_e32 v3, s3109; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0110; VI-NEXT: s_endpgm111;112; EG-LABEL: shl_v4i32:113; EG: ; %bb.0:114; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[]115; EG-NEXT: TEX 1 @6116; EG-NEXT: ALU 5, @11, KC0[CB0:0-32], KC1[]117; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1118; EG-NEXT: CF_END119; EG-NEXT: PAD120; EG-NEXT: Fetch clause starting at 6:121; EG-NEXT: VTX_READ_128 T1.XYZW, T0.X, 16, #1122; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1123; EG-NEXT: ALU clause starting at 10:124; EG-NEXT: MOV * T0.X, KC0[2].Z,125; EG-NEXT: ALU clause starting at 11:126; EG-NEXT: LSHL * T0.W, T0.W, T1.W,127; EG-NEXT: LSHL * T0.Z, T0.Z, T1.Z,128; EG-NEXT: LSHL * T0.Y, T0.Y, T1.Y,129; EG-NEXT: LSHL T0.X, T0.X, T1.X,130; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,131; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)132 %b_ptr = getelementptr <4 x i32>, ptr addrspace(1) %in, i32 1133 %a = load <4 x i32>, ptr addrspace(1) %in134 %b = load <4 x i32>, ptr addrspace(1) %b_ptr135 %result = shl <4 x i32> %a, %b136 store <4 x i32> %result, ptr addrspace(1) %out137 ret void138}139 140define amdgpu_kernel void @shl_i16(ptr addrspace(1) %out, ptr addrspace(1) %in) {141; SI-LABEL: shl_i16:142; SI: ; %bb.0:143; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9144; SI-NEXT: s_mov_b32 s7, 0xf000145; SI-NEXT: s_mov_b32 s6, -1146; SI-NEXT: s_mov_b32 s10, s6147; SI-NEXT: s_mov_b32 s11, s7148; SI-NEXT: s_waitcnt lgkmcnt(0)149; SI-NEXT: s_mov_b32 s8, s2150; SI-NEXT: s_mov_b32 s9, s3151; SI-NEXT: buffer_load_ushort v0, off, s[8:11], 0152; SI-NEXT: buffer_load_ushort v1, off, s[8:11], 0 offset:2153; SI-NEXT: s_mov_b32 s4, s0154; SI-NEXT: s_mov_b32 s5, s1155; SI-NEXT: s_waitcnt vmcnt(0)156; SI-NEXT: v_lshl_b32_e32 v0, v0, v1157; SI-NEXT: buffer_store_short v0, off, s[4:7], 0158; SI-NEXT: s_endpgm159;160; VI-LABEL: shl_i16:161; VI: ; %bb.0:162; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24163; VI-NEXT: s_mov_b32 s7, 0xf000164; VI-NEXT: s_mov_b32 s6, -1165; VI-NEXT: s_mov_b32 s10, s6166; VI-NEXT: s_mov_b32 s11, s7167; VI-NEXT: s_waitcnt lgkmcnt(0)168; VI-NEXT: s_mov_b32 s8, s2169; VI-NEXT: s_mov_b32 s9, s3170; VI-NEXT: buffer_load_ushort v0, off, s[8:11], 0171; VI-NEXT: buffer_load_ushort v1, off, s[8:11], 0 offset:2172; VI-NEXT: s_mov_b32 s4, s0173; VI-NEXT: s_mov_b32 s5, s1174; VI-NEXT: s_waitcnt vmcnt(0)175; VI-NEXT: v_lshlrev_b32_e32 v0, v1, v0176; VI-NEXT: buffer_store_short v0, off, s[4:7], 0177; VI-NEXT: s_endpgm178;179; EG-LABEL: shl_i16:180; EG: ; %bb.0:181; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[]182; EG-NEXT: TEX 1 @6183; EG-NEXT: ALU 12, @11, KC0[CB0:0-32], KC1[]184; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X185; EG-NEXT: CF_END186; EG-NEXT: PAD187; EG-NEXT: Fetch clause starting at 6:188; EG-NEXT: VTX_READ_16 T1.X, T0.X, 2, #1189; EG-NEXT: VTX_READ_16 T0.X, T0.X, 0, #1190; EG-NEXT: ALU clause starting at 10:191; EG-NEXT: MOV * T0.X, KC0[2].Z,192; EG-NEXT: ALU clause starting at 11:193; EG-NEXT: AND_INT T0.W, KC0[2].Y, literal.x,194; EG-NEXT: LSHL * T1.W, T0.X, T1.X,195; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)196; EG-NEXT: AND_INT T1.W, PS, literal.x,197; EG-NEXT: LSHL * T0.W, PV.W, literal.y,198; EG-NEXT: 65535(9.183409e-41), 3(4.203895e-45)199; EG-NEXT: LSHL T0.X, PV.W, PS,200; EG-NEXT: LSHL * T0.W, literal.x, PS,201; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)202; EG-NEXT: MOV T0.Y, 0.0,203; EG-NEXT: MOV * T0.Z, 0.0,204; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,205; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)206 %b_ptr = getelementptr i16, ptr addrspace(1) %in, i16 1207 %a = load i16, ptr addrspace(1) %in208 %b = load i16, ptr addrspace(1) %b_ptr209 %result = shl i16 %a, %b210 store i16 %result, ptr addrspace(1) %out211 ret void212}213 214define amdgpu_kernel void @shl_i16_v_s(ptr addrspace(1) %out, ptr addrspace(1) %in, i16 %b) {215; SI-LABEL: shl_i16_v_s:216; SI: ; %bb.0:217; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9218; SI-NEXT: s_load_dword s12, s[4:5], 0xd219; SI-NEXT: s_mov_b32 s7, 0xf000220; SI-NEXT: s_mov_b32 s6, -1221; SI-NEXT: s_mov_b32 s10, s6222; SI-NEXT: s_waitcnt lgkmcnt(0)223; SI-NEXT: s_mov_b32 s8, s2224; SI-NEXT: s_mov_b32 s9, s3225; SI-NEXT: s_mov_b32 s11, s7226; SI-NEXT: buffer_load_ushort v0, off, s[8:11], 0227; SI-NEXT: s_mov_b32 s4, s0228; SI-NEXT: s_mov_b32 s5, s1229; SI-NEXT: s_waitcnt vmcnt(0)230; SI-NEXT: v_lshlrev_b32_e32 v0, s12, v0231; SI-NEXT: buffer_store_short v0, off, s[4:7], 0232; SI-NEXT: s_endpgm233;234; VI-LABEL: shl_i16_v_s:235; VI: ; %bb.0:236; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24237; VI-NEXT: s_load_dword s12, s[4:5], 0x34238; VI-NEXT: s_mov_b32 s7, 0xf000239; VI-NEXT: s_mov_b32 s6, -1240; VI-NEXT: s_mov_b32 s10, s6241; VI-NEXT: s_waitcnt lgkmcnt(0)242; VI-NEXT: s_mov_b32 s8, s2243; VI-NEXT: s_mov_b32 s9, s3244; VI-NEXT: s_mov_b32 s11, s7245; VI-NEXT: buffer_load_ushort v0, off, s[8:11], 0246; VI-NEXT: s_mov_b32 s4, s0247; VI-NEXT: s_mov_b32 s5, s1248; VI-NEXT: s_waitcnt vmcnt(0)249; VI-NEXT: v_lshlrev_b32_e32 v0, s12, v0250; VI-NEXT: buffer_store_short v0, off, s[4:7], 0251; VI-NEXT: s_endpgm252;253; EG-LABEL: shl_i16_v_s:254; EG: ; %bb.0:255; EG-NEXT: ALU 1, @10, KC0[CB0:0-32], KC1[]256; EG-NEXT: TEX 1 @6257; EG-NEXT: ALU 12, @12, KC0[CB0:0-32], KC1[]258; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X259; EG-NEXT: CF_END260; EG-NEXT: PAD261; EG-NEXT: Fetch clause starting at 6:262; EG-NEXT: VTX_READ_16 T1.X, T1.X, 0, #1263; EG-NEXT: VTX_READ_16 T0.X, T0.X, 44, #3264; EG-NEXT: ALU clause starting at 10:265; EG-NEXT: MOV T0.X, 0.0,266; EG-NEXT: MOV * T1.X, KC0[2].Z,267; EG-NEXT: ALU clause starting at 12:268; EG-NEXT: AND_INT T0.W, KC0[2].Y, literal.x,269; EG-NEXT: LSHL * T1.W, T1.X, T0.X,270; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)271; EG-NEXT: AND_INT T1.W, PS, literal.x,272; EG-NEXT: LSHL * T0.W, PV.W, literal.y,273; EG-NEXT: 65535(9.183409e-41), 3(4.203895e-45)274; EG-NEXT: LSHL T0.X, PV.W, PS,275; EG-NEXT: LSHL * T0.W, literal.x, PS,276; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)277; EG-NEXT: MOV T0.Y, 0.0,278; EG-NEXT: MOV * T0.Z, 0.0,279; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,280; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)281 %a = load i16, ptr addrspace(1) %in282 %result = shl i16 %a, %b283 store i16 %result, ptr addrspace(1) %out284 ret void285}286 287define amdgpu_kernel void @shl_i16_v_compute_s(ptr addrspace(1) %out, ptr addrspace(1) %in, i16 %b) {288; SI-LABEL: shl_i16_v_compute_s:289; SI: ; %bb.0:290; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9291; SI-NEXT: s_load_dword s12, s[4:5], 0xd292; SI-NEXT: s_mov_b32 s7, 0xf000293; SI-NEXT: s_mov_b32 s6, -1294; SI-NEXT: s_mov_b32 s10, s6295; SI-NEXT: s_waitcnt lgkmcnt(0)296; SI-NEXT: s_mov_b32 s8, s2297; SI-NEXT: s_mov_b32 s9, s3298; SI-NEXT: s_mov_b32 s11, s7299; SI-NEXT: buffer_load_ushort v0, off, s[8:11], 0300; SI-NEXT: s_add_i32 s12, s12, 3301; SI-NEXT: s_mov_b32 s4, s0302; SI-NEXT: s_mov_b32 s5, s1303; SI-NEXT: s_waitcnt vmcnt(0)304; SI-NEXT: v_lshlrev_b32_e32 v0, s12, v0305; SI-NEXT: buffer_store_short v0, off, s[4:7], 0306; SI-NEXT: s_endpgm307;308; VI-LABEL: shl_i16_v_compute_s:309; VI: ; %bb.0:310; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24311; VI-NEXT: s_load_dword s12, s[4:5], 0x34312; VI-NEXT: s_mov_b32 s7, 0xf000313; VI-NEXT: s_mov_b32 s6, -1314; VI-NEXT: s_mov_b32 s10, s6315; VI-NEXT: s_waitcnt lgkmcnt(0)316; VI-NEXT: s_mov_b32 s8, s2317; VI-NEXT: s_mov_b32 s9, s3318; VI-NEXT: s_mov_b32 s11, s7319; VI-NEXT: buffer_load_ushort v0, off, s[8:11], 0320; VI-NEXT: s_add_i32 s12, s12, 3321; VI-NEXT: s_mov_b32 s4, s0322; VI-NEXT: s_mov_b32 s5, s1323; VI-NEXT: s_waitcnt vmcnt(0)324; VI-NEXT: v_lshlrev_b32_e32 v0, s12, v0325; VI-NEXT: buffer_store_short v0, off, s[4:7], 0326; VI-NEXT: s_endpgm327;328; EG-LABEL: shl_i16_v_compute_s:329; EG: ; %bb.0:330; EG-NEXT: ALU 0, @12, KC0[], KC1[]331; EG-NEXT: TEX 0 @8332; EG-NEXT: ALU 0, @13, KC0[CB0:0-32], KC1[]333; EG-NEXT: TEX 0 @10334; EG-NEXT: ALU 15, @14, KC0[CB0:0-32], KC1[]335; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X336; EG-NEXT: CF_END337; EG-NEXT: PAD338; EG-NEXT: Fetch clause starting at 8:339; EG-NEXT: VTX_READ_16 T0.X, T0.X, 44, #3340; EG-NEXT: Fetch clause starting at 10:341; EG-NEXT: VTX_READ_16 T1.X, T1.X, 0, #1342; EG-NEXT: ALU clause starting at 12:343; EG-NEXT: MOV * T0.X, 0.0,344; EG-NEXT: ALU clause starting at 13:345; EG-NEXT: MOV * T1.X, KC0[2].Z,346; EG-NEXT: ALU clause starting at 14:347; EG-NEXT: ADD_INT * T0.W, T0.X, literal.x,348; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)349; EG-NEXT: AND_INT T0.W, PV.W, literal.x,350; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.y,351; EG-NEXT: 65535(9.183409e-41), 3(4.203895e-45)352; EG-NEXT: LSHL * T0.W, T1.X, PV.W,353; EG-NEXT: AND_INT T0.W, PV.W, literal.x,354; EG-NEXT: LSHL * T1.W, T1.W, literal.y,355; EG-NEXT: 65535(9.183409e-41), 3(4.203895e-45)356; EG-NEXT: LSHL T0.X, PV.W, PS,357; EG-NEXT: LSHL * T0.W, literal.x, PS,358; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)359; EG-NEXT: MOV T0.Y, 0.0,360; EG-NEXT: MOV * T0.Z, 0.0,361; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,362; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)363 %a = load i16, ptr addrspace(1) %in364 %b.add = add i16 %b, 3365 %result = shl i16 %a, %b.add366 store i16 %result, ptr addrspace(1) %out367 ret void368}369 370define amdgpu_kernel void @shl_i16_computed_amount(ptr addrspace(1) %out, ptr addrspace(1) %in) {371; SI-LABEL: shl_i16_computed_amount:372; SI: ; %bb.0:373; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9374; SI-NEXT: s_mov_b32 s7, 0xf000375; SI-NEXT: s_mov_b32 s6, -1376; SI-NEXT: s_mov_b32 s10, s6377; SI-NEXT: s_mov_b32 s11, s7378; SI-NEXT: s_waitcnt lgkmcnt(0)379; SI-NEXT: s_mov_b32 s8, s2380; SI-NEXT: s_mov_b32 s9, s3381; SI-NEXT: v_lshlrev_b32_e32 v0, 1, v0382; SI-NEXT: v_mov_b32_e32 v1, 0383; SI-NEXT: s_mov_b32 s14, 0384; SI-NEXT: s_mov_b32 s15, s7385; SI-NEXT: s_mov_b64 s[12:13], s[2:3]386; SI-NEXT: buffer_load_ushort v2, off, s[8:11], 0 glc387; SI-NEXT: s_waitcnt vmcnt(0)388; SI-NEXT: buffer_load_ushort v0, v[0:1], s[12:15], 0 addr64 offset:2 glc389; SI-NEXT: s_waitcnt vmcnt(0)390; SI-NEXT: s_mov_b32 s4, s0391; SI-NEXT: s_mov_b32 s5, s1392; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0393; SI-NEXT: v_lshlrev_b32_e32 v0, v0, v2394; SI-NEXT: buffer_store_short v0, off, s[4:7], 0395; SI-NEXT: s_endpgm396;397; VI-LABEL: shl_i16_computed_amount:398; VI: ; %bb.0:399; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24400; VI-NEXT: v_lshlrev_b32_e32 v0, 1, v0401; VI-NEXT: s_mov_b32 s7, 0xf000402; VI-NEXT: s_mov_b32 s6, -1403; VI-NEXT: s_mov_b32 s10, s6404; VI-NEXT: s_waitcnt lgkmcnt(0)405; VI-NEXT: v_mov_b32_e32 v1, s3406; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0407; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc408; VI-NEXT: v_add_u32_e32 v0, vcc, 2, v0409; VI-NEXT: s_mov_b32 s8, s2410; VI-NEXT: s_mov_b32 s9, s3411; VI-NEXT: s_mov_b32 s11, s7412; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc413; VI-NEXT: buffer_load_ushort v2, off, s[8:11], 0 glc414; VI-NEXT: s_waitcnt vmcnt(0)415; VI-NEXT: flat_load_ushort v0, v[0:1] glc416; VI-NEXT: s_waitcnt vmcnt(0)417; VI-NEXT: s_mov_b32 s4, s0418; VI-NEXT: s_mov_b32 s5, s1419; VI-NEXT: v_add_u16_e32 v0, 3, v0420; VI-NEXT: v_lshlrev_b16_e32 v0, v0, v2421; VI-NEXT: buffer_store_short v0, off, s[4:7], 0422; VI-NEXT: s_endpgm423;424; EG-LABEL: shl_i16_computed_amount:425; EG: ; %bb.0:426; EG-NEXT: ALU 0, @12, KC0[CB0:0-32], KC1[]427; EG-NEXT: TEX 0 @8428; EG-NEXT: ALU 1, @13, KC0[CB0:0-32], KC1[]429; EG-NEXT: TEX 0 @10430; EG-NEXT: ALU 15, @15, KC0[CB0:0-32], KC1[]431; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X432; EG-NEXT: CF_END433; EG-NEXT: PAD434; EG-NEXT: Fetch clause starting at 8:435; EG-NEXT: VTX_READ_16 T1.X, T1.X, 0, #1436; EG-NEXT: Fetch clause starting at 10:437; EG-NEXT: VTX_READ_16 T0.X, T0.X, 2, #1438; EG-NEXT: ALU clause starting at 12:439; EG-NEXT: MOV * T1.X, KC0[2].Z,440; EG-NEXT: ALU clause starting at 13:441; EG-NEXT: LSHL * T0.W, T0.X, 1,442; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,443; EG-NEXT: ALU clause starting at 15:444; EG-NEXT: ADD_INT * T0.W, T0.X, literal.x,445; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)446; EG-NEXT: AND_INT T0.W, PV.W, literal.x,447; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.y,448; EG-NEXT: 65535(9.183409e-41), 3(4.203895e-45)449; EG-NEXT: LSHL * T0.W, T1.X, PV.W,450; EG-NEXT: AND_INT T0.W, PV.W, literal.x,451; EG-NEXT: LSHL * T1.W, T1.W, literal.y,452; EG-NEXT: 65535(9.183409e-41), 3(4.203895e-45)453; EG-NEXT: LSHL T0.X, PV.W, PS,454; EG-NEXT: LSHL * T0.W, literal.x, PS,455; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)456; EG-NEXT: MOV T0.Y, 0.0,457; EG-NEXT: MOV * T0.Z, 0.0,458; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,459; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)460 %tid = call i32 @llvm.amdgcn.workitem.id.x() #0461 %gep = getelementptr inbounds i16, ptr addrspace(1) %in, i32 %tid462 %gep.out = getelementptr inbounds i16, ptr addrspace(1) %out, i32 %tid463 %b_ptr = getelementptr i16, ptr addrspace(1) %gep, i16 1464 %a = load volatile i16, ptr addrspace(1) %in465 %b = load volatile i16, ptr addrspace(1) %b_ptr466 %b.add = add i16 %b, 3467 %result = shl i16 %a, %b.add468 store i16 %result, ptr addrspace(1) %out469 ret void470}471 472define amdgpu_kernel void @shl_i16_i_s(ptr addrspace(1) %out, i16 zeroext %a) {473; SI-LABEL: shl_i16_i_s:474; SI: ; %bb.0:475; SI-NEXT: s_load_dword s6, s[4:5], 0xb476; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9477; SI-NEXT: s_mov_b32 s3, 0xf000478; SI-NEXT: s_mov_b32 s2, -1479; SI-NEXT: s_waitcnt lgkmcnt(0)480; SI-NEXT: s_lshl_b32 s4, s6, 12481; SI-NEXT: v_mov_b32_e32 v0, s4482; SI-NEXT: buffer_store_short v0, off, s[0:3], 0483; SI-NEXT: s_endpgm484;485; VI-LABEL: shl_i16_i_s:486; VI: ; %bb.0:487; VI-NEXT: s_load_dword s6, s[4:5], 0x2c488; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24489; VI-NEXT: s_mov_b32 s3, 0xf000490; VI-NEXT: s_mov_b32 s2, -1491; VI-NEXT: s_waitcnt lgkmcnt(0)492; VI-NEXT: s_lshl_b32 s4, s6, 12493; VI-NEXT: v_mov_b32_e32 v0, s4494; VI-NEXT: buffer_store_short v0, off, s[0:3], 0495; VI-NEXT: s_endpgm496;497; EG-LABEL: shl_i16_i_s:498; EG: ; %bb.0:499; EG-NEXT: ALU 0, @8, KC0[], KC1[]500; EG-NEXT: TEX 0 @6501; EG-NEXT: ALU 14, @9, KC0[CB0:0-32], KC1[]502; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X503; EG-NEXT: CF_END504; EG-NEXT: PAD505; EG-NEXT: Fetch clause starting at 6:506; EG-NEXT: VTX_READ_16 T0.X, T0.X, 40, #3507; EG-NEXT: ALU clause starting at 8:508; EG-NEXT: MOV * T0.X, 0.0,509; EG-NEXT: ALU clause starting at 9:510; EG-NEXT: BFE_INT T0.W, T0.X, 0.0, literal.x,511; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.y,512; EG-NEXT: 16(2.242078e-44), 3(4.203895e-45)513; EG-NEXT: LSHL * T0.W, PV.W, literal.x,514; EG-NEXT: 12(1.681558e-44), 0(0.000000e+00)515; EG-NEXT: AND_INT T0.W, PV.W, literal.x,516; EG-NEXT: LSHL * T1.W, T1.W, literal.y,517; EG-NEXT: 61440(8.609578e-41), 3(4.203895e-45)518; EG-NEXT: LSHL T0.X, PV.W, PS,519; EG-NEXT: LSHL * T0.W, literal.x, PS,520; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)521; EG-NEXT: MOV T0.Y, 0.0,522; EG-NEXT: MOV * T0.Z, 0.0,523; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,524; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)525 %result = shl i16 %a, 12526 store i16 %result, ptr addrspace(1) %out527 ret void528}529 530define amdgpu_kernel void @shl_v2i16(ptr addrspace(1) %out, ptr addrspace(1) %in) {531; SI-LABEL: shl_v2i16:532; SI: ; %bb.0:533; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9534; SI-NEXT: s_mov_b32 s7, 0xf000535; SI-NEXT: s_mov_b32 s6, -1536; SI-NEXT: s_mov_b32 s10, s6537; SI-NEXT: s_mov_b32 s11, s7538; SI-NEXT: s_waitcnt lgkmcnt(0)539; SI-NEXT: s_mov_b32 s8, s2540; SI-NEXT: s_mov_b32 s9, s3541; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0542; SI-NEXT: v_mov_b32_e32 v1, 0543; SI-NEXT: s_mov_b32 s14, 0544; SI-NEXT: s_mov_b32 s15, s7545; SI-NEXT: s_mov_b64 s[12:13], s[2:3]546; SI-NEXT: buffer_load_dword v2, off, s[8:11], 0547; SI-NEXT: buffer_load_dword v0, v[0:1], s[12:15], 0 addr64 offset:4548; SI-NEXT: s_mov_b32 s4, s0549; SI-NEXT: s_mov_b32 s5, s1550; SI-NEXT: s_waitcnt vmcnt(1)551; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v2552; SI-NEXT: s_waitcnt vmcnt(0)553; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v0554; SI-NEXT: v_lshlrev_b32_e32 v0, v0, v2555; SI-NEXT: v_lshlrev_b32_e32 v1, v3, v1556; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0557; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1558; SI-NEXT: v_or_b32_e32 v0, v0, v1559; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0560; SI-NEXT: s_endpgm561;562; VI-LABEL: shl_v2i16:563; VI: ; %bb.0:564; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24565; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0566; VI-NEXT: s_waitcnt lgkmcnt(0)567; VI-NEXT: v_mov_b32_e32 v1, s3568; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0569; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc570; VI-NEXT: v_add_u32_e32 v0, vcc, 4, v0571; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc572; VI-NEXT: flat_load_dword v0, v[0:1]573; VI-NEXT: s_load_dword s4, s[2:3], 0x0574; VI-NEXT: s_mov_b32 s3, 0xf000575; VI-NEXT: s_mov_b32 s2, -1576; VI-NEXT: s_waitcnt lgkmcnt(0)577; VI-NEXT: s_lshr_b32 s5, s4, 16578; VI-NEXT: v_mov_b32_e32 v1, s5579; VI-NEXT: s_waitcnt vmcnt(0)580; VI-NEXT: v_lshlrev_b16_e64 v2, v0, s4581; VI-NEXT: v_lshlrev_b16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD582; VI-NEXT: v_or_b32_e32 v0, v2, v0583; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0584; VI-NEXT: s_endpgm585;586; EG-LABEL: shl_v2i16:587; EG: ; %bb.0:588; EG-NEXT: ALU 2, @12, KC0[CB0:0-32], KC1[]589; EG-NEXT: TEX 0 @8590; EG-NEXT: ALU 0, @15, KC0[CB0:0-32], KC1[]591; EG-NEXT: TEX 0 @10592; EG-NEXT: ALU 11, @16, KC0[CB0:0-32], KC1[]593; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T7.X, 1594; EG-NEXT: CF_END595; EG-NEXT: PAD596; EG-NEXT: Fetch clause starting at 8:597; EG-NEXT: VTX_READ_32 T0.X, T0.X, 4, #1598; EG-NEXT: Fetch clause starting at 10:599; EG-NEXT: VTX_READ_32 T7.X, T7.X, 0, #1600; EG-NEXT: ALU clause starting at 12:601; EG-NEXT: LSHL * T0.W, T0.X, literal.x,602; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)603; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,604; EG-NEXT: ALU clause starting at 15:605; EG-NEXT: MOV * T7.X, KC0[2].Z,606; EG-NEXT: ALU clause starting at 16:607; EG-NEXT: AND_INT T0.Z, T0.X, literal.x,608; EG-NEXT: LSHR T0.W, T0.X, literal.y,609; EG-NEXT: LSHR * T1.W, T7.X, literal.y,610; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44)611; EG-NEXT: LSHL T0.W, PS, PV.W,612; EG-NEXT: LSHL * T1.W, T7.X, PV.Z,613; EG-NEXT: AND_INT T1.W, PS, literal.x,614; EG-NEXT: LSHL * T0.W, PV.W, literal.y,615; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44)616; EG-NEXT: OR_INT T0.X, PV.W, PS,617; EG-NEXT: LSHR * T7.X, KC0[2].Y, literal.x,618; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)619 %tid = call i32 @llvm.amdgcn.workitem.id.x() #0620 %gep = getelementptr inbounds <2 x i16>, ptr addrspace(1) %in, i32 %tid621 %gep.out = getelementptr inbounds <2 x i16>, ptr addrspace(1) %out, i32 %tid622 %b_ptr = getelementptr <2 x i16>, ptr addrspace(1) %gep, i16 1623 %a = load <2 x i16>, ptr addrspace(1) %in624 %b = load <2 x i16>, ptr addrspace(1) %b_ptr625 %result = shl <2 x i16> %a, %b626 store <2 x i16> %result, ptr addrspace(1) %out627 ret void628}629 630define amdgpu_kernel void @shl_v4i16(ptr addrspace(1) %out, ptr addrspace(1) %in) {631; SI-LABEL: shl_v4i16:632; SI: ; %bb.0:633; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9634; SI-NEXT: s_mov_b32 s7, 0xf000635; SI-NEXT: s_mov_b32 s6, 0636; SI-NEXT: v_lshlrev_b32_e32 v4, 3, v0637; SI-NEXT: v_mov_b32_e32 v5, 0638; SI-NEXT: s_waitcnt lgkmcnt(0)639; SI-NEXT: s_mov_b64 s[4:5], s[2:3]640; SI-NEXT: buffer_load_dwordx4 v[0:3], v[4:5], s[4:7], 0 addr64641; SI-NEXT: s_mov_b64 s[2:3], s[6:7]642; SI-NEXT: s_waitcnt vmcnt(0)643; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v0644; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v1645; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v2646; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v3647; SI-NEXT: v_lshlrev_b32_e32 v1, v3, v1648; SI-NEXT: v_lshlrev_b32_e32 v0, v2, v0649; SI-NEXT: v_lshlrev_b32_e32 v2, v9, v7650; SI-NEXT: v_lshlrev_b32_e32 v3, v8, v6651; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1652; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0653; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2654; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3655; SI-NEXT: v_or_b32_e32 v1, v1, v2656; SI-NEXT: v_or_b32_e32 v0, v0, v3657; SI-NEXT: buffer_store_dwordx2 v[0:1], v[4:5], s[0:3], 0 addr64658; SI-NEXT: s_endpgm659;660; VI-LABEL: shl_v4i16:661; VI: ; %bb.0:662; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24663; VI-NEXT: v_lshlrev_b32_e32 v4, 3, v0664; VI-NEXT: s_waitcnt lgkmcnt(0)665; VI-NEXT: v_mov_b32_e32 v1, s3666; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v4667; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc668; VI-NEXT: flat_load_dwordx4 v[0:3], v[0:1]669; VI-NEXT: v_mov_b32_e32 v5, s1670; VI-NEXT: v_add_u32_e32 v4, vcc, s0, v4671; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc672; VI-NEXT: s_waitcnt vmcnt(0)673; VI-NEXT: v_lshlrev_b16_e32 v6, v3, v1674; VI-NEXT: v_lshlrev_b16_sdwa v1, v3, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1675; VI-NEXT: v_lshlrev_b16_e32 v3, v2, v0676; VI-NEXT: v_lshlrev_b16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1677; VI-NEXT: v_or_b32_e32 v1, v6, v1678; VI-NEXT: v_or_b32_e32 v0, v3, v0679; VI-NEXT: flat_store_dwordx2 v[4:5], v[0:1]680; VI-NEXT: s_endpgm681;682; EG-LABEL: shl_v4i16:683; EG: ; %bb.0:684; EG-NEXT: ALU 3, @8, KC0[CB0:0-32], KC1[]685; EG-NEXT: TEX 0 @6686; EG-NEXT: ALU 42, @12, KC0[CB0:0-32], KC1[]687; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T10.XY, T0.X, 1688; EG-NEXT: CF_END689; EG-NEXT: PAD690; EG-NEXT: Fetch clause starting at 6:691; EG-NEXT: VTX_READ_128 T10.XYZW, T0.X, 0, #1692; EG-NEXT: ALU clause starting at 8:693; EG-NEXT: MOV T0.Y, T6.X,694; EG-NEXT: LSHL * T0.W, T0.X, literal.x, BS:VEC_120/SCL_212695; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)696; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,697; EG-NEXT: ALU clause starting at 12:698; EG-NEXT: AND_INT * T1.W, T10.Z, literal.x,699; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)700; EG-NEXT: LSHL * T1.W, T10.X, PV.W,701; EG-NEXT: AND_INT T1.W, PV.W, literal.x,702; EG-NEXT: AND_INT * T2.W, T0.Y, literal.y,703; EG-NEXT: 65535(9.183409e-41), -65536(nan)704; EG-NEXT: OR_INT * T1.W, PS, PV.W,705; EG-NEXT: MOV * T6.X, PV.W,706; EG-NEXT: MOV T0.X, PV.X,707; EG-NEXT: LSHR T1.W, T10.Z, literal.x,708; EG-NEXT: LSHR * T2.W, T10.X, literal.x,709; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)710; EG-NEXT: LSHL T1.W, PS, PV.W,711; EG-NEXT: AND_INT * T2.W, PV.X, literal.x,712; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)713; EG-NEXT: LSHL * T1.W, PV.W, literal.x,714; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)715; EG-NEXT: OR_INT * T1.W, T2.W, PV.W,716; EG-NEXT: MOV T6.X, PV.W,717; EG-NEXT: MOV * T0.X, T7.X,718; EG-NEXT: AND_INT * T1.W, T10.W, literal.x,719; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)720; EG-NEXT: LSHL T1.W, T10.Y, PV.W,721; EG-NEXT: AND_INT * T2.W, T0.X, literal.x,722; EG-NEXT: -65536(nan), 0(0.000000e+00)723; EG-NEXT: AND_INT * T1.W, PV.W, literal.x,724; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)725; EG-NEXT: OR_INT * T1.W, T2.W, PV.W,726; EG-NEXT: MOV * T7.X, PV.W,727; EG-NEXT: MOV T0.X, PV.X,728; EG-NEXT: LSHR T1.W, T10.W, literal.x,729; EG-NEXT: LSHR * T2.W, T10.Y, literal.x,730; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)731; EG-NEXT: LSHL * T1.W, PS, PV.W,732; EG-NEXT: AND_INT T0.Z, T0.X, literal.x,733; EG-NEXT: LSHL T1.W, PV.W, literal.y,734; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, T0.W,735; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44)736; EG-NEXT: LSHR T0.X, PS, literal.x,737; EG-NEXT: OR_INT * T10.Y, PV.Z, PV.W,738; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)739; EG-NEXT: MOV T7.X, PV.Y,740; EG-NEXT: MOV * T10.X, T6.X,741 %tid = call i32 @llvm.amdgcn.workitem.id.x() #0742 %gep = getelementptr inbounds <4 x i16>, ptr addrspace(1) %in, i32 %tid743 %gep.out = getelementptr inbounds <4 x i16>, ptr addrspace(1) %out, i32 %tid744 %b_ptr = getelementptr <4 x i16>, ptr addrspace(1) %gep, i16 1745 %a = load <4 x i16>, ptr addrspace(1) %gep746 %b = load <4 x i16>, ptr addrspace(1) %b_ptr747 %result = shl <4 x i16> %a, %b748 store <4 x i16> %result, ptr addrspace(1) %gep.out749 ret void750}751 752define amdgpu_kernel void @shl_i64(ptr addrspace(1) %out, ptr addrspace(1) %in) {753; SI-LABEL: shl_i64:754; SI: ; %bb.0:755; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9756; SI-NEXT: s_mov_b32 s7, 0xf000757; SI-NEXT: s_mov_b32 s6, -1758; SI-NEXT: s_mov_b32 s10, s6759; SI-NEXT: s_mov_b32 s11, s7760; SI-NEXT: s_waitcnt lgkmcnt(0)761; SI-NEXT: s_mov_b32 s8, s2762; SI-NEXT: s_mov_b32 s9, s3763; SI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0764; SI-NEXT: s_mov_b32 s4, s0765; SI-NEXT: s_mov_b32 s5, s1766; SI-NEXT: s_waitcnt vmcnt(0)767; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], v2768; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0769; SI-NEXT: s_endpgm770;771; VI-LABEL: shl_i64:772; VI: ; %bb.0:773; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24774; VI-NEXT: s_waitcnt lgkmcnt(0)775; VI-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0776; VI-NEXT: s_mov_b32 s3, 0xf000777; VI-NEXT: s_mov_b32 s2, -1778; VI-NEXT: s_waitcnt lgkmcnt(0)779; VI-NEXT: s_lshl_b64 s[4:5], s[4:5], s6780; VI-NEXT: v_mov_b32_e32 v0, s4781; VI-NEXT: v_mov_b32_e32 v1, s5782; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0783; VI-NEXT: s_endpgm784;785; EG-LABEL: shl_i64:786; EG: ; %bb.0:787; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]788; EG-NEXT: TEX 0 @6789; EG-NEXT: ALU 12, @9, KC0[CB0:0-32], KC1[]790; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1791; EG-NEXT: CF_END792; EG-NEXT: PAD793; EG-NEXT: Fetch clause starting at 6:794; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1795; EG-NEXT: ALU clause starting at 8:796; EG-NEXT: MOV * T0.X, KC0[2].Z,797; EG-NEXT: ALU clause starting at 9:798; EG-NEXT: LSHR T1.Y, T0.Y, 1,799; EG-NEXT: NOT_INT T1.Z, T0.Z,800; EG-NEXT: BIT_ALIGN_INT T0.W, T0.Y, T0.X, 1,801; EG-NEXT: AND_INT * T1.W, T0.Z, literal.x,802; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)803; EG-NEXT: LSHL T2.Z, T0.X, PS,804; EG-NEXT: BIT_ALIGN_INT T0.W, PV.Y, PV.W, PV.Z,805; EG-NEXT: AND_INT * T1.W, T0.Z, literal.x,806; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)807; EG-NEXT: CNDE_INT * T0.Y, PS, PV.W, PV.Z,808; EG-NEXT: CNDE_INT T0.X, T1.W, T2.Z, 0.0,809; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,810; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)811 %b_ptr = getelementptr i64, ptr addrspace(1) %in, i64 1812 %a = load i64, ptr addrspace(1) %in813 %b = load i64, ptr addrspace(1) %b_ptr814 %result = shl i64 %a, %b815 store i64 %result, ptr addrspace(1) %out816 ret void817}818 819define amdgpu_kernel void @shl_v2i64(ptr addrspace(1) %out, ptr addrspace(1) %in) {820; SI-LABEL: shl_v2i64:821; SI: ; %bb.0:822; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9823; SI-NEXT: s_mov_b32 s7, 0xf000824; SI-NEXT: s_mov_b32 s6, -1825; SI-NEXT: s_mov_b32 s10, s6826; SI-NEXT: s_mov_b32 s11, s7827; SI-NEXT: s_waitcnt lgkmcnt(0)828; SI-NEXT: s_mov_b32 s8, s2829; SI-NEXT: s_mov_b32 s9, s3830; SI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0831; SI-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:16832; SI-NEXT: s_mov_b32 s4, s0833; SI-NEXT: s_mov_b32 s5, s1834; SI-NEXT: s_waitcnt vmcnt(0)835; SI-NEXT: v_lshl_b64 v[2:3], v[2:3], v6836; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], v4837; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0838; SI-NEXT: s_endpgm839;840; VI-LABEL: shl_v2i64:841; VI: ; %bb.0:842; VI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x24843; VI-NEXT: s_waitcnt lgkmcnt(0)844; VI-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0845; VI-NEXT: s_mov_b32 s11, 0xf000846; VI-NEXT: s_mov_b32 s10, -1847; VI-NEXT: s_waitcnt lgkmcnt(0)848; VI-NEXT: s_lshl_b64 s[2:3], s[2:3], s6849; VI-NEXT: s_lshl_b64 s[0:1], s[0:1], s4850; VI-NEXT: v_mov_b32_e32 v0, s0851; VI-NEXT: v_mov_b32_e32 v1, s1852; VI-NEXT: v_mov_b32_e32 v2, s2853; VI-NEXT: v_mov_b32_e32 v3, s3854; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0855; VI-NEXT: s_endpgm856;857; EG-LABEL: shl_v2i64:858; EG: ; %bb.0:859; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[]860; EG-NEXT: TEX 1 @6861; EG-NEXT: ALU 23, @11, KC0[CB0:0-32], KC1[]862; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T2.XYZW, T0.X, 1863; EG-NEXT: CF_END864; EG-NEXT: PAD865; EG-NEXT: Fetch clause starting at 6:866; EG-NEXT: VTX_READ_128 T1.XYZW, T0.X, 16, #1867; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1868; EG-NEXT: ALU clause starting at 10:869; EG-NEXT: MOV * T0.X, KC0[2].Z,870; EG-NEXT: ALU clause starting at 11:871; EG-NEXT: AND_INT * T1.W, T1.Z, literal.x,872; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)873; EG-NEXT: LSHL T2.X, T0.Z, PV.W,874; EG-NEXT: AND_INT T1.Y, T1.Z, literal.x, BS:VEC_120/SCL_212875; EG-NEXT: LSHR T2.Z, T0.W, 1,876; EG-NEXT: BIT_ALIGN_INT T0.W, T0.W, T0.Z, 1, BS:VEC_102/SCL_221877; EG-NEXT: NOT_INT * T1.W, T1.Z,878; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)879; EG-NEXT: BIT_ALIGN_INT T3.X, PV.Z, PV.W, PS,880; EG-NEXT: LSHR T2.Y, T0.Y, 1,881; EG-NEXT: NOT_INT T0.Z, T1.X,882; EG-NEXT: BIT_ALIGN_INT T0.W, T0.Y, T0.X, 1,883; EG-NEXT: AND_INT * T1.W, T1.X, literal.x,884; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)885; EG-NEXT: LSHL T0.Y, T0.X, PS, BS:VEC_120/SCL_212886; EG-NEXT: AND_INT T1.Z, T1.X, literal.x, BS:VEC_201887; EG-NEXT: BIT_ALIGN_INT T0.W, PV.Y, PV.W, PV.Z,888; EG-NEXT: CNDE_INT * T2.W, T1.Y, PV.X, T2.X,889; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)890; EG-NEXT: CNDE_INT T2.Y, PV.Z, PV.W, PV.Y,891; EG-NEXT: CNDE_INT * T2.Z, T1.Y, T2.X, 0.0,892; EG-NEXT: CNDE_INT T2.X, T1.Z, T0.Y, 0.0,893; EG-NEXT: LSHR * T0.X, KC0[2].Y, literal.x,894; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)895 %b_ptr = getelementptr <2 x i64>, ptr addrspace(1) %in, i64 1896 %a = load <2 x i64>, ptr addrspace(1) %in897 %b = load <2 x i64>, ptr addrspace(1) %b_ptr898 %result = shl <2 x i64> %a, %b899 store <2 x i64> %result, ptr addrspace(1) %out900 ret void901}902 903define amdgpu_kernel void @shl_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %in) {904; SI-LABEL: shl_v4i64:905; SI: ; %bb.0:906; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9907; SI-NEXT: s_mov_b32 s7, 0xf000908; SI-NEXT: s_mov_b32 s6, -1909; SI-NEXT: s_mov_b32 s10, s6910; SI-NEXT: s_mov_b32 s11, s7911; SI-NEXT: s_waitcnt lgkmcnt(0)912; SI-NEXT: s_mov_b32 s8, s2913; SI-NEXT: s_mov_b32 s9, s3914; SI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0 offset:48915; SI-NEXT: buffer_load_dwordx4 v[3:6], off, s[8:11], 0 offset:16916; SI-NEXT: buffer_load_dwordx4 v[7:10], off, s[8:11], 0917; SI-NEXT: buffer_load_dwordx4 v[11:14], off, s[8:11], 0 offset:32918; SI-NEXT: s_mov_b32 s4, s0919; SI-NEXT: s_mov_b32 s5, s1920; SI-NEXT: s_waitcnt vmcnt(2)921; SI-NEXT: v_lshl_b64 v[5:6], v[5:6], v2922; SI-NEXT: v_lshl_b64 v[3:4], v[3:4], v0923; SI-NEXT: s_waitcnt vmcnt(0)924; SI-NEXT: v_lshl_b64 v[9:10], v[9:10], v13925; SI-NEXT: v_lshl_b64 v[7:8], v[7:8], v11926; SI-NEXT: buffer_store_dwordx4 v[3:6], off, s[4:7], 0 offset:16927; SI-NEXT: buffer_store_dwordx4 v[7:10], off, s[4:7], 0928; SI-NEXT: s_endpgm929;930; VI-LABEL: shl_v4i64:931; VI: ; %bb.0:932; VI-NEXT: s_load_dwordx4 s[16:19], s[4:5], 0x24933; VI-NEXT: s_waitcnt lgkmcnt(0)934; VI-NEXT: s_load_dwordx16 s[0:15], s[18:19], 0x0935; VI-NEXT: s_mov_b32 s19, 0xf000936; VI-NEXT: s_mov_b32 s18, -1937; VI-NEXT: s_waitcnt lgkmcnt(0)938; VI-NEXT: s_lshl_b64 s[6:7], s[6:7], s14939; VI-NEXT: s_lshl_b64 s[4:5], s[4:5], s12940; VI-NEXT: s_lshl_b64 s[2:3], s[2:3], s10941; VI-NEXT: s_lshl_b64 s[0:1], s[0:1], s8942; VI-NEXT: v_mov_b32_e32 v0, s4943; VI-NEXT: v_mov_b32_e32 v1, s5944; VI-NEXT: v_mov_b32_e32 v2, s6945; VI-NEXT: v_mov_b32_e32 v3, s7946; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:16947; VI-NEXT: s_nop 0948; VI-NEXT: v_mov_b32_e32 v0, s0949; VI-NEXT: v_mov_b32_e32 v1, s1950; VI-NEXT: v_mov_b32_e32 v2, s2951; VI-NEXT: v_mov_b32_e32 v3, s3952; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0953; VI-NEXT: s_endpgm954;955; EG-LABEL: shl_v4i64:956; EG: ; %bb.0:957; EG-NEXT: ALU 0, @14, KC0[CB0:0-32], KC1[]958; EG-NEXT: TEX 3 @6959; EG-NEXT: ALU 48, @15, KC0[CB0:0-32], KC1[]960; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T2.XYZW, T0.X, 0961; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T3.XYZW, T1.X, 1962; EG-NEXT: CF_END963; EG-NEXT: Fetch clause starting at 6:964; EG-NEXT: VTX_READ_128 T1.XYZW, T0.X, 32, #1965; EG-NEXT: VTX_READ_128 T2.XYZW, T0.X, 48, #1966; EG-NEXT: VTX_READ_128 T3.XYZW, T0.X, 16, #1967; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1968; EG-NEXT: ALU clause starting at 14:969; EG-NEXT: MOV * T0.X, KC0[2].Z,970; EG-NEXT: ALU clause starting at 15:971; EG-NEXT: AND_INT * T1.W, T1.Z, literal.x,972; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)973; EG-NEXT: LSHL * T1.W, T0.Z, PV.W,974; EG-NEXT: AND_INT T4.X, T1.Z, literal.x,975; EG-NEXT: LSHR T1.Y, T3.W, 1,976; EG-NEXT: NOT_INT T4.Z, T2.Z, BS:VEC_201977; EG-NEXT: BIT_ALIGN_INT T2.W, T3.W, T3.Z, 1,978; EG-NEXT: AND_INT * T3.W, T2.Z, literal.y,979; EG-NEXT: 32(4.484155e-44), 31(4.344025e-44)980; EG-NEXT: LSHL T5.X, T3.Z, PS,981; EG-NEXT: AND_INT T2.Y, T2.Z, literal.x, BS:VEC_120/SCL_212982; EG-NEXT: BIT_ALIGN_INT T2.Z, PV.Y, PV.W, PV.Z,983; EG-NEXT: LSHR T2.W, T3.Y, 1,984; EG-NEXT: NOT_INT * T3.W, T2.X,985; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)986; EG-NEXT: BIT_ALIGN_INT T6.X, T3.Y, T3.X, 1,987; EG-NEXT: AND_INT T1.Y, T2.X, literal.x,988; EG-NEXT: LSHR T3.Z, T0.W, 1,989; EG-NEXT: BIT_ALIGN_INT T0.W, T0.W, T0.Z, 1,990; EG-NEXT: NOT_INT * T4.W, T1.Z,991; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)992; EG-NEXT: BIT_ALIGN_INT T7.X, PV.Z, PV.W, PS,993; EG-NEXT: LSHL T1.Y, T3.X, PV.Y, BS:VEC_120/SCL_212994; EG-NEXT: AND_INT T0.Z, T2.X, literal.x, BS:VEC_201995; EG-NEXT: BIT_ALIGN_INT T0.W, T2.W, PV.X, T3.W,996; EG-NEXT: CNDE_INT * T3.W, T2.Y, T2.Z, T5.X,997; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)998; EG-NEXT: LSHR T2.X, T0.Y, 1,999; EG-NEXT: CNDE_INT T3.Y, PV.Z, PV.W, PV.Y,1000; EG-NEXT: NOT_INT T1.Z, T1.X,1001; EG-NEXT: BIT_ALIGN_INT T0.W, T0.Y, T0.X, 1,1002; EG-NEXT: AND_INT * T2.W, T1.X, literal.x,1003; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)1004; EG-NEXT: LSHL T0.X, T0.X, PS,1005; EG-NEXT: AND_INT T0.Y, T1.X, literal.x, BS:VEC_120/SCL_2121006; EG-NEXT: CNDE_INT T3.Z, T2.Y, T5.X, 0.0, BS:VEC_021/SCL_1221007; EG-NEXT: BIT_ALIGN_INT * T0.W, PV.X, PV.W, PV.Z,1008; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)1009; EG-NEXT: CNDE_INT * T2.W, T4.X, T7.X, T1.W,1010; EG-NEXT: CNDE_INT T3.X, T0.Z, T1.Y, 0.0,1011; EG-NEXT: CNDE_INT T2.Y, T0.Y, T0.W, T0.X,1012; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,1013; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)1014; EG-NEXT: LSHR T1.X, PV.W, literal.x,1015; EG-NEXT: CNDE_INT T2.Z, T4.X, T1.W, 0.0,1016; EG-NEXT: CNDE_INT * T2.X, T0.Y, T0.X, 0.0,1017; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1018; EG-NEXT: LSHR * T0.X, KC0[2].Y, literal.x,1019; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1020 %b_ptr = getelementptr <4 x i64>, ptr addrspace(1) %in, i64 11021 %a = load <4 x i64>, ptr addrspace(1) %in1022 %b = load <4 x i64>, ptr addrspace(1) %b_ptr1023 %result = shl <4 x i64> %a, %b1024 store <4 x i64> %result, ptr addrspace(1) %out1025 ret void1026}1027 1028; Make sure load width gets reduced to i32 load.1029define amdgpu_kernel void @s_shl_32_i64(ptr addrspace(1) %out, [8 x i32], i64 %a) {1030; SI-LABEL: s_shl_32_i64:1031; SI: ; %bb.0:1032; SI-NEXT: s_load_dword s6, s[4:5], 0x131033; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x91034; SI-NEXT: s_mov_b32 s3, 0xf0001035; SI-NEXT: s_mov_b32 s2, -11036; SI-NEXT: v_mov_b32_e32 v0, 01037; SI-NEXT: s_waitcnt lgkmcnt(0)1038; SI-NEXT: v_mov_b32_e32 v1, s61039; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 01040; SI-NEXT: s_endpgm1041;1042; VI-LABEL: s_shl_32_i64:1043; VI: ; %bb.0:1044; VI-NEXT: s_load_dword s6, s[4:5], 0x4c1045; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x241046; VI-NEXT: s_mov_b32 s3, 0xf0001047; VI-NEXT: s_mov_b32 s2, -11048; VI-NEXT: v_mov_b32_e32 v0, 01049; VI-NEXT: s_waitcnt lgkmcnt(0)1050; VI-NEXT: v_mov_b32_e32 v1, s61051; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 01052; VI-NEXT: s_endpgm1053;1054; EG-LABEL: s_shl_32_i64:1055; EG: ; %bb.0:1056; EG-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]1057; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 11058; EG-NEXT: CF_END1059; EG-NEXT: PAD1060; EG-NEXT: ALU clause starting at 4:1061; EG-NEXT: MOV * T0.Y, KC0[4].W,1062; EG-NEXT: MOV T0.X, 0.0,1063; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1064; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1065 %result = shl i64 %a, 321066 store i64 %result, ptr addrspace(1) %out1067 ret void1068}1069 1070define amdgpu_kernel void @v_shl_32_i64(ptr addrspace(1) %out, ptr addrspace(1) %in) {1071; SI-LABEL: v_shl_32_i64:1072; SI: ; %bb.0:1073; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91074; SI-NEXT: s_ashr_i32 s9, s8, 311075; SI-NEXT: s_mov_b32 s7, 0xf0001076; SI-NEXT: s_mov_b32 s6, 01077; SI-NEXT: v_mov_b32_e32 v2, 01078; SI-NEXT: s_waitcnt lgkmcnt(0)1079; SI-NEXT: s_mov_b64 s[4:5], s[2:3]1080; SI-NEXT: s_lshl_b64 s[2:3], s[8:9], 31081; SI-NEXT: v_mov_b32_e32 v0, s21082; SI-NEXT: v_mov_b32_e32 v1, s31083; SI-NEXT: buffer_load_dword v3, v[0:1], s[4:7], 0 addr641084; SI-NEXT: s_mov_b64 s[2:3], s[6:7]1085; SI-NEXT: s_waitcnt vmcnt(0)1086; SI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr641087; SI-NEXT: s_endpgm1088;1089; VI-LABEL: v_shl_32_i64:1090; VI: ; %bb.0:1091; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241092; VI-NEXT: s_ashr_i32 s9, s8, 311093; VI-NEXT: s_lshl_b64 s[4:5], s[8:9], 31094; VI-NEXT: v_mov_b32_e32 v0, 01095; VI-NEXT: s_waitcnt lgkmcnt(0)1096; VI-NEXT: s_add_u32 s2, s2, s41097; VI-NEXT: s_addc_u32 s3, s3, s51098; VI-NEXT: s_load_dword s2, s[2:3], 0x01099; VI-NEXT: s_add_u32 s0, s0, s41100; VI-NEXT: s_addc_u32 s1, s1, s51101; VI-NEXT: v_mov_b32_e32 v3, s11102; VI-NEXT: v_mov_b32_e32 v2, s01103; VI-NEXT: s_waitcnt lgkmcnt(0)1104; VI-NEXT: v_mov_b32_e32 v1, s21105; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]1106; VI-NEXT: s_endpgm1107;1108; EG-LABEL: v_shl_32_i64:1109; EG: ; %bb.0:1110; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]1111; EG-NEXT: TEX 0 @61112; EG-NEXT: ALU 4, @11, KC0[CB0:0-32], KC1[]1113; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XY, T2.X, 11114; EG-NEXT: CF_END1115; EG-NEXT: PAD1116; EG-NEXT: Fetch clause starting at 6:1117; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #11118; EG-NEXT: ALU clause starting at 8:1119; EG-NEXT: LSHL * T0.W, T1.X, literal.x,1120; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)1121; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,1122; EG-NEXT: ALU clause starting at 11:1123; EG-NEXT: MOV T1.X, 0.0,1124; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, T0.W,1125; EG-NEXT: LSHR T2.X, PV.W, literal.x,1126; EG-NEXT: MOV * T1.Y, T0.X,1127; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1128 %tid = call i32 @llvm.amdgcn.workgroup.id.x() #01129 %gep.in = getelementptr i64, ptr addrspace(1) %in, i32 %tid1130 %gep.out = getelementptr i64, ptr addrspace(1) %out, i32 %tid1131 %a = load i64, ptr addrspace(1) %gep.in1132 %result = shl i64 %a, 321133 store i64 %result, ptr addrspace(1) %gep.out1134 ret void1135}1136 1137define amdgpu_kernel void @s_shl_constant_i64(ptr addrspace(1) %out, i64 %a) {1138; SI-LABEL: s_shl_constant_i64:1139; SI: ; %bb.0:1140; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91141; SI-NEXT: s_mov_b32 s6, -11142; SI-NEXT: s_mov_b32 s9, 0xffff1143; SI-NEXT: s_mov_b32 s8, s61144; SI-NEXT: s_mov_b32 s7, 0xf0001145; SI-NEXT: s_waitcnt lgkmcnt(0)1146; SI-NEXT: s_mov_b32 s4, s01147; SI-NEXT: s_mov_b32 s5, s11148; SI-NEXT: s_lshl_b64 s[0:1], s[8:9], s21149; SI-NEXT: v_mov_b32_e32 v0, s01150; SI-NEXT: v_mov_b32_e32 v1, s11151; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 01152; SI-NEXT: s_endpgm1153;1154; VI-LABEL: s_shl_constant_i64:1155; VI: ; %bb.0:1156; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241157; VI-NEXT: s_mov_b32 s6, -11158; VI-NEXT: s_mov_b32 s9, 0xffff1159; VI-NEXT: s_mov_b32 s8, s61160; VI-NEXT: s_mov_b32 s7, 0xf0001161; VI-NEXT: s_waitcnt lgkmcnt(0)1162; VI-NEXT: s_mov_b32 s4, s01163; VI-NEXT: s_mov_b32 s5, s11164; VI-NEXT: s_lshl_b64 s[0:1], s[8:9], s21165; VI-NEXT: v_mov_b32_e32 v0, s01166; VI-NEXT: v_mov_b32_e32 v1, s11167; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 01168; VI-NEXT: s_endpgm1169;1170; EG-LABEL: s_shl_constant_i64:1171; EG: ; %bb.0:1172; EG-NEXT: ALU 12, @4, KC0[CB0:0-32], KC1[]1173; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 11174; EG-NEXT: CF_END1175; EG-NEXT: PAD1176; EG-NEXT: ALU clause starting at 4:1177; EG-NEXT: MOV T0.Z, literal.x,1178; EG-NEXT: NOT_INT T0.W, KC0[2].W,1179; EG-NEXT: AND_INT * T1.W, KC0[2].W, literal.y,1180; EG-NEXT: -1(nan), 31(4.344025e-44)1181; EG-NEXT: LSHL T1.Z, literal.x, PS,1182; EG-NEXT: BIT_ALIGN_INT T0.W, literal.y, PV.Z, PV.W,1183; EG-NEXT: AND_INT * T1.W, KC0[2].W, literal.z,1184; EG-NEXT: -1(nan), 32767(4.591635e-41)1185; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)1186; EG-NEXT: CNDE_INT * T0.Y, PS, PV.W, PV.Z,1187; EG-NEXT: CNDE_INT T0.X, T1.W, T1.Z, 0.0,1188; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1189; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1190 %shl = shl i64 281474976710655, %a1191 store i64 %shl, ptr addrspace(1) %out, align 81192 ret void1193}1194 1195define amdgpu_kernel void @v_shl_constant_i64(ptr addrspace(1) %out, ptr addrspace(1) %aptr) {1196; SI-LABEL: v_shl_constant_i64:1197; SI: ; %bb.0:1198; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91199; SI-NEXT: s_mov_b32 s7, 0xf0001200; SI-NEXT: s_mov_b32 s6, -11201; SI-NEXT: s_mov_b32 s10, s61202; SI-NEXT: s_mov_b32 s11, s71203; SI-NEXT: s_waitcnt lgkmcnt(0)1204; SI-NEXT: s_mov_b32 s8, s21205; SI-NEXT: s_mov_b32 s9, s31206; SI-NEXT: buffer_load_dword v0, off, s[8:11], 01207; SI-NEXT: s_mov_b32 s2, 0xab19b2071208; SI-NEXT: s_movk_i32 s3, 0x11e1209; SI-NEXT: s_mov_b32 s4, s01210; SI-NEXT: s_mov_b32 s5, s11211; SI-NEXT: s_waitcnt vmcnt(0)1212; SI-NEXT: v_lshl_b64 v[0:1], s[2:3], v01213; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 01214; SI-NEXT: s_endpgm1215;1216; VI-LABEL: v_shl_constant_i64:1217; VI: ; %bb.0:1218; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241219; VI-NEXT: s_mov_b32 s7, 0xf0001220; VI-NEXT: s_mov_b32 s6, -11221; VI-NEXT: s_waitcnt lgkmcnt(0)1222; VI-NEXT: s_load_dword s2, s[2:3], 0x01223; VI-NEXT: s_mov_b32 s4, s01224; VI-NEXT: s_mov_b32 s5, s11225; VI-NEXT: s_mov_b32 s0, 0xab19b2071226; VI-NEXT: s_movk_i32 s1, 0x11e1227; VI-NEXT: s_waitcnt lgkmcnt(0)1228; VI-NEXT: s_lshl_b64 s[0:1], s[0:1], s21229; VI-NEXT: v_mov_b32_e32 v0, s01230; VI-NEXT: v_mov_b32_e32 v1, s11231; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 01232; VI-NEXT: s_endpgm1233;1234; EG-LABEL: v_shl_constant_i64:1235; EG: ; %bb.0:1236; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]1237; EG-NEXT: TEX 0 @61238; EG-NEXT: ALU 12, @9, KC0[CB0:0-32], KC1[]1239; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 11240; EG-NEXT: CF_END1241; EG-NEXT: PAD1242; EG-NEXT: Fetch clause starting at 6:1243; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #11244; EG-NEXT: ALU clause starting at 8:1245; EG-NEXT: MOV * T0.X, KC0[2].Z,1246; EG-NEXT: ALU clause starting at 9:1247; EG-NEXT: NOT_INT T0.Z, T0.X,1248; EG-NEXT: MOV T0.W, literal.x,1249; EG-NEXT: AND_INT * T1.W, T0.X, literal.y,1250; EG-NEXT: 1435293955(1.935796e+13), 31(4.344025e-44)1251; EG-NEXT: LSHL T1.Z, literal.x, PS,1252; EG-NEXT: BIT_ALIGN_INT T0.W, literal.y, PV.W, PV.Z,1253; EG-NEXT: AND_INT * T1.W, T0.X, literal.z,1254; EG-NEXT: -1424379385(-5.460358e-13), 143(2.003857e-43)1255; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)1256; EG-NEXT: CNDE_INT * T0.Y, PS, PV.W, PV.Z,1257; EG-NEXT: CNDE_INT T0.X, T1.W, T1.Z, 0.0,1258; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1259; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1260 %a = load i64, ptr addrspace(1) %aptr, align 81261 %shl = shl i64 1231231234567, %a1262 store i64 %shl, ptr addrspace(1) %out, align 81263 ret void1264}1265 1266define amdgpu_kernel void @v_shl_i64_32_bit_constant(ptr addrspace(1) %out, ptr addrspace(1) %aptr) {1267; SI-LABEL: v_shl_i64_32_bit_constant:1268; SI: ; %bb.0:1269; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91270; SI-NEXT: s_mov_b32 s7, 0xf0001271; SI-NEXT: s_mov_b32 s6, -11272; SI-NEXT: s_mov_b32 s10, s61273; SI-NEXT: s_mov_b32 s11, s71274; SI-NEXT: s_waitcnt lgkmcnt(0)1275; SI-NEXT: s_mov_b32 s8, s21276; SI-NEXT: s_mov_b32 s9, s31277; SI-NEXT: buffer_load_dword v0, off, s[8:11], 01278; SI-NEXT: s_mov_b64 s[2:3], 0x12d6871279; SI-NEXT: s_mov_b32 s4, s01280; SI-NEXT: s_mov_b32 s5, s11281; SI-NEXT: s_waitcnt vmcnt(0)1282; SI-NEXT: v_lshl_b64 v[0:1], s[2:3], v01283; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 01284; SI-NEXT: s_endpgm1285;1286; VI-LABEL: v_shl_i64_32_bit_constant:1287; VI: ; %bb.0:1288; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241289; VI-NEXT: s_waitcnt lgkmcnt(0)1290; VI-NEXT: s_load_dword s4, s[2:3], 0x01291; VI-NEXT: s_mov_b32 s3, 0xf0001292; VI-NEXT: s_mov_b32 s2, -11293; VI-NEXT: s_waitcnt lgkmcnt(0)1294; VI-NEXT: s_lshl_b64 s[4:5], 0x12d687, s41295; VI-NEXT: v_mov_b32_e32 v0, s41296; VI-NEXT: v_mov_b32_e32 v1, s51297; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 01298; VI-NEXT: s_endpgm1299;1300; EG-LABEL: v_shl_i64_32_bit_constant:1301; EG: ; %bb.0:1302; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]1303; EG-NEXT: TEX 0 @61304; EG-NEXT: ALU 11, @9, KC0[CB0:0-32], KC1[]1305; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 11306; EG-NEXT: CF_END1307; EG-NEXT: PAD1308; EG-NEXT: Fetch clause starting at 6:1309; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #11310; EG-NEXT: ALU clause starting at 8:1311; EG-NEXT: MOV * T0.X, KC0[2].Z,1312; EG-NEXT: ALU clause starting at 9:1313; EG-NEXT: AND_INT T0.W, T0.X, literal.x,1314; EG-NEXT: NOT_INT * T1.W, T0.X,1315; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)1316; EG-NEXT: BIT_ALIGN_INT T0.Z, 0.0, literal.x, PS,1317; EG-NEXT: LSHL T0.W, literal.y, PV.W,1318; EG-NEXT: AND_INT * T1.W, T0.X, literal.z,1319; EG-NEXT: 617283(8.649977e-40), 1234567(1.729997e-39)1320; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)1321; EG-NEXT: CNDE_INT * T0.Y, PS, PV.Z, PV.W,1322; EG-NEXT: CNDE_INT T0.X, T1.W, T0.W, 0.0,1323; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1324; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1325 %a = load i64, ptr addrspace(1) %aptr, align 81326 %shl = shl i64 1234567, %a1327 store i64 %shl, ptr addrspace(1) %out, align 81328 ret void1329}1330 1331define amdgpu_kernel void @v_shl_inline_imm_64_i64(ptr addrspace(1) %out, ptr addrspace(1) %aptr) {1332; SI-LABEL: v_shl_inline_imm_64_i64:1333; SI: ; %bb.0:1334; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91335; SI-NEXT: s_mov_b32 s7, 0xf0001336; SI-NEXT: s_mov_b32 s6, -11337; SI-NEXT: s_mov_b32 s10, s61338; SI-NEXT: s_mov_b32 s11, s71339; SI-NEXT: s_waitcnt lgkmcnt(0)1340; SI-NEXT: s_mov_b32 s8, s21341; SI-NEXT: s_mov_b32 s9, s31342; SI-NEXT: buffer_load_dword v0, off, s[8:11], 01343; SI-NEXT: s_mov_b32 s4, s01344; SI-NEXT: s_mov_b32 s5, s11345; SI-NEXT: s_waitcnt vmcnt(0)1346; SI-NEXT: v_lshl_b64 v[0:1], 64, v01347; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 01348; SI-NEXT: s_endpgm1349;1350; VI-LABEL: v_shl_inline_imm_64_i64:1351; VI: ; %bb.0:1352; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241353; VI-NEXT: s_waitcnt lgkmcnt(0)1354; VI-NEXT: s_load_dword s4, s[2:3], 0x01355; VI-NEXT: s_mov_b32 s3, 0xf0001356; VI-NEXT: s_mov_b32 s2, -11357; VI-NEXT: s_waitcnt lgkmcnt(0)1358; VI-NEXT: s_lshl_b64 s[4:5], 64, s41359; VI-NEXT: v_mov_b32_e32 v0, s41360; VI-NEXT: v_mov_b32_e32 v1, s51361; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 01362; VI-NEXT: s_endpgm1363;1364; EG-LABEL: v_shl_inline_imm_64_i64:1365; EG: ; %bb.0:1366; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]1367; EG-NEXT: TEX 0 @61368; EG-NEXT: ALU 10, @9, KC0[CB0:0-32], KC1[]1369; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 11370; EG-NEXT: CF_END1371; EG-NEXT: PAD1372; EG-NEXT: Fetch clause starting at 6:1373; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #11374; EG-NEXT: ALU clause starting at 8:1375; EG-NEXT: MOV * T0.X, KC0[2].Z,1376; EG-NEXT: ALU clause starting at 9:1377; EG-NEXT: AND_INT T0.W, T0.X, literal.x,1378; EG-NEXT: NOT_INT * T1.W, T0.X,1379; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)1380; EG-NEXT: BIT_ALIGN_INT T0.Z, 0.0, literal.x, PS,1381; EG-NEXT: LSHL T0.W, literal.y, PV.W,1382; EG-NEXT: AND_INT * T1.W, T0.X, literal.x,1383; EG-NEXT: 32(4.484155e-44), 64(8.968310e-44)1384; EG-NEXT: CNDE_INT * T0.Y, PS, PV.Z, PV.W,1385; EG-NEXT: CNDE_INT T0.X, T1.W, T0.W, 0.0,1386; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1387; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1388 %a = load i64, ptr addrspace(1) %aptr, align 81389 %shl = shl i64 64, %a1390 store i64 %shl, ptr addrspace(1) %out, align 81391 ret void1392}1393 1394define amdgpu_kernel void @s_shl_inline_imm_64_i64(ptr addrspace(1) %out, ptr addrspace(1) %aptr, i64 %a) {1395; SI-LABEL: s_shl_inline_imm_64_i64:1396; SI: ; %bb.0:1397; SI-NEXT: s_load_dword s6, s[4:5], 0xd1398; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x91399; SI-NEXT: s_mov_b32 s3, 0xf0001400; SI-NEXT: s_mov_b32 s2, -11401; SI-NEXT: s_waitcnt lgkmcnt(0)1402; SI-NEXT: s_lshl_b64 s[4:5], 64, s61403; SI-NEXT: v_mov_b32_e32 v0, s41404; SI-NEXT: v_mov_b32_e32 v1, s51405; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 01406; SI-NEXT: s_endpgm1407;1408; VI-LABEL: s_shl_inline_imm_64_i64:1409; VI: ; %bb.0:1410; VI-NEXT: s_load_dword s6, s[4:5], 0x341411; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x241412; VI-NEXT: s_mov_b32 s3, 0xf0001413; VI-NEXT: s_mov_b32 s2, -11414; VI-NEXT: s_waitcnt lgkmcnt(0)1415; VI-NEXT: s_lshl_b64 s[4:5], 64, s61416; VI-NEXT: v_mov_b32_e32 v0, s41417; VI-NEXT: v_mov_b32_e32 v1, s51418; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 01419; VI-NEXT: s_endpgm1420;1421; EG-LABEL: s_shl_inline_imm_64_i64:1422; EG: ; %bb.0:1423; EG-NEXT: ALU 10, @4, KC0[CB0:0-32], KC1[]1424; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 11425; EG-NEXT: CF_END1426; EG-NEXT: PAD1427; EG-NEXT: ALU clause starting at 4:1428; EG-NEXT: AND_INT T0.W, KC0[2].W, literal.x,1429; EG-NEXT: NOT_INT * T1.W, KC0[2].W,1430; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)1431; EG-NEXT: BIT_ALIGN_INT T0.Z, 0.0, literal.x, PS,1432; EG-NEXT: AND_INT T1.W, KC0[2].W, literal.x,1433; EG-NEXT: LSHL * T0.W, literal.y, PV.W,1434; EG-NEXT: 32(4.484155e-44), 64(8.968310e-44)1435; EG-NEXT: CNDE_INT * T0.Y, PV.W, PV.Z, PS,1436; EG-NEXT: CNDE_INT T0.X, T1.W, T0.W, 0.0,1437; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1438; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1439 %shl = shl i64 64, %a1440 store i64 %shl, ptr addrspace(1) %out, align 81441 ret void1442}1443 1444define amdgpu_kernel void @s_shl_inline_imm_1_i64(ptr addrspace(1) %out, ptr addrspace(1) %aptr, i64 %a) {1445; SI-LABEL: s_shl_inline_imm_1_i64:1446; SI: ; %bb.0:1447; SI-NEXT: s_load_dword s6, s[4:5], 0xd1448; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x91449; SI-NEXT: s_mov_b32 s3, 0xf0001450; SI-NEXT: s_mov_b32 s2, -11451; SI-NEXT: s_waitcnt lgkmcnt(0)1452; SI-NEXT: s_lshl_b64 s[4:5], 1, s61453; SI-NEXT: v_mov_b32_e32 v0, s41454; SI-NEXT: v_mov_b32_e32 v1, s51455; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 01456; SI-NEXT: s_endpgm1457;1458; VI-LABEL: s_shl_inline_imm_1_i64:1459; VI: ; %bb.0:1460; VI-NEXT: s_load_dword s6, s[4:5], 0x341461; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x241462; VI-NEXT: s_mov_b32 s3, 0xf0001463; VI-NEXT: s_mov_b32 s2, -11464; VI-NEXT: s_waitcnt lgkmcnt(0)1465; VI-NEXT: s_lshl_b64 s[4:5], 1, s61466; VI-NEXT: v_mov_b32_e32 v0, s41467; VI-NEXT: v_mov_b32_e32 v1, s51468; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 01469; VI-NEXT: s_endpgm1470;1471; EG-LABEL: s_shl_inline_imm_1_i64:1472; EG: ; %bb.0:1473; EG-NEXT: ALU 11, @4, KC0[CB0:0-32], KC1[]1474; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 11475; EG-NEXT: CF_END1476; EG-NEXT: PAD1477; EG-NEXT: ALU clause starting at 4:1478; EG-NEXT: AND_INT T0.W, KC0[2].W, literal.x,1479; EG-NEXT: LSHL * T1.W, KC0[2].W, literal.y,1480; EG-NEXT: 31(4.344025e-44), 26(3.643376e-44)1481; EG-NEXT: ASHR T1.W, PS, literal.x,1482; EG-NEXT: LSHL * T0.W, 1, PV.W,1483; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)1484; EG-NEXT: AND_INT T0.Y, PV.W, PS,1485; EG-NEXT: AND_INT * T1.W, KC0[2].W, literal.x,1486; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)1487; EG-NEXT: CNDE_INT T0.X, PV.W, T0.W, 0.0,1488; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1489; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1490 %shl = shl i64 1, %a1491 store i64 %shl, ptr addrspace(1) %out, align 81492 ret void1493}1494 1495define amdgpu_kernel void @s_shl_inline_imm_1_0_i64(ptr addrspace(1) %out, ptr addrspace(1) %aptr, i64 %a) {1496; SI-LABEL: s_shl_inline_imm_1_0_i64:1497; SI: ; %bb.0:1498; SI-NEXT: s_load_dword s6, s[4:5], 0xd1499; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x91500; SI-NEXT: s_mov_b32 s3, 0xf0001501; SI-NEXT: s_mov_b32 s2, -11502; SI-NEXT: s_waitcnt lgkmcnt(0)1503; SI-NEXT: s_lshl_b64 s[4:5], 1.0, s61504; SI-NEXT: v_mov_b32_e32 v0, s41505; SI-NEXT: v_mov_b32_e32 v1, s51506; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 01507; SI-NEXT: s_endpgm1508;1509; VI-LABEL: s_shl_inline_imm_1_0_i64:1510; VI: ; %bb.0:1511; VI-NEXT: s_load_dword s6, s[4:5], 0x341512; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x241513; VI-NEXT: s_mov_b32 s3, 0xf0001514; VI-NEXT: s_mov_b32 s2, -11515; VI-NEXT: s_waitcnt lgkmcnt(0)1516; VI-NEXT: s_lshl_b64 s[4:5], 1.0, s61517; VI-NEXT: v_mov_b32_e32 v0, s41518; VI-NEXT: v_mov_b32_e32 v1, s51519; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 01520; VI-NEXT: s_endpgm1521;1522; EG-LABEL: s_shl_inline_imm_1_0_i64:1523; EG: ; %bb.0:1524; EG-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[]1525; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 11526; EG-NEXT: CF_END1527; EG-NEXT: PAD1528; EG-NEXT: ALU clause starting at 4:1529; EG-NEXT: NOT_INT * T0.W, KC0[2].W,1530; EG-NEXT: BIT_ALIGN_INT T0.W, literal.x, 0.0, PV.W,1531; EG-NEXT: AND_INT * T1.W, KC0[2].W, literal.y,1532; EG-NEXT: 536346624(1.050321e-19), 32(4.484155e-44)1533; EG-NEXT: CNDE_INT * T0.Y, PS, PV.W, 0.0,1534; EG-NEXT: MOV T0.X, 0.0,1535; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1536; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1537 %shl = shl i64 4607182418800017408, %a1538 store i64 %shl, ptr addrspace(1) %out, align 81539 ret void1540}1541 1542define amdgpu_kernel void @s_shl_inline_imm_neg_1_0_i64(ptr addrspace(1) %out, ptr addrspace(1) %aptr, i64 %a) {1543; SI-LABEL: s_shl_inline_imm_neg_1_0_i64:1544; SI: ; %bb.0:1545; SI-NEXT: s_load_dword s6, s[4:5], 0xd1546; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x91547; SI-NEXT: s_mov_b32 s3, 0xf0001548; SI-NEXT: s_mov_b32 s2, -11549; SI-NEXT: s_waitcnt lgkmcnt(0)1550; SI-NEXT: s_lshl_b64 s[4:5], -1.0, s61551; SI-NEXT: v_mov_b32_e32 v0, s41552; SI-NEXT: v_mov_b32_e32 v1, s51553; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 01554; SI-NEXT: s_endpgm1555;1556; VI-LABEL: s_shl_inline_imm_neg_1_0_i64:1557; VI: ; %bb.0:1558; VI-NEXT: s_load_dword s6, s[4:5], 0x341559; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x241560; VI-NEXT: s_mov_b32 s3, 0xf0001561; VI-NEXT: s_mov_b32 s2, -11562; VI-NEXT: s_waitcnt lgkmcnt(0)1563; VI-NEXT: s_lshl_b64 s[4:5], -1.0, s61564; VI-NEXT: v_mov_b32_e32 v0, s41565; VI-NEXT: v_mov_b32_e32 v1, s51566; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 01567; VI-NEXT: s_endpgm1568;1569; EG-LABEL: s_shl_inline_imm_neg_1_0_i64:1570; EG: ; %bb.0:1571; EG-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[]1572; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 11573; EG-NEXT: CF_END1574; EG-NEXT: PAD1575; EG-NEXT: ALU clause starting at 4:1576; EG-NEXT: NOT_INT * T0.W, KC0[2].W,1577; EG-NEXT: BIT_ALIGN_INT T0.W, literal.x, 0.0, PV.W,1578; EG-NEXT: AND_INT * T1.W, KC0[2].W, literal.y,1579; EG-NEXT: 1610088448(3.574057e+19), 32(4.484155e-44)1580; EG-NEXT: CNDE_INT * T0.Y, PS, PV.W, 0.0,1581; EG-NEXT: MOV T0.X, 0.0,1582; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1583; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1584 %shl = shl i64 13830554455654793216, %a1585 store i64 %shl, ptr addrspace(1) %out, align 81586 ret void1587}1588 1589define amdgpu_kernel void @s_shl_inline_imm_0_5_i64(ptr addrspace(1) %out, ptr addrspace(1) %aptr, i64 %a) {1590; SI-LABEL: s_shl_inline_imm_0_5_i64:1591; SI: ; %bb.0:1592; SI-NEXT: s_load_dword s6, s[4:5], 0xd1593; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x91594; SI-NEXT: s_mov_b32 s3, 0xf0001595; SI-NEXT: s_mov_b32 s2, -11596; SI-NEXT: s_waitcnt lgkmcnt(0)1597; SI-NEXT: s_lshl_b64 s[4:5], 0.5, s61598; SI-NEXT: v_mov_b32_e32 v0, s41599; SI-NEXT: v_mov_b32_e32 v1, s51600; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 01601; SI-NEXT: s_endpgm1602;1603; VI-LABEL: s_shl_inline_imm_0_5_i64:1604; VI: ; %bb.0:1605; VI-NEXT: s_load_dword s6, s[4:5], 0x341606; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x241607; VI-NEXT: s_mov_b32 s3, 0xf0001608; VI-NEXT: s_mov_b32 s2, -11609; VI-NEXT: s_waitcnt lgkmcnt(0)1610; VI-NEXT: s_lshl_b64 s[4:5], 0.5, s61611; VI-NEXT: v_mov_b32_e32 v0, s41612; VI-NEXT: v_mov_b32_e32 v1, s51613; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 01614; VI-NEXT: s_endpgm1615;1616; EG-LABEL: s_shl_inline_imm_0_5_i64:1617; EG: ; %bb.0:1618; EG-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[]1619; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 11620; EG-NEXT: CF_END1621; EG-NEXT: PAD1622; EG-NEXT: ALU clause starting at 4:1623; EG-NEXT: NOT_INT * T0.W, KC0[2].W,1624; EG-NEXT: BIT_ALIGN_INT T0.W, literal.x, 0.0, PV.W,1625; EG-NEXT: AND_INT * T1.W, KC0[2].W, literal.y,1626; EG-NEXT: 535822336(1.016440e-19), 32(4.484155e-44)1627; EG-NEXT: CNDE_INT * T0.Y, PS, PV.W, 0.0,1628; EG-NEXT: MOV T0.X, 0.0,1629; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1630; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1631 %shl = shl i64 4602678819172646912, %a1632 store i64 %shl, ptr addrspace(1) %out, align 81633 ret void1634}1635 1636define amdgpu_kernel void @s_shl_inline_imm_neg_0_5_i64(ptr addrspace(1) %out, ptr addrspace(1) %aptr, i64 %a) {1637; SI-LABEL: s_shl_inline_imm_neg_0_5_i64:1638; SI: ; %bb.0:1639; SI-NEXT: s_load_dword s6, s[4:5], 0xd1640; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x91641; SI-NEXT: s_mov_b32 s3, 0xf0001642; SI-NEXT: s_mov_b32 s2, -11643; SI-NEXT: s_waitcnt lgkmcnt(0)1644; SI-NEXT: s_lshl_b64 s[4:5], -0.5, s61645; SI-NEXT: v_mov_b32_e32 v0, s41646; SI-NEXT: v_mov_b32_e32 v1, s51647; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 01648; SI-NEXT: s_endpgm1649;1650; VI-LABEL: s_shl_inline_imm_neg_0_5_i64:1651; VI: ; %bb.0:1652; VI-NEXT: s_load_dword s6, s[4:5], 0x341653; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x241654; VI-NEXT: s_mov_b32 s3, 0xf0001655; VI-NEXT: s_mov_b32 s2, -11656; VI-NEXT: s_waitcnt lgkmcnt(0)1657; VI-NEXT: s_lshl_b64 s[4:5], -0.5, s61658; VI-NEXT: v_mov_b32_e32 v0, s41659; VI-NEXT: v_mov_b32_e32 v1, s51660; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 01661; VI-NEXT: s_endpgm1662;1663; EG-LABEL: s_shl_inline_imm_neg_0_5_i64:1664; EG: ; %bb.0:1665; EG-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[]1666; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 11667; EG-NEXT: CF_END1668; EG-NEXT: PAD1669; EG-NEXT: ALU clause starting at 4:1670; EG-NEXT: NOT_INT * T0.W, KC0[2].W,1671; EG-NEXT: BIT_ALIGN_INT T0.W, literal.x, 0.0, PV.W,1672; EG-NEXT: AND_INT * T1.W, KC0[2].W, literal.y,1673; EG-NEXT: 1609564160(3.458765e+19), 32(4.484155e-44)1674; EG-NEXT: CNDE_INT * T0.Y, PS, PV.W, 0.0,1675; EG-NEXT: MOV T0.X, 0.0,1676; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1677; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1678 %shl = shl i64 13826050856027422720, %a1679 store i64 %shl, ptr addrspace(1) %out, align 81680 ret void1681}1682 1683define amdgpu_kernel void @s_shl_inline_imm_2_0_i64(ptr addrspace(1) %out, ptr addrspace(1) %aptr, i64 %a) {1684; SI-LABEL: s_shl_inline_imm_2_0_i64:1685; SI: ; %bb.0:1686; SI-NEXT: s_load_dword s6, s[4:5], 0xd1687; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x91688; SI-NEXT: s_mov_b32 s3, 0xf0001689; SI-NEXT: s_mov_b32 s2, -11690; SI-NEXT: s_waitcnt lgkmcnt(0)1691; SI-NEXT: s_lshl_b64 s[4:5], 2.0, s61692; SI-NEXT: v_mov_b32_e32 v0, s41693; SI-NEXT: v_mov_b32_e32 v1, s51694; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 01695; SI-NEXT: s_endpgm1696;1697; VI-LABEL: s_shl_inline_imm_2_0_i64:1698; VI: ; %bb.0:1699; VI-NEXT: s_load_dword s6, s[4:5], 0x341700; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x241701; VI-NEXT: s_mov_b32 s3, 0xf0001702; VI-NEXT: s_mov_b32 s2, -11703; VI-NEXT: s_waitcnt lgkmcnt(0)1704; VI-NEXT: s_lshl_b64 s[4:5], 2.0, s61705; VI-NEXT: v_mov_b32_e32 v0, s41706; VI-NEXT: v_mov_b32_e32 v1, s51707; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 01708; VI-NEXT: s_endpgm1709;1710; EG-LABEL: s_shl_inline_imm_2_0_i64:1711; EG: ; %bb.0:1712; EG-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[]1713; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 11714; EG-NEXT: CF_END1715; EG-NEXT: PAD1716; EG-NEXT: ALU clause starting at 4:1717; EG-NEXT: NOT_INT * T0.W, KC0[2].W,1718; EG-NEXT: BIT_ALIGN_INT T0.W, literal.x, 0.0, PV.W,1719; EG-NEXT: AND_INT * T1.W, KC0[2].W, literal.y,1720; EG-NEXT: 536870912(1.084202e-19), 32(4.484155e-44)1721; EG-NEXT: CNDE_INT * T0.Y, PS, PV.W, 0.0,1722; EG-NEXT: MOV T0.X, 0.0,1723; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1724; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1725 %shl = shl i64 4611686018427387904, %a1726 store i64 %shl, ptr addrspace(1) %out, align 81727 ret void1728}1729 1730define amdgpu_kernel void @s_shl_inline_imm_neg_2_0_i64(ptr addrspace(1) %out, ptr addrspace(1) %aptr, i64 %a) {1731; SI-LABEL: s_shl_inline_imm_neg_2_0_i64:1732; SI: ; %bb.0:1733; SI-NEXT: s_load_dword s6, s[4:5], 0xd1734; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x91735; SI-NEXT: s_mov_b32 s3, 0xf0001736; SI-NEXT: s_mov_b32 s2, -11737; SI-NEXT: s_waitcnt lgkmcnt(0)1738; SI-NEXT: s_lshl_b64 s[4:5], -2.0, s61739; SI-NEXT: v_mov_b32_e32 v0, s41740; SI-NEXT: v_mov_b32_e32 v1, s51741; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 01742; SI-NEXT: s_endpgm1743;1744; VI-LABEL: s_shl_inline_imm_neg_2_0_i64:1745; VI: ; %bb.0:1746; VI-NEXT: s_load_dword s6, s[4:5], 0x341747; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x241748; VI-NEXT: s_mov_b32 s3, 0xf0001749; VI-NEXT: s_mov_b32 s2, -11750; VI-NEXT: s_waitcnt lgkmcnt(0)1751; VI-NEXT: s_lshl_b64 s[4:5], -2.0, s61752; VI-NEXT: v_mov_b32_e32 v0, s41753; VI-NEXT: v_mov_b32_e32 v1, s51754; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 01755; VI-NEXT: s_endpgm1756;1757; EG-LABEL: s_shl_inline_imm_neg_2_0_i64:1758; EG: ; %bb.0:1759; EG-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[]1760; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 11761; EG-NEXT: CF_END1762; EG-NEXT: PAD1763; EG-NEXT: ALU clause starting at 4:1764; EG-NEXT: NOT_INT * T0.W, KC0[2].W,1765; EG-NEXT: BIT_ALIGN_INT T0.W, literal.x, 0.0, PV.W,1766; EG-NEXT: AND_INT * T1.W, KC0[2].W, literal.y,1767; EG-NEXT: 1610612736(3.689349e+19), 32(4.484155e-44)1768; EG-NEXT: CNDE_INT * T0.Y, PS, PV.W, 0.0,1769; EG-NEXT: MOV T0.X, 0.0,1770; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1771; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1772 %shl = shl i64 13835058055282163712, %a1773 store i64 %shl, ptr addrspace(1) %out, align 81774 ret void1775}1776 1777define amdgpu_kernel void @s_shl_inline_imm_4_0_i64(ptr addrspace(1) %out, ptr addrspace(1) %aptr, i64 %a) {1778; SI-LABEL: s_shl_inline_imm_4_0_i64:1779; SI: ; %bb.0:1780; SI-NEXT: s_load_dword s6, s[4:5], 0xd1781; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x91782; SI-NEXT: s_mov_b32 s3, 0xf0001783; SI-NEXT: s_mov_b32 s2, -11784; SI-NEXT: s_waitcnt lgkmcnt(0)1785; SI-NEXT: s_lshl_b64 s[4:5], 4.0, s61786; SI-NEXT: v_mov_b32_e32 v0, s41787; SI-NEXT: v_mov_b32_e32 v1, s51788; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 01789; SI-NEXT: s_endpgm1790;1791; VI-LABEL: s_shl_inline_imm_4_0_i64:1792; VI: ; %bb.0:1793; VI-NEXT: s_load_dword s6, s[4:5], 0x341794; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x241795; VI-NEXT: s_mov_b32 s3, 0xf0001796; VI-NEXT: s_mov_b32 s2, -11797; VI-NEXT: s_waitcnt lgkmcnt(0)1798; VI-NEXT: s_lshl_b64 s[4:5], 4.0, s61799; VI-NEXT: v_mov_b32_e32 v0, s41800; VI-NEXT: v_mov_b32_e32 v1, s51801; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 01802; VI-NEXT: s_endpgm1803;1804; EG-LABEL: s_shl_inline_imm_4_0_i64:1805; EG: ; %bb.0:1806; EG-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[]1807; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 11808; EG-NEXT: CF_END1809; EG-NEXT: PAD1810; EG-NEXT: ALU clause starting at 4:1811; EG-NEXT: NOT_INT * T0.W, KC0[2].W,1812; EG-NEXT: BIT_ALIGN_INT T0.W, literal.x, 0.0, PV.W,1813; EG-NEXT: AND_INT * T1.W, KC0[2].W, literal.y,1814; EG-NEXT: 537395200(1.151965e-19), 32(4.484155e-44)1815; EG-NEXT: CNDE_INT * T0.Y, PS, PV.W, 0.0,1816; EG-NEXT: MOV T0.X, 0.0,1817; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1818; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1819 %shl = shl i64 4616189618054758400, %a1820 store i64 %shl, ptr addrspace(1) %out, align 81821 ret void1822}1823 1824define amdgpu_kernel void @s_shl_inline_imm_neg_4_0_i64(ptr addrspace(1) %out, ptr addrspace(1) %aptr, i64 %a) {1825; SI-LABEL: s_shl_inline_imm_neg_4_0_i64:1826; SI: ; %bb.0:1827; SI-NEXT: s_load_dword s6, s[4:5], 0xd1828; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x91829; SI-NEXT: s_mov_b32 s3, 0xf0001830; SI-NEXT: s_mov_b32 s2, -11831; SI-NEXT: s_waitcnt lgkmcnt(0)1832; SI-NEXT: s_lshl_b64 s[4:5], -4.0, s61833; SI-NEXT: v_mov_b32_e32 v0, s41834; SI-NEXT: v_mov_b32_e32 v1, s51835; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 01836; SI-NEXT: s_endpgm1837;1838; VI-LABEL: s_shl_inline_imm_neg_4_0_i64:1839; VI: ; %bb.0:1840; VI-NEXT: s_load_dword s6, s[4:5], 0x341841; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x241842; VI-NEXT: s_mov_b32 s3, 0xf0001843; VI-NEXT: s_mov_b32 s2, -11844; VI-NEXT: s_waitcnt lgkmcnt(0)1845; VI-NEXT: s_lshl_b64 s[4:5], -4.0, s61846; VI-NEXT: v_mov_b32_e32 v0, s41847; VI-NEXT: v_mov_b32_e32 v1, s51848; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 01849; VI-NEXT: s_endpgm1850;1851; EG-LABEL: s_shl_inline_imm_neg_4_0_i64:1852; EG: ; %bb.0:1853; EG-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[]1854; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 11855; EG-NEXT: CF_END1856; EG-NEXT: PAD1857; EG-NEXT: ALU clause starting at 4:1858; EG-NEXT: NOT_INT * T0.W, KC0[2].W,1859; EG-NEXT: BIT_ALIGN_INT T0.W, literal.x, 0.0, PV.W,1860; EG-NEXT: AND_INT * T1.W, KC0[2].W, literal.y,1861; EG-NEXT: 1611137024(3.919933e+19), 32(4.484155e-44)1862; EG-NEXT: CNDE_INT * T0.Y, PS, PV.W, 0.0,1863; EG-NEXT: MOV T0.X, 0.0,1864; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1865; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1866 %shl = shl i64 13839561654909534208, %a1867 store i64 %shl, ptr addrspace(1) %out, align 81868 ret void1869}1870 1871 1872; Test with the 64-bit integer bitpattern for a 32-bit float in the1873; low 32-bits, which is not a valid 64-bit inline immmediate.1874define amdgpu_kernel void @s_shl_inline_imm_f32_4_0_i64(ptr addrspace(1) %out, ptr addrspace(1) %aptr, i64 %a) {1875; SI-LABEL: s_shl_inline_imm_f32_4_0_i64:1876; SI: ; %bb.0:1877; SI-NEXT: s_load_dword s6, s[4:5], 0xd1878; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x91879; SI-NEXT: s_mov_b32 s3, 0xf0001880; SI-NEXT: s_mov_b32 s2, -11881; SI-NEXT: s_waitcnt lgkmcnt(0)1882; SI-NEXT: s_lshl_b64 s[4:5], 0x40800000, s61883; SI-NEXT: v_mov_b32_e32 v0, s41884; SI-NEXT: v_mov_b32_e32 v1, s51885; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 01886; SI-NEXT: s_endpgm1887;1888; VI-LABEL: s_shl_inline_imm_f32_4_0_i64:1889; VI: ; %bb.0:1890; VI-NEXT: s_load_dword s6, s[4:5], 0x341891; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x241892; VI-NEXT: s_mov_b32 s3, 0xf0001893; VI-NEXT: s_mov_b32 s2, -11894; VI-NEXT: s_waitcnt lgkmcnt(0)1895; VI-NEXT: s_lshl_b64 s[4:5], 0x40800000, s61896; VI-NEXT: v_mov_b32_e32 v0, s41897; VI-NEXT: v_mov_b32_e32 v1, s51898; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 01899; VI-NEXT: s_endpgm1900;1901; EG-LABEL: s_shl_inline_imm_f32_4_0_i64:1902; EG: ; %bb.0:1903; EG-NEXT: ALU 11, @4, KC0[CB0:0-32], KC1[]1904; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 11905; EG-NEXT: CF_END1906; EG-NEXT: PAD1907; EG-NEXT: ALU clause starting at 4:1908; EG-NEXT: AND_INT T0.W, KC0[2].W, literal.x,1909; EG-NEXT: NOT_INT * T1.W, KC0[2].W,1910; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)1911; EG-NEXT: BIT_ALIGN_INT T0.Z, 0.0, literal.x, PS,1912; EG-NEXT: AND_INT T1.W, KC0[2].W, literal.y,1913; EG-NEXT: LSHL * T0.W, literal.z, PV.W,1914; EG-NEXT: 541065216(1.626303e-19), 32(4.484155e-44)1915; EG-NEXT: 1082130432(4.000000e+00), 0(0.000000e+00)1916; EG-NEXT: CNDE_INT * T0.Y, PV.W, PV.Z, PS,1917; EG-NEXT: CNDE_INT T0.X, T1.W, T0.W, 0.0,1918; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1919; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1920 %shl = shl i64 1082130432, %a1921 store i64 %shl, ptr addrspace(1) %out, align 81922 ret void1923}1924 1925; FIXME: Copy of -1 register1926define amdgpu_kernel void @s_shl_inline_imm_f32_neg_4_0_i64(ptr addrspace(1) %out, ptr addrspace(1) %aptr, i64 %a) {1927; SI-LABEL: s_shl_inline_imm_f32_neg_4_0_i64:1928; SI: ; %bb.0:1929; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x91930; SI-NEXT: s_load_dword s6, s[4:5], 0xd1931; SI-NEXT: s_mov_b32 s4, -4.01932; SI-NEXT: s_mov_b32 s5, -11933; SI-NEXT: s_mov_b32 s3, 0xf0001934; SI-NEXT: s_mov_b32 s2, -11935; SI-NEXT: s_waitcnt lgkmcnt(0)1936; SI-NEXT: s_lshl_b64 s[4:5], s[4:5], s61937; SI-NEXT: v_mov_b32_e32 v0, s41938; SI-NEXT: v_mov_b32_e32 v1, s51939; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 01940; SI-NEXT: s_endpgm1941;1942; VI-LABEL: s_shl_inline_imm_f32_neg_4_0_i64:1943; VI: ; %bb.0:1944; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x241945; VI-NEXT: s_load_dword s6, s[4:5], 0x341946; VI-NEXT: s_mov_b32 s4, -4.01947; VI-NEXT: s_mov_b32 s5, -11948; VI-NEXT: s_mov_b32 s3, 0xf0001949; VI-NEXT: s_mov_b32 s2, -11950; VI-NEXT: s_waitcnt lgkmcnt(0)1951; VI-NEXT: s_lshl_b64 s[4:5], s[4:5], s61952; VI-NEXT: v_mov_b32_e32 v0, s41953; VI-NEXT: v_mov_b32_e32 v1, s51954; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 01955; VI-NEXT: s_endpgm1956;1957; EG-LABEL: s_shl_inline_imm_f32_neg_4_0_i64:1958; EG: ; %bb.0:1959; EG-NEXT: ALU 12, @4, KC0[CB0:0-32], KC1[]1960; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 11961; EG-NEXT: CF_END1962; EG-NEXT: PAD1963; EG-NEXT: ALU clause starting at 4:1964; EG-NEXT: MOV T0.Z, literal.x,1965; EG-NEXT: NOT_INT T0.W, KC0[2].W,1966; EG-NEXT: AND_INT * T1.W, KC0[2].W, literal.y,1967; EG-NEXT: -532676608(-5.534023e+19), 31(4.344025e-44)1968; EG-NEXT: LSHL T1.Z, literal.x, PS,1969; EG-NEXT: BIT_ALIGN_INT T0.W, literal.y, PV.Z, PV.W,1970; EG-NEXT: AND_INT * T1.W, KC0[2].W, literal.z,1971; EG-NEXT: -1065353216(-4.000000e+00), 2147483647(nan)1972; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)1973; EG-NEXT: CNDE_INT * T0.Y, PS, PV.W, PV.Z,1974; EG-NEXT: CNDE_INT T0.X, T1.W, T1.Z, 0.0,1975; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1976; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1977 %shl = shl i64 -1065353216, %a1978 store i64 %shl, ptr addrspace(1) %out, align 81979 ret void1980}1981 1982define amdgpu_kernel void @s_shl_inline_high_imm_f32_4_0_i64(ptr addrspace(1) %out, ptr addrspace(1) %aptr, i64 %a) {1983; SI-LABEL: s_shl_inline_high_imm_f32_4_0_i64:1984; SI: ; %bb.0:1985; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x91986; SI-NEXT: s_load_dword s6, s[4:5], 0xd1987; SI-NEXT: s_mov_b32 s4, 01988; SI-NEXT: s_mov_b32 s5, 4.01989; SI-NEXT: s_mov_b32 s3, 0xf0001990; SI-NEXT: s_mov_b32 s2, -11991; SI-NEXT: s_waitcnt lgkmcnt(0)1992; SI-NEXT: s_lshl_b64 s[4:5], s[4:5], s61993; SI-NEXT: v_mov_b32_e32 v0, s41994; SI-NEXT: v_mov_b32_e32 v1, s51995; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 01996; SI-NEXT: s_endpgm1997;1998; VI-LABEL: s_shl_inline_high_imm_f32_4_0_i64:1999; VI: ; %bb.0:2000; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x242001; VI-NEXT: s_load_dword s6, s[4:5], 0x342002; VI-NEXT: s_mov_b32 s4, 02003; VI-NEXT: s_mov_b32 s5, 4.02004; VI-NEXT: s_mov_b32 s3, 0xf0002005; VI-NEXT: s_mov_b32 s2, -12006; VI-NEXT: s_waitcnt lgkmcnt(0)2007; VI-NEXT: s_lshl_b64 s[4:5], s[4:5], s62008; VI-NEXT: v_mov_b32_e32 v0, s42009; VI-NEXT: v_mov_b32_e32 v1, s52010; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 02011; VI-NEXT: s_endpgm2012;2013; EG-LABEL: s_shl_inline_high_imm_f32_4_0_i64:2014; EG: ; %bb.0:2015; EG-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[]2016; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 12017; EG-NEXT: CF_END2018; EG-NEXT: PAD2019; EG-NEXT: ALU clause starting at 4:2020; EG-NEXT: NOT_INT * T0.W, KC0[2].W,2021; EG-NEXT: BIT_ALIGN_INT T0.W, literal.x, 0.0, PV.W,2022; EG-NEXT: AND_INT * T1.W, KC0[2].W, literal.y,2023; EG-NEXT: 541065216(1.626303e-19), 32(4.484155e-44)2024; EG-NEXT: CNDE_INT * T0.Y, PS, PV.W, 0.0,2025; EG-NEXT: MOV T0.X, 0.0,2026; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,2027; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)2028 %shl = shl i64 4647714815446351872, %a2029 store i64 %shl, ptr addrspace(1) %out, align 82030 ret void2031}2032 2033define amdgpu_kernel void @s_shl_inline_high_imm_f32_neg_4_0_i64(ptr addrspace(1) %out, ptr addrspace(1) %aptr, i64 %a) {2034; SI-LABEL: s_shl_inline_high_imm_f32_neg_4_0_i64:2035; SI: ; %bb.0:2036; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x92037; SI-NEXT: s_load_dword s6, s[4:5], 0xd2038; SI-NEXT: s_mov_b32 s4, 02039; SI-NEXT: s_mov_b32 s5, -4.02040; SI-NEXT: s_mov_b32 s3, 0xf0002041; SI-NEXT: s_mov_b32 s2, -12042; SI-NEXT: s_waitcnt lgkmcnt(0)2043; SI-NEXT: s_lshl_b64 s[4:5], s[4:5], s62044; SI-NEXT: v_mov_b32_e32 v0, s42045; SI-NEXT: v_mov_b32_e32 v1, s52046; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 02047; SI-NEXT: s_endpgm2048;2049; VI-LABEL: s_shl_inline_high_imm_f32_neg_4_0_i64:2050; VI: ; %bb.0:2051; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x242052; VI-NEXT: s_load_dword s6, s[4:5], 0x342053; VI-NEXT: s_mov_b32 s4, 02054; VI-NEXT: s_mov_b32 s5, -4.02055; VI-NEXT: s_mov_b32 s3, 0xf0002056; VI-NEXT: s_mov_b32 s2, -12057; VI-NEXT: s_waitcnt lgkmcnt(0)2058; VI-NEXT: s_lshl_b64 s[4:5], s[4:5], s62059; VI-NEXT: v_mov_b32_e32 v0, s42060; VI-NEXT: v_mov_b32_e32 v1, s52061; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 02062; VI-NEXT: s_endpgm2063;2064; EG-LABEL: s_shl_inline_high_imm_f32_neg_4_0_i64:2065; EG: ; %bb.0:2066; EG-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[]2067; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 12068; EG-NEXT: CF_END2069; EG-NEXT: PAD2070; EG-NEXT: ALU clause starting at 4:2071; EG-NEXT: NOT_INT * T0.W, KC0[2].W,2072; EG-NEXT: BIT_ALIGN_INT T0.W, literal.x, 0.0, PV.W,2073; EG-NEXT: AND_INT * T1.W, KC0[2].W, literal.y,2074; EG-NEXT: 1614807040(5.534023e+19), 32(4.484155e-44)2075; EG-NEXT: CNDE_INT * T0.Y, PS, PV.W, 0.0,2076; EG-NEXT: MOV T0.X, 0.0,2077; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,2078; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)2079 %shl = shl i64 13871086852301127680, %a2080 store i64 %shl, ptr addrspace(1) %out, align 82081 ret void2082}2083 2084define amdgpu_kernel void @test_mul2(i32 %p) {2085; SI-LABEL: test_mul2:2086; SI: ; %bb.0:2087; SI-NEXT: s_load_dword s0, s[4:5], 0x92088; SI-NEXT: s_mov_b32 s3, 0xf0002089; SI-NEXT: s_mov_b32 s2, -12090; SI-NEXT: s_waitcnt lgkmcnt(0)2091; SI-NEXT: s_lshl_b32 s0, s0, 12092; SI-NEXT: v_mov_b32_e32 v0, s02093; SI-NEXT: buffer_store_dword v0, off, s[0:3], 02094; SI-NEXT: s_waitcnt vmcnt(0)2095; SI-NEXT: s_endpgm2096;2097; VI-LABEL: test_mul2:2098; VI: ; %bb.0:2099; VI-NEXT: s_load_dword s0, s[4:5], 0x242100; VI-NEXT: s_mov_b32 s3, 0xf0002101; VI-NEXT: s_mov_b32 s2, -12102; VI-NEXT: s_waitcnt lgkmcnt(0)2103; VI-NEXT: s_lshl_b32 s0, s0, 12104; VI-NEXT: v_mov_b32_e32 v0, s02105; VI-NEXT: buffer_store_dword v0, off, s[0:3], 02106; VI-NEXT: s_waitcnt vmcnt(0)2107; VI-NEXT: s_endpgm2108;2109; EG-LABEL: test_mul2:2110; EG: ; %bb.0:2111; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]2112; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 12113; EG-NEXT: CF_END2114; EG-NEXT: PAD2115; EG-NEXT: ALU clause starting at 4:2116; EG-NEXT: MOV T0.X, literal.x,2117; EG-NEXT: LSHL * T1.X, KC0[2].Y, 1,2118; EG-NEXT: 0(0.000000e+00), 0(0.000000e+00)2119 %i = mul i32 %p, 22120 store volatile i32 %i, ptr addrspace(1) poison2121 ret void2122}2123 2124define void @shl_or_k(ptr addrspace(1) %out, i32 %in) {2125; SI-LABEL: shl_or_k:2126; SI: ; %bb.0:2127; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2128; SI-NEXT: s_mov_b32 s6, 02129; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v22130; SI-NEXT: s_mov_b32 s7, 0xf0002131; SI-NEXT: s_mov_b32 s4, s62132; SI-NEXT: s_mov_b32 s5, s62133; SI-NEXT: v_or_b32_e32 v2, 4, v22134; SI-NEXT: buffer_store_dword v2, v[0:1], s[4:7], 0 addr642135; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)2136; SI-NEXT: s_setpc_b64 s[30:31]2137;2138; VI-LABEL: shl_or_k:2139; VI: ; %bb.0:2140; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2141; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v22142; VI-NEXT: v_or_b32_e32 v2, 4, v22143; VI-NEXT: flat_store_dword v[0:1], v22144; VI-NEXT: s_waitcnt vmcnt(0)2145; VI-NEXT: s_setpc_b64 s[30:31]2146;2147; EG-LABEL: shl_or_k:2148; EG: ; %bb.0:2149; EG-NEXT: ALU 4, @4, KC0[CB0:0-32], KC1[]2150; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 12151; EG-NEXT: CF_END2152; EG-NEXT: PAD2153; EG-NEXT: ALU clause starting at 4:2154; EG-NEXT: LSHL * T0.W, KC0[2].Z, literal.x,2155; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)2156; EG-NEXT: OR_INT T0.X, PV.W, literal.x,2157; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,2158; EG-NEXT: 4(5.605194e-45), 2(2.802597e-45)2159 %tmp0 = or i32 %in, 12160 %tmp2 = shl i32 %tmp0, 22161 store i32 %tmp2, ptr addrspace(1) %out2162 ret void2163}2164 2165define void @shl_or_k_two_uses(ptr addrspace(1) %out0, ptr addrspace(1) %out1, i32 %in) {2166; SI-LABEL: shl_or_k_two_uses:2167; SI: ; %bb.0:2168; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2169; SI-NEXT: s_mov_b32 s6, 02170; SI-NEXT: v_or_b32_e32 v4, 1, v42171; SI-NEXT: s_mov_b32 s7, 0xf0002172; SI-NEXT: s_mov_b32 s4, s62173; SI-NEXT: s_mov_b32 s5, s62174; SI-NEXT: v_lshlrev_b32_e32 v5, 2, v42175; SI-NEXT: buffer_store_dword v5, v[0:1], s[4:7], 0 addr642176; SI-NEXT: buffer_store_dword v4, v[2:3], s[4:7], 0 addr642177; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)2178; SI-NEXT: s_setpc_b64 s[30:31]2179;2180; VI-LABEL: shl_or_k_two_uses:2181; VI: ; %bb.0:2182; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2183; VI-NEXT: v_or_b32_e32 v4, 1, v42184; VI-NEXT: v_lshlrev_b32_e32 v5, 2, v42185; VI-NEXT: flat_store_dword v[0:1], v52186; VI-NEXT: flat_store_dword v[2:3], v42187; VI-NEXT: s_waitcnt vmcnt(0)2188; VI-NEXT: s_setpc_b64 s[30:31]2189;2190; EG-LABEL: shl_or_k_two_uses:2191; EG: ; %bb.0:2192; EG-NEXT: ALU 5, @4, KC0[CB0:0-32], KC1[]2193; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T2.X, T3.X, 02194; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 12195; EG-NEXT: CF_END2196; EG-NEXT: ALU clause starting at 4:2197; EG-NEXT: LSHR T0.X, KC0[2].Z, literal.x,2198; EG-NEXT: OR_INT * T1.X, KC0[2].W, 1,2199; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)2200; EG-NEXT: LSHL T2.X, PS, literal.x,2201; EG-NEXT: LSHR * T3.X, KC0[2].Y, literal.x,2202; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)2203 %tmp0 = or i32 %in, 12204 %tmp2 = shl i32 %tmp0, 22205 store i32 %tmp2, ptr addrspace(1) %out02206 store i32 %tmp0, ptr addrspace(1) %out12207 ret void2208}2209 2210attributes #0 = { nounwind readnone }2211