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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52;; Test reduction of:3;;4;; DST = shl i64 X, Y5;;6;; where Y is in the range [63-32] to:7;;8;; DST = [0, shl i32 X, (Y & 0x1F)]9 10; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck %s11 12;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;13; Test range with metadata14;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;15 16define i64 @shl_metadata(i64 %arg0, ptr %arg1.ptr) {17; CHECK-LABEL: shl_metadata:18; CHECK: ; %bb.0:19; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)20; CHECK-NEXT: flat_load_dword v1, v[2:3]21; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)22; CHECK-NEXT: v_lshlrev_b32_e32 v1, v1, v023; CHECK-NEXT: v_mov_b32_e32 v0, 024; CHECK-NEXT: s_setpc_b64 s[30:31]25 %shift.amt = load i64, ptr %arg1.ptr, !range !0, !noundef !{}26 %shl = shl i64 %arg0, %shift.amt27 ret i64 %shl28}29 30define i64 @shl_metadata_two_ranges(i64 %arg0, ptr %arg1.ptr) {31; CHECK-LABEL: shl_metadata_two_ranges:32; CHECK: ; %bb.0:33; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)34; CHECK-NEXT: flat_load_dword v1, v[2:3]35; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)36; CHECK-NEXT: v_lshlrev_b32_e32 v1, v1, v037; CHECK-NEXT: v_mov_b32_e32 v0, 038; CHECK-NEXT: s_setpc_b64 s[30:31]39 %shift.amt = load i64, ptr %arg1.ptr, !range !1, !noundef !{}40 %shl = shl i64 %arg0, %shift.amt41 ret i64 %shl42}43 44; Known minimum is too low. Reduction must not be done.45define i64 @shl_metadata_out_of_range(i64 %arg0, ptr %arg1.ptr) {46; CHECK-LABEL: shl_metadata_out_of_range:47; CHECK: ; %bb.0:48; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)49; CHECK-NEXT: flat_load_dword v2, v[2:3]50; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)51; CHECK-NEXT: v_lshlrev_b64 v[0:1], v2, v[0:1]52; CHECK-NEXT: s_setpc_b64 s[30:31]53 %shift.amt = load i64, ptr %arg1.ptr, !range !2, !noundef !{}54 %shl = shl i64 %arg0, %shift.amt55 ret i64 %shl56}57 58; Bounds cannot be truncated to i32 when load is narrowed to i32.59; Reduction must not be done.60; Bounds were chosen so that if bounds were truncated to i32 the61; known minimum would be 32 and the shl would be erroneously reduced.62define i64 @shl_metadata_cant_be_narrowed_to_i32(i64 %arg0, ptr %arg1.ptr) {63; CHECK-LABEL: shl_metadata_cant_be_narrowed_to_i32:64; CHECK: ; %bb.0:65; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)66; CHECK-NEXT: flat_load_dword v2, v[2:3]67; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)68; CHECK-NEXT: v_lshlrev_b64 v[0:1], v2, v[0:1]69; CHECK-NEXT: s_setpc_b64 s[30:31]70 %shift.amt = load i64, ptr %arg1.ptr, !range !3, !noundef !{}71 %shl = shl i64 %arg0, %shift.amt72 ret i64 %shl73}74 75define <2 x i64> @shl_v2_metadata(<2 x i64> %arg0, ptr %arg1.ptr) {76; CHECK-LABEL: shl_v2_metadata:77; CHECK: ; %bb.0:78; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)79; CHECK-NEXT: flat_load_dwordx4 v[3:6], v[4:5]80; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)81; CHECK-NEXT: v_lshlrev_b32_e32 v1, v3, v082; CHECK-NEXT: v_lshlrev_b32_e32 v3, v5, v283; CHECK-NEXT: v_mov_b32_e32 v0, 084; CHECK-NEXT: v_mov_b32_e32 v2, 085; CHECK-NEXT: s_setpc_b64 s[30:31]86 %shift.amt = load <2 x i64>, ptr %arg1.ptr, !range !0, !noundef !{}87 %shl = shl <2 x i64> %arg0, %shift.amt88 ret <2 x i64> %shl89}90 91define <3 x i64> @shl_v3_metadata(<3 x i64> %arg0, ptr %arg1.ptr) {92; CHECK-LABEL: shl_v3_metadata:93; CHECK: ; %bb.0:94; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)95; CHECK-NEXT: flat_load_dword v1, v[6:7] offset:1696; CHECK-NEXT: flat_load_dwordx4 v[8:11], v[6:7]97; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)98; CHECK-NEXT: v_lshlrev_b32_e32 v5, v1, v499; CHECK-NEXT: v_lshlrev_b32_e32 v1, v8, v0100; CHECK-NEXT: v_lshlrev_b32_e32 v3, v10, v2101; CHECK-NEXT: v_mov_b32_e32 v0, 0102; CHECK-NEXT: v_mov_b32_e32 v2, 0103; CHECK-NEXT: v_mov_b32_e32 v4, 0104; CHECK-NEXT: s_setpc_b64 s[30:31]105 %shift.amt = load <3 x i64>, ptr %arg1.ptr, !range !0, !noundef !{}106 %shl = shl <3 x i64> %arg0, %shift.amt107 ret <3 x i64> %shl108}109 110define <4 x i64> @shl_v4_metadata(<4 x i64> %arg0, ptr %arg1.ptr) {111; CHECK-LABEL: shl_v4_metadata:112; CHECK: ; %bb.0:113; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)114; CHECK-NEXT: flat_load_dwordx4 v[10:13], v[8:9]115; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)116; CHECK-NEXT: flat_load_dwordx4 v[13:16], v[8:9] offset:16117; CHECK-NEXT: ; kill: killed $vgpr8 killed $vgpr9118; CHECK-NEXT: v_lshlrev_b32_e32 v1, v10, v0119; CHECK-NEXT: v_lshlrev_b32_e32 v3, v12, v2120; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)121; CHECK-NEXT: v_lshlrev_b32_e32 v5, v13, v4122; CHECK-NEXT: v_lshlrev_b32_e32 v7, v15, v6123; CHECK-NEXT: v_mov_b32_e32 v0, 0124; CHECK-NEXT: v_mov_b32_e32 v2, 0125; CHECK-NEXT: v_mov_b32_e32 v4, 0126; CHECK-NEXT: v_mov_b32_e32 v6, 0127; CHECK-NEXT: s_setpc_b64 s[30:31]128 %shift.amt = load <4 x i64>, ptr %arg1.ptr, !range !0, !noundef !{}129 %shl = shl <4 x i64> %arg0, %shift.amt130 ret <4 x i64> %shl131}132 133!0 = !{i64 32, i64 64}134!1 = !{i64 32, i64 38, i64 42, i64 48}135!2 = !{i64 31, i64 38, i64 42, i64 48}136!3 = !{i64 32, i64 38, i64 2147483680, i64 2147483681}137 138;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;139; Test range with an "or X, 16"140;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;141 142; These cases must not be reduced because the known minimum, 16, is not in range.143 144define i64 @shl_or16(i64 %arg0, i64 %shift_amt) {145; CHECK-LABEL: shl_or16:146; CHECK: ; %bb.0:147; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)148; CHECK-NEXT: v_or_b32_e32 v2, 16, v2149; CHECK-NEXT: v_lshlrev_b64 v[0:1], v2, v[0:1]150; CHECK-NEXT: s_setpc_b64 s[30:31]151 %or = or i64 %shift_amt, 16152 %shl = shl i64 %arg0, %or153 ret i64 %shl154}155 156define <2 x i64> @shl_v2_or16(<2 x i64> %arg0, <2 x i64> %shift_amt) {157; CHECK-LABEL: shl_v2_or16:158; CHECK: ; %bb.0:159; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)160; CHECK-NEXT: v_or_b32_e32 v5, 16, v6161; CHECK-NEXT: v_or_b32_e32 v4, 16, v4162; CHECK-NEXT: v_lshlrev_b64 v[0:1], v4, v[0:1]163; CHECK-NEXT: v_lshlrev_b64 v[2:3], v5, v[2:3]164; CHECK-NEXT: s_setpc_b64 s[30:31]165 %or = or <2 x i64> %shift_amt, splat (i64 16)166 %shl = shl <2 x i64> %arg0, %or167 ret <2 x i64> %shl168}169 170define <3 x i64> @shl_v3_or16(<3 x i64> %arg0, <3 x i64> %shift_amt) {171; CHECK-LABEL: shl_v3_or16:172; CHECK: ; %bb.0:173; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)174; CHECK-NEXT: v_or_b32_e32 v7, 16, v10175; CHECK-NEXT: v_or_b32_e32 v8, 16, v8176; CHECK-NEXT: v_or_b32_e32 v6, 16, v6177; CHECK-NEXT: v_lshlrev_b64 v[0:1], v6, v[0:1]178; CHECK-NEXT: v_lshlrev_b64 v[2:3], v8, v[2:3]179; CHECK-NEXT: v_lshlrev_b64 v[4:5], v7, v[4:5]180; CHECK-NEXT: s_setpc_b64 s[30:31]181 %or = or <3 x i64> %shift_amt, splat (i64 16)182 %shl = shl <3 x i64> %arg0, %or183 ret <3 x i64> %shl184}185 186define <4 x i64> @shl_v4_or16(<4 x i64> %arg0, <4 x i64> %shift_amt) {187; CHECK-LABEL: shl_v4_or16:188; CHECK: ; %bb.0:189; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)190; CHECK-NEXT: v_or_b32_e32 v9, 16, v14191; CHECK-NEXT: v_or_b32_e32 v11, 16, v12192; CHECK-NEXT: v_or_b32_e32 v10, 16, v10193; CHECK-NEXT: v_or_b32_e32 v8, 16, v8194; CHECK-NEXT: v_lshlrev_b64 v[0:1], v8, v[0:1]195; CHECK-NEXT: v_lshlrev_b64 v[2:3], v10, v[2:3]196; CHECK-NEXT: v_lshlrev_b64 v[4:5], v11, v[4:5]197; CHECK-NEXT: v_lshlrev_b64 v[6:7], v9, v[6:7]198; CHECK-NEXT: s_setpc_b64 s[30:31]199 %or = or <4 x i64> %shift_amt, splat (i64 16)200 %shl = shl <4 x i64> %arg0, %or201 ret <4 x i64> %shl202}203 204; test SGPR205 206define i64 @shl_or16_sgpr(i64 inreg %arg0, i64 inreg %shift_amt) {207; CHECK-LABEL: shl_or16_sgpr:208; CHECK: ; %bb.0:209; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)210; CHECK-NEXT: s_or_b32 s4, s18, 16211; CHECK-NEXT: s_lshl_b64 s[4:5], s[16:17], s4212; CHECK-NEXT: v_mov_b32_e32 v0, s4213; CHECK-NEXT: v_mov_b32_e32 v1, s5214; CHECK-NEXT: s_setpc_b64 s[30:31]215 %or = or i64 %shift_amt, 16216 %shl = shl i64 %arg0, %or217 ret i64 %shl218}219 220define <2 x i64> @shl_v2_or16_sgpr(<2 x i64> inreg %arg0, <2 x i64> inreg %shift_amt) {221; CHECK-LABEL: shl_v2_or16_sgpr:222; CHECK: ; %bb.0:223; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)224; CHECK-NEXT: s_or_b32 s6, s22, 16225; CHECK-NEXT: s_or_b32 s4, s20, 16226; CHECK-NEXT: s_lshl_b64 s[4:5], s[16:17], s4227; CHECK-NEXT: s_lshl_b64 s[6:7], s[18:19], s6228; CHECK-NEXT: v_mov_b32_e32 v0, s4229; CHECK-NEXT: v_mov_b32_e32 v1, s5230; CHECK-NEXT: v_mov_b32_e32 v2, s6231; CHECK-NEXT: v_mov_b32_e32 v3, s7232; CHECK-NEXT: s_setpc_b64 s[30:31]233 %or = or <2 x i64> %shift_amt, splat (i64 16)234 %shl = shl <2 x i64> %arg0, %or235 ret <2 x i64> %shl236}237 238define <3 x i64> @shl_v3_or16_sgpr(<3 x i64> inreg %arg0, <3 x i64> inreg %shift_amt) {239; CHECK-LABEL: shl_v3_or16_sgpr:240; CHECK: ; %bb.0:241; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)242; CHECK-NEXT: s_or_b32 s8, s26, 16243; CHECK-NEXT: s_or_b32 s6, s24, 16244; CHECK-NEXT: s_or_b32 s4, s22, 16245; CHECK-NEXT: s_lshl_b64 s[4:5], s[16:17], s4246; CHECK-NEXT: s_lshl_b64 s[6:7], s[18:19], s6247; CHECK-NEXT: s_lshl_b64 s[8:9], s[20:21], s8248; CHECK-NEXT: v_mov_b32_e32 v0, s4249; CHECK-NEXT: v_mov_b32_e32 v1, s5250; CHECK-NEXT: v_mov_b32_e32 v2, s6251; CHECK-NEXT: v_mov_b32_e32 v3, s7252; CHECK-NEXT: v_mov_b32_e32 v4, s8253; CHECK-NEXT: v_mov_b32_e32 v5, s9254; CHECK-NEXT: s_setpc_b64 s[30:31]255 %or = or <3 x i64> %shift_amt, splat (i64 16)256 %shl = shl <3 x i64> %arg0, %or257 ret <3 x i64> %shl258}259 260define <4 x i64> @shl_v4_or16_sgpr(<4 x i64> inreg %arg0, <4 x i64> inreg %shift_amt) {261; CHECK-LABEL: shl_v4_or16_sgpr:262; CHECK: ; %bb.0:263; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)264; CHECK-NEXT: v_or_b32_e32 v0, 16, v0265; CHECK-NEXT: s_or_b32 s8, s28, 16266; CHECK-NEXT: s_or_b32 s6, s26, 16267; CHECK-NEXT: s_or_b32 s4, s24, 16268; CHECK-NEXT: s_lshl_b64 s[4:5], s[16:17], s4269; CHECK-NEXT: s_lshl_b64 s[6:7], s[18:19], s6270; CHECK-NEXT: s_lshl_b64 s[8:9], s[20:21], s8271; CHECK-NEXT: v_lshlrev_b64 v[6:7], v0, s[22:23]272; CHECK-NEXT: v_mov_b32_e32 v0, s4273; CHECK-NEXT: v_mov_b32_e32 v1, s5274; CHECK-NEXT: v_mov_b32_e32 v2, s6275; CHECK-NEXT: v_mov_b32_e32 v3, s7276; CHECK-NEXT: v_mov_b32_e32 v4, s8277; CHECK-NEXT: v_mov_b32_e32 v5, s9278; CHECK-NEXT: s_setpc_b64 s[30:31]279 %or = or <4 x i64> %shift_amt, splat (i64 16)280 %shl = shl <4 x i64> %arg0, %or281 ret <4 x i64> %shl282}283 284;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;285; Test range with an "or X, 32"286;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;287 288; These cases are reduced because computeKnownBits() can calculate a minimum of 32289; based on the OR with 32.290 291define i64 @shl_or32(i64 %arg0, i64 %shift_amt) {292; CHECK-LABEL: shl_or32:293; CHECK: ; %bb.0:294; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)295; CHECK-NEXT: v_lshlrev_b32_e32 v1, v2, v0296; CHECK-NEXT: v_mov_b32_e32 v0, 0297; CHECK-NEXT: s_setpc_b64 s[30:31]298 %or = or i64 %shift_amt, 32299 %shl = shl i64 %arg0, %or300 ret i64 %shl301}302 303define <2 x i64> @shl_v2_or32(<2 x i64> %arg0, <2 x i64> %shift_amt) {304; CHECK-LABEL: shl_v2_or32:305; CHECK: ; %bb.0:306; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)307; CHECK-NEXT: v_lshlrev_b32_e32 v1, v4, v0308; CHECK-NEXT: v_lshlrev_b32_e32 v3, v6, v2309; CHECK-NEXT: v_mov_b32_e32 v0, 0310; CHECK-NEXT: v_mov_b32_e32 v2, 0311; CHECK-NEXT: s_setpc_b64 s[30:31]312 %or = or <2 x i64> %shift_amt, splat (i64 32)313 %shl = shl <2 x i64> %arg0, %or314 ret <2 x i64> %shl315}316 317define <3 x i64> @shl_v3_or32(<3 x i64> %arg0, <3 x i64> %shift_amt) {318; CHECK-LABEL: shl_v3_or32:319; CHECK: ; %bb.0:320; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)321; CHECK-NEXT: v_lshlrev_b32_e32 v1, v6, v0322; CHECK-NEXT: v_lshlrev_b32_e32 v3, v8, v2323; CHECK-NEXT: v_lshlrev_b32_e32 v5, v10, v4324; CHECK-NEXT: v_mov_b32_e32 v0, 0325; CHECK-NEXT: v_mov_b32_e32 v2, 0326; CHECK-NEXT: v_mov_b32_e32 v4, 0327; CHECK-NEXT: s_setpc_b64 s[30:31]328 %or = or <3 x i64> %shift_amt, splat (i64 32)329 %shl = shl <3 x i64> %arg0, %or330 ret <3 x i64> %shl331}332 333define <4 x i64> @shl_v4_or32(<4 x i64> %arg0, <4 x i64> %shift_amt) {334; CHECK-LABEL: shl_v4_or32:335; CHECK: ; %bb.0:336; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)337; CHECK-NEXT: v_lshlrev_b32_e32 v1, v8, v0338; CHECK-NEXT: v_lshlrev_b32_e32 v3, v10, v2339; CHECK-NEXT: v_lshlrev_b32_e32 v5, v12, v4340; CHECK-NEXT: v_lshlrev_b32_e32 v7, v14, v6341; CHECK-NEXT: v_mov_b32_e32 v0, 0342; CHECK-NEXT: v_mov_b32_e32 v2, 0343; CHECK-NEXT: v_mov_b32_e32 v4, 0344; CHECK-NEXT: v_mov_b32_e32 v6, 0345; CHECK-NEXT: s_setpc_b64 s[30:31]346 %or = or <4 x i64> %shift_amt, splat (i64 32)347 %shl = shl <4 x i64> %arg0, %or348 ret <4 x i64> %shl349}350 351; test SGPR352 353define i64 @shl_or32_sgpr(i64 inreg %arg0, i64 inreg %shift_amt) {354; CHECK-LABEL: shl_or32_sgpr:355; CHECK: ; %bb.0:356; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)357; CHECK-NEXT: s_lshl_b32 s4, s16, s18358; CHECK-NEXT: v_mov_b32_e32 v0, 0359; CHECK-NEXT: v_mov_b32_e32 v1, s4360; CHECK-NEXT: s_setpc_b64 s[30:31]361 %or = or i64 %shift_amt, 32362 %shl = shl i64 %arg0, %or363 ret i64 %shl364}365 366define <2 x i64> @shl_v2_or32_sgpr(<2 x i64> inreg %arg0, <2 x i64> inreg %shift_amt) {367; CHECK-LABEL: shl_v2_or32_sgpr:368; CHECK: ; %bb.0:369; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)370; CHECK-NEXT: s_lshl_b32 s4, s16, s20371; CHECK-NEXT: s_lshl_b32 s5, s18, s22372; CHECK-NEXT: v_mov_b32_e32 v0, 0373; CHECK-NEXT: v_mov_b32_e32 v1, s4374; CHECK-NEXT: v_mov_b32_e32 v2, 0375; CHECK-NEXT: v_mov_b32_e32 v3, s5376; CHECK-NEXT: s_setpc_b64 s[30:31]377 %or = or <2 x i64> %shift_amt, splat (i64 32)378 %shl = shl <2 x i64> %arg0, %or379 ret <2 x i64> %shl380}381 382define <3 x i64> @shl_v3_or32_sgpr(<3 x i64> inreg %arg0, <3 x i64> inreg %shift_amt) {383; CHECK-LABEL: shl_v3_or32_sgpr:384; CHECK: ; %bb.0:385; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)386; CHECK-NEXT: s_lshl_b32 s4, s16, s22387; CHECK-NEXT: s_lshl_b32 s5, s18, s24388; CHECK-NEXT: s_lshl_b32 s6, s20, s26389; CHECK-NEXT: v_mov_b32_e32 v0, 0390; CHECK-NEXT: v_mov_b32_e32 v1, s4391; CHECK-NEXT: v_mov_b32_e32 v2, 0392; CHECK-NEXT: v_mov_b32_e32 v3, s5393; CHECK-NEXT: v_mov_b32_e32 v4, 0394; CHECK-NEXT: v_mov_b32_e32 v5, s6395; CHECK-NEXT: s_setpc_b64 s[30:31]396 %or = or <3 x i64> %shift_amt, splat (i64 32)397 %shl = shl <3 x i64> %arg0, %or398 ret <3 x i64> %shl399}400 401define <4 x i64> @shl_v4_or32_sgpr(<4 x i64> inreg %arg0, <4 x i64> inreg %shift_amt) {402; CHECK-LABEL: shl_v4_or32_sgpr:403; CHECK: ; %bb.0:404; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)405; CHECK-NEXT: s_lshl_b32 s4, s16, s24406; CHECK-NEXT: s_lshl_b32 s5, s18, s26407; CHECK-NEXT: s_lshl_b32 s6, s20, s28408; CHECK-NEXT: v_lshlrev_b32_e64 v7, v0, s22409; CHECK-NEXT: v_mov_b32_e32 v0, 0410; CHECK-NEXT: v_mov_b32_e32 v1, s4411; CHECK-NEXT: v_mov_b32_e32 v2, 0412; CHECK-NEXT: v_mov_b32_e32 v3, s5413; CHECK-NEXT: v_mov_b32_e32 v4, 0414; CHECK-NEXT: v_mov_b32_e32 v5, s6415; CHECK-NEXT: v_mov_b32_e32 v6, 0416; CHECK-NEXT: s_setpc_b64 s[30:31]417 %or = or <4 x i64> %shift_amt, splat (i64 32)418 %shl = shl <4 x i64> %arg0, %or419 ret <4 x i64> %shl420}421 422;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;423; Test range from max/min424;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;425 426; FIXME: This case should be reduced too, but computeKnownBits() cannot427; determine the range. Match current results for now.428 429define i64 @shl_maxmin(i64 %arg0, i64 noundef %arg1) {430; CHECK-LABEL: shl_maxmin:431; CHECK: ; %bb.0:432; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)433; CHECK-NEXT: v_cmp_lt_u64_e32 vcc, 32, v[2:3]434; CHECK-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc435; CHECK-NEXT: v_cndmask_b32_e32 v2, 32, v2, vcc436; CHECK-NEXT: v_cmp_gt_u64_e32 vcc, 63, v[2:3]437; CHECK-NEXT: v_cndmask_b32_e32 v2, 63, v2, vcc438; CHECK-NEXT: v_lshlrev_b64 v[0:1], v2, v[0:1]439; CHECK-NEXT: s_setpc_b64 s[30:31]440 %max = call i64 @llvm.umax.i64(i64 %arg1, i64 32)441 %min = call i64 @llvm.umin.i64(i64 %max, i64 63)442 %shl = shl i64 %arg0, %min443 ret i64 %shl444}445 446define <2 x i64> @shl_v2_maxmin(<2 x i64> %arg0, <2 x i64> noundef %arg1) {447; CHECK-LABEL: shl_v2_maxmin:448; CHECK: ; %bb.0:449; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)450; CHECK-NEXT: v_cmp_lt_u64_e32 vcc, 32, v[4:5]451; CHECK-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc452; CHECK-NEXT: v_cndmask_b32_e32 v4, 32, v4, vcc453; CHECK-NEXT: v_cmp_lt_u64_e32 vcc, 32, v[6:7]454; CHECK-NEXT: v_cndmask_b32_e32 v7, 0, v7, vcc455; CHECK-NEXT: v_cndmask_b32_e32 v6, 32, v6, vcc456; CHECK-NEXT: v_cmp_gt_u64_e32 vcc, 63, v[6:7]457; CHECK-NEXT: v_cndmask_b32_e32 v6, 63, v6, vcc458; CHECK-NEXT: v_cmp_gt_u64_e32 vcc, 63, v[4:5]459; CHECK-NEXT: v_lshlrev_b64 v[2:3], v6, v[2:3]460; CHECK-NEXT: v_cndmask_b32_e32 v4, 63, v4, vcc461; CHECK-NEXT: v_lshlrev_b64 v[0:1], v4, v[0:1]462; CHECK-NEXT: s_setpc_b64 s[30:31]463 %max = call <2 x i64> @llvm.umax.i64(<2 x i64> %arg1, <2 x i64> splat (i64 32))464 %min = call <2 x i64> @llvm.umin.i64(<2 x i64> %max, <2 x i64> splat (i64 63))465 %shl = shl <2 x i64> %arg0, %min466 ret <2 x i64> %shl467}468 469define <3 x i64> @shl_v3_maxmin(<3 x i64> %arg0, <3 x i64> noundef %arg1) {470; CHECK-LABEL: shl_v3_maxmin:471; CHECK: ; %bb.0:472; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)473; CHECK-NEXT: v_cmp_lt_u64_e32 vcc, 32, v[6:7]474; CHECK-NEXT: v_cndmask_b32_e32 v7, 0, v7, vcc475; CHECK-NEXT: v_cndmask_b32_e32 v6, 32, v6, vcc476; CHECK-NEXT: v_cmp_lt_u64_e32 vcc, 32, v[8:9]477; CHECK-NEXT: v_cndmask_b32_e32 v9, 0, v9, vcc478; CHECK-NEXT: v_cndmask_b32_e32 v8, 32, v8, vcc479; CHECK-NEXT: v_cmp_lt_u64_e32 vcc, 32, v[10:11]480; CHECK-NEXT: v_cndmask_b32_e32 v11, 0, v11, vcc481; CHECK-NEXT: v_cndmask_b32_e32 v10, 32, v10, vcc482; CHECK-NEXT: v_cmp_gt_u64_e32 vcc, 63, v[10:11]483; CHECK-NEXT: v_cndmask_b32_e32 v10, 63, v10, vcc484; CHECK-NEXT: v_cmp_gt_u64_e32 vcc, 63, v[8:9]485; CHECK-NEXT: v_lshlrev_b64 v[4:5], v10, v[4:5]486; CHECK-NEXT: v_cndmask_b32_e32 v8, 63, v8, vcc487; CHECK-NEXT: v_cmp_gt_u64_e32 vcc, 63, v[6:7]488; CHECK-NEXT: v_lshlrev_b64 v[2:3], v8, v[2:3]489; CHECK-NEXT: v_cndmask_b32_e32 v6, 63, v6, vcc490; CHECK-NEXT: v_lshlrev_b64 v[0:1], v6, v[0:1]491; CHECK-NEXT: s_setpc_b64 s[30:31]492 %max = call <3 x i64> @llvm.umax.i64(<3 x i64> %arg1, <3 x i64> splat (i64 32))493 %min = call <3 x i64> @llvm.umin.i64(<3 x i64> %max, <3 x i64> splat (i64 63))494 %shl = shl <3 x i64> %arg0, %min495 ret <3 x i64> %shl496}497 498define <4 x i64> @shl_v4_maxmin(<4 x i64> %arg0, <4 x i64> noundef %arg1) {499; CHECK-LABEL: shl_v4_maxmin:500; CHECK: ; %bb.0:501; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)502; CHECK-NEXT: v_cmp_lt_u64_e32 vcc, 32, v[8:9]503; CHECK-NEXT: v_cndmask_b32_e32 v9, 0, v9, vcc504; CHECK-NEXT: v_cndmask_b32_e32 v8, 32, v8, vcc505; CHECK-NEXT: v_cmp_lt_u64_e32 vcc, 32, v[10:11]506; CHECK-NEXT: v_cndmask_b32_e32 v11, 0, v11, vcc507; CHECK-NEXT: v_cndmask_b32_e32 v10, 32, v10, vcc508; CHECK-NEXT: v_cmp_lt_u64_e32 vcc, 32, v[12:13]509; CHECK-NEXT: v_cndmask_b32_e32 v13, 0, v13, vcc510; CHECK-NEXT: v_cndmask_b32_e32 v12, 32, v12, vcc511; CHECK-NEXT: v_cmp_lt_u64_e32 vcc, 32, v[14:15]512; CHECK-NEXT: v_cndmask_b32_e32 v15, 0, v15, vcc513; CHECK-NEXT: v_cndmask_b32_e32 v14, 32, v14, vcc514; CHECK-NEXT: v_cmp_gt_u64_e32 vcc, 63, v[14:15]515; CHECK-NEXT: v_cndmask_b32_e32 v14, 63, v14, vcc516; CHECK-NEXT: v_cmp_gt_u64_e32 vcc, 63, v[12:13]517; CHECK-NEXT: v_lshlrev_b64 v[6:7], v14, v[6:7]518; CHECK-NEXT: v_cndmask_b32_e32 v12, 63, v12, vcc519; CHECK-NEXT: v_cmp_gt_u64_e32 vcc, 63, v[10:11]520; CHECK-NEXT: v_lshlrev_b64 v[4:5], v12, v[4:5]521; CHECK-NEXT: v_cndmask_b32_e32 v10, 63, v10, vcc522; CHECK-NEXT: v_cmp_gt_u64_e32 vcc, 63, v[8:9]523; CHECK-NEXT: v_lshlrev_b64 v[2:3], v10, v[2:3]524; CHECK-NEXT: v_cndmask_b32_e32 v8, 63, v8, vcc525; CHECK-NEXT: v_lshlrev_b64 v[0:1], v8, v[0:1]526; CHECK-NEXT: s_setpc_b64 s[30:31]527 %max = call <4 x i64> @llvm.umax.i64(<4 x i64> %arg1, <4 x i64> splat (i64 32))528 %min = call <4 x i64> @llvm.umin.i64(<4 x i64> %max, <4 x i64> splat (i64 63))529 %shl = shl <4 x i64> %arg0, %min530 ret <4 x i64> %shl531}532