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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9-SDAG %s3; RUN: llc -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,GFX8-SDAG %s4; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GCN,GFX10-SDAG %s5; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GCN,GFX10-SDAG %s6 7; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s8; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,GFX8 %s9; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GCN,GFX10 %s10; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GCN,GFX10 %s11 12; Test gfx9+ s_shl[1-4]_add_u32 pattern matching13 14define amdgpu_ps i32 @s_shl1_add_u32(i32 inreg %src0, i32 inreg %src1) {15; GFX9-SDAG-LABEL: s_shl1_add_u32:16; GFX9-SDAG: ; %bb.0:17; GFX9-SDAG-NEXT: s_lshl1_add_u32 s0, s0, s118; GFX9-SDAG-NEXT: ; return to shader part epilog19;20; GFX8-SDAG-LABEL: s_shl1_add_u32:21; GFX8-SDAG: ; %bb.0:22; GFX8-SDAG-NEXT: s_lshl_b32 s0, s0, 123; GFX8-SDAG-NEXT: s_add_i32 s0, s0, s124; GFX8-SDAG-NEXT: ; return to shader part epilog25;26; GFX10-SDAG-LABEL: s_shl1_add_u32:27; GFX10-SDAG: ; %bb.0:28; GFX10-SDAG-NEXT: s_lshl1_add_u32 s0, s0, s129; GFX10-SDAG-NEXT: ; return to shader part epilog30;31; GFX9-LABEL: s_shl1_add_u32:32; GFX9: ; %bb.0:33; GFX9-NEXT: s_lshl1_add_u32 s0, s0, s134; GFX9-NEXT: ; return to shader part epilog35;36; GFX8-LABEL: s_shl1_add_u32:37; GFX8: ; %bb.0:38; GFX8-NEXT: s_lshl_b32 s0, s0, 139; GFX8-NEXT: s_add_i32 s0, s0, s140; GFX8-NEXT: ; return to shader part epilog41;42; GFX10-LABEL: s_shl1_add_u32:43; GFX10: ; %bb.0:44; GFX10-NEXT: s_lshl1_add_u32 s0, s0, s145; GFX10-NEXT: ; return to shader part epilog46 %shl = shl i32 %src0, 147 %add = add i32 %shl, %src148 ret i32 %add49}50 51define amdgpu_ps i32 @s_shl2_add_u32(i32 inreg %src0, i32 inreg %src1) {52; GFX9-SDAG-LABEL: s_shl2_add_u32:53; GFX9-SDAG: ; %bb.0:54; GFX9-SDAG-NEXT: s_lshl2_add_u32 s0, s0, s155; GFX9-SDAG-NEXT: ; return to shader part epilog56;57; GFX8-SDAG-LABEL: s_shl2_add_u32:58; GFX8-SDAG: ; %bb.0:59; GFX8-SDAG-NEXT: s_lshl_b32 s0, s0, 260; GFX8-SDAG-NEXT: s_add_i32 s0, s0, s161; GFX8-SDAG-NEXT: ; return to shader part epilog62;63; GFX10-SDAG-LABEL: s_shl2_add_u32:64; GFX10-SDAG: ; %bb.0:65; GFX10-SDAG-NEXT: s_lshl2_add_u32 s0, s0, s166; GFX10-SDAG-NEXT: ; return to shader part epilog67;68; GFX9-LABEL: s_shl2_add_u32:69; GFX9: ; %bb.0:70; GFX9-NEXT: s_lshl2_add_u32 s0, s0, s171; GFX9-NEXT: ; return to shader part epilog72;73; GFX8-LABEL: s_shl2_add_u32:74; GFX8: ; %bb.0:75; GFX8-NEXT: s_lshl_b32 s0, s0, 276; GFX8-NEXT: s_add_i32 s0, s0, s177; GFX8-NEXT: ; return to shader part epilog78;79; GFX10-LABEL: s_shl2_add_u32:80; GFX10: ; %bb.0:81; GFX10-NEXT: s_lshl2_add_u32 s0, s0, s182; GFX10-NEXT: ; return to shader part epilog83 %shl = shl i32 %src0, 284 %add = add i32 %shl, %src185 ret i32 %add86}87 88define amdgpu_ps i32 @s_shl3_add_u32(i32 inreg %src0, i32 inreg %src1) {89; GFX9-SDAG-LABEL: s_shl3_add_u32:90; GFX9-SDAG: ; %bb.0:91; GFX9-SDAG-NEXT: s_lshl3_add_u32 s0, s0, s192; GFX9-SDAG-NEXT: ; return to shader part epilog93;94; GFX8-SDAG-LABEL: s_shl3_add_u32:95; GFX8-SDAG: ; %bb.0:96; GFX8-SDAG-NEXT: s_lshl_b32 s0, s0, 397; GFX8-SDAG-NEXT: s_add_i32 s0, s0, s198; GFX8-SDAG-NEXT: ; return to shader part epilog99;100; GFX10-SDAG-LABEL: s_shl3_add_u32:101; GFX10-SDAG: ; %bb.0:102; GFX10-SDAG-NEXT: s_lshl3_add_u32 s0, s0, s1103; GFX10-SDAG-NEXT: ; return to shader part epilog104;105; GFX9-LABEL: s_shl3_add_u32:106; GFX9: ; %bb.0:107; GFX9-NEXT: s_lshl3_add_u32 s0, s0, s1108; GFX9-NEXT: ; return to shader part epilog109;110; GFX8-LABEL: s_shl3_add_u32:111; GFX8: ; %bb.0:112; GFX8-NEXT: s_lshl_b32 s0, s0, 3113; GFX8-NEXT: s_add_i32 s0, s0, s1114; GFX8-NEXT: ; return to shader part epilog115;116; GFX10-LABEL: s_shl3_add_u32:117; GFX10: ; %bb.0:118; GFX10-NEXT: s_lshl3_add_u32 s0, s0, s1119; GFX10-NEXT: ; return to shader part epilog120 %shl = shl i32 %src0, 3121 %add = add i32 %shl, %src1122 ret i32 %add123}124 125define amdgpu_ps i32 @s_shl4_add_u32(i32 inreg %src0, i32 inreg %src1) {126; GFX9-SDAG-LABEL: s_shl4_add_u32:127; GFX9-SDAG: ; %bb.0:128; GFX9-SDAG-NEXT: s_lshl4_add_u32 s0, s0, s1129; GFX9-SDAG-NEXT: ; return to shader part epilog130;131; GFX8-SDAG-LABEL: s_shl4_add_u32:132; GFX8-SDAG: ; %bb.0:133; GFX8-SDAG-NEXT: s_lshl_b32 s0, s0, 4134; GFX8-SDAG-NEXT: s_add_i32 s0, s0, s1135; GFX8-SDAG-NEXT: ; return to shader part epilog136;137; GFX10-SDAG-LABEL: s_shl4_add_u32:138; GFX10-SDAG: ; %bb.0:139; GFX10-SDAG-NEXT: s_lshl4_add_u32 s0, s0, s1140; GFX10-SDAG-NEXT: ; return to shader part epilog141;142; GFX9-LABEL: s_shl4_add_u32:143; GFX9: ; %bb.0:144; GFX9-NEXT: s_lshl4_add_u32 s0, s0, s1145; GFX9-NEXT: ; return to shader part epilog146;147; GFX8-LABEL: s_shl4_add_u32:148; GFX8: ; %bb.0:149; GFX8-NEXT: s_lshl_b32 s0, s0, 4150; GFX8-NEXT: s_add_i32 s0, s0, s1151; GFX8-NEXT: ; return to shader part epilog152;153; GFX10-LABEL: s_shl4_add_u32:154; GFX10: ; %bb.0:155; GFX10-NEXT: s_lshl4_add_u32 s0, s0, s1156; GFX10-NEXT: ; return to shader part epilog157 %shl = shl i32 %src0, 4158 %add = add i32 %shl, %src1159 ret i32 %add160}161 162define amdgpu_ps i32 @s_shl5_add_u32(i32 inreg %src0, i32 inreg %src1) {163; GCN-LABEL: s_shl5_add_u32:164; GCN: ; %bb.0:165; GCN-NEXT: s_lshl_b32 s0, s0, 5166; GCN-NEXT: s_add_i32 s0, s0, s1167; GCN-NEXT: ; return to shader part epilog168 %shl = shl i32 %src0, 5169 %add = add i32 %shl, %src1170 ret i32 %add171}172 173define i32 @v_shl1_add_u32(i32 %src0, i32 %src1) {174; GFX9-SDAG-LABEL: v_shl1_add_u32:175; GFX9-SDAG: ; %bb.0:176; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)177; GFX9-SDAG-NEXT: v_lshl_add_u32 v0, v0, 1, v1178; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]179;180; GFX8-SDAG-LABEL: v_shl1_add_u32:181; GFX8-SDAG: ; %bb.0:182; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)183; GFX8-SDAG-NEXT: v_lshlrev_b32_e32 v0, 1, v0184; GFX8-SDAG-NEXT: v_add_u32_e32 v0, vcc, v0, v1185; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]186;187; GFX10-SDAG-LABEL: v_shl1_add_u32:188; GFX10-SDAG: ; %bb.0:189; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)190; GFX10-SDAG-NEXT: v_lshl_add_u32 v0, v0, 1, v1191; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]192;193; GFX9-LABEL: v_shl1_add_u32:194; GFX9: ; %bb.0:195; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)196; GFX9-NEXT: v_lshl_add_u32 v0, v0, 1, v1197; GFX9-NEXT: s_setpc_b64 s[30:31]198;199; GFX8-LABEL: v_shl1_add_u32:200; GFX8: ; %bb.0:201; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)202; GFX8-NEXT: v_lshlrev_b32_e32 v0, 1, v0203; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v1204; GFX8-NEXT: s_setpc_b64 s[30:31]205;206; GFX10-LABEL: v_shl1_add_u32:207; GFX10: ; %bb.0:208; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)209; GFX10-NEXT: v_lshl_add_u32 v0, v0, 1, v1210; GFX10-NEXT: s_setpc_b64 s[30:31]211 %shl = shl i32 %src0, 1212 %add = add i32 %shl, %src1213 ret i32 %add214}215 216define i32 @v_shl2_add_u32(i32 %src0, i32 %src1) {217; GFX9-SDAG-LABEL: v_shl2_add_u32:218; GFX9-SDAG: ; %bb.0:219; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)220; GFX9-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, v1221; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]222;223; GFX8-SDAG-LABEL: v_shl2_add_u32:224; GFX8-SDAG: ; %bb.0:225; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)226; GFX8-SDAG-NEXT: v_lshlrev_b32_e32 v0, 2, v0227; GFX8-SDAG-NEXT: v_add_u32_e32 v0, vcc, v0, v1228; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]229;230; GFX10-SDAG-LABEL: v_shl2_add_u32:231; GFX10-SDAG: ; %bb.0:232; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)233; GFX10-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, v1234; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]235;236; GFX9-LABEL: v_shl2_add_u32:237; GFX9: ; %bb.0:238; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)239; GFX9-NEXT: v_lshl_add_u32 v0, v0, 2, v1240; GFX9-NEXT: s_setpc_b64 s[30:31]241;242; GFX8-LABEL: v_shl2_add_u32:243; GFX8: ; %bb.0:244; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)245; GFX8-NEXT: v_lshlrev_b32_e32 v0, 2, v0246; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v1247; GFX8-NEXT: s_setpc_b64 s[30:31]248;249; GFX10-LABEL: v_shl2_add_u32:250; GFX10: ; %bb.0:251; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)252; GFX10-NEXT: v_lshl_add_u32 v0, v0, 2, v1253; GFX10-NEXT: s_setpc_b64 s[30:31]254 %shl = shl i32 %src0, 2255 %add = add i32 %shl, %src1256 ret i32 %add257}258 259define i32 @v_shl3_add_u32(i32 %src0, i32 %src1) {260; GFX9-SDAG-LABEL: v_shl3_add_u32:261; GFX9-SDAG: ; %bb.0:262; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)263; GFX9-SDAG-NEXT: v_lshl_add_u32 v0, v0, 3, v1264; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]265;266; GFX8-SDAG-LABEL: v_shl3_add_u32:267; GFX8-SDAG: ; %bb.0:268; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)269; GFX8-SDAG-NEXT: v_lshlrev_b32_e32 v0, 3, v0270; GFX8-SDAG-NEXT: v_add_u32_e32 v0, vcc, v0, v1271; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]272;273; GFX10-SDAG-LABEL: v_shl3_add_u32:274; GFX10-SDAG: ; %bb.0:275; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)276; GFX10-SDAG-NEXT: v_lshl_add_u32 v0, v0, 3, v1277; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]278;279; GFX9-LABEL: v_shl3_add_u32:280; GFX9: ; %bb.0:281; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)282; GFX9-NEXT: v_lshl_add_u32 v0, v0, 3, v1283; GFX9-NEXT: s_setpc_b64 s[30:31]284;285; GFX8-LABEL: v_shl3_add_u32:286; GFX8: ; %bb.0:287; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)288; GFX8-NEXT: v_lshlrev_b32_e32 v0, 3, v0289; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v1290; GFX8-NEXT: s_setpc_b64 s[30:31]291;292; GFX10-LABEL: v_shl3_add_u32:293; GFX10: ; %bb.0:294; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)295; GFX10-NEXT: v_lshl_add_u32 v0, v0, 3, v1296; GFX10-NEXT: s_setpc_b64 s[30:31]297 %shl = shl i32 %src0, 3298 %add = add i32 %shl, %src1299 ret i32 %add300}301 302define i32 @v_shl4_add_u32(i32 %src0, i32 %src1) {303; GFX9-SDAG-LABEL: v_shl4_add_u32:304; GFX9-SDAG: ; %bb.0:305; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)306; GFX9-SDAG-NEXT: v_lshl_add_u32 v0, v0, 4, v1307; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]308;309; GFX8-SDAG-LABEL: v_shl4_add_u32:310; GFX8-SDAG: ; %bb.0:311; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)312; GFX8-SDAG-NEXT: v_lshlrev_b32_e32 v0, 4, v0313; GFX8-SDAG-NEXT: v_add_u32_e32 v0, vcc, v0, v1314; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]315;316; GFX10-SDAG-LABEL: v_shl4_add_u32:317; GFX10-SDAG: ; %bb.0:318; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)319; GFX10-SDAG-NEXT: v_lshl_add_u32 v0, v0, 4, v1320; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]321;322; GFX9-LABEL: v_shl4_add_u32:323; GFX9: ; %bb.0:324; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)325; GFX9-NEXT: v_lshl_add_u32 v0, v0, 4, v1326; GFX9-NEXT: s_setpc_b64 s[30:31]327;328; GFX8-LABEL: v_shl4_add_u32:329; GFX8: ; %bb.0:330; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)331; GFX8-NEXT: v_lshlrev_b32_e32 v0, 4, v0332; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v1333; GFX8-NEXT: s_setpc_b64 s[30:31]334;335; GFX10-LABEL: v_shl4_add_u32:336; GFX10: ; %bb.0:337; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)338; GFX10-NEXT: v_lshl_add_u32 v0, v0, 4, v1339; GFX10-NEXT: s_setpc_b64 s[30:31]340 %shl = shl i32 %src0, 4341 %add = add i32 %shl, %src1342 ret i32 %add343}344 345define i32 @v_shl5_add_u32(i32 %src0, i32 %src1) {346; GFX9-SDAG-LABEL: v_shl5_add_u32:347; GFX9-SDAG: ; %bb.0:348; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)349; GFX9-SDAG-NEXT: v_lshl_add_u32 v0, v0, 5, v1350; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]351;352; GFX8-SDAG-LABEL: v_shl5_add_u32:353; GFX8-SDAG: ; %bb.0:354; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)355; GFX8-SDAG-NEXT: v_lshlrev_b32_e32 v0, 5, v0356; GFX8-SDAG-NEXT: v_add_u32_e32 v0, vcc, v0, v1357; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]358;359; GFX10-SDAG-LABEL: v_shl5_add_u32:360; GFX10-SDAG: ; %bb.0:361; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)362; GFX10-SDAG-NEXT: v_lshl_add_u32 v0, v0, 5, v1363; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]364;365; GFX9-LABEL: v_shl5_add_u32:366; GFX9: ; %bb.0:367; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)368; GFX9-NEXT: v_lshl_add_u32 v0, v0, 5, v1369; GFX9-NEXT: s_setpc_b64 s[30:31]370;371; GFX8-LABEL: v_shl5_add_u32:372; GFX8: ; %bb.0:373; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)374; GFX8-NEXT: v_lshlrev_b32_e32 v0, 5, v0375; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v1376; GFX8-NEXT: s_setpc_b64 s[30:31]377;378; GFX10-LABEL: v_shl5_add_u32:379; GFX10: ; %bb.0:380; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)381; GFX10-NEXT: v_lshl_add_u32 v0, v0, 5, v1382; GFX10-NEXT: s_setpc_b64 s[30:31]383 %shl = shl i32 %src0, 5384 %add = add i32 %shl, %src1385 ret i32 %add386}387 388; FIXME: Use v_lshl_add_u32389; shift is scalar, but add is vector.390define amdgpu_ps float @shl1_add_u32_vgpr1(i32 inreg %src0, i32 %src1) {391; GFX9-SDAG-LABEL: shl1_add_u32_vgpr1:392; GFX9-SDAG: ; %bb.0:393; GFX9-SDAG-NEXT: v_lshl_add_u32 v0, s0, 1, v0394; GFX9-SDAG-NEXT: ; return to shader part epilog395;396; GFX8-SDAG-LABEL: shl1_add_u32_vgpr1:397; GFX8-SDAG: ; %bb.0:398; GFX8-SDAG-NEXT: s_lshl_b32 s0, s0, 1399; GFX8-SDAG-NEXT: v_add_u32_e32 v0, vcc, s0, v0400; GFX8-SDAG-NEXT: ; return to shader part epilog401;402; GFX10-SDAG-LABEL: shl1_add_u32_vgpr1:403; GFX10-SDAG: ; %bb.0:404; GFX10-SDAG-NEXT: v_lshl_add_u32 v0, s0, 1, v0405; GFX10-SDAG-NEXT: ; return to shader part epilog406;407; GFX9-LABEL: shl1_add_u32_vgpr1:408; GFX9: ; %bb.0:409; GFX9-NEXT: s_lshl_b32 s0, s0, 1410; GFX9-NEXT: v_add_u32_e32 v0, s0, v0411; GFX9-NEXT: ; return to shader part epilog412;413; GFX8-LABEL: shl1_add_u32_vgpr1:414; GFX8: ; %bb.0:415; GFX8-NEXT: s_lshl_b32 s0, s0, 1416; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v0417; GFX8-NEXT: ; return to shader part epilog418;419; GFX10-LABEL: shl1_add_u32_vgpr1:420; GFX10: ; %bb.0:421; GFX10-NEXT: s_lshl_b32 s0, s0, 1422; GFX10-NEXT: v_add_nc_u32_e32 v0, s0, v0423; GFX10-NEXT: ; return to shader part epilog424 %shl = shl i32 %src0, 1425 %add = add i32 %shl, %src1426 %cast = bitcast i32 %add to float427 ret float %cast428}429 430define amdgpu_ps float @shl2_add_u32_vgpr1(i32 inreg %src0, i32 %src1) {431; GFX9-SDAG-LABEL: shl2_add_u32_vgpr1:432; GFX9-SDAG: ; %bb.0:433; GFX9-SDAG-NEXT: v_lshl_add_u32 v0, s0, 2, v0434; GFX9-SDAG-NEXT: ; return to shader part epilog435;436; GFX8-SDAG-LABEL: shl2_add_u32_vgpr1:437; GFX8-SDAG: ; %bb.0:438; GFX8-SDAG-NEXT: s_lshl_b32 s0, s0, 2439; GFX8-SDAG-NEXT: v_add_u32_e32 v0, vcc, s0, v0440; GFX8-SDAG-NEXT: ; return to shader part epilog441;442; GFX10-SDAG-LABEL: shl2_add_u32_vgpr1:443; GFX10-SDAG: ; %bb.0:444; GFX10-SDAG-NEXT: v_lshl_add_u32 v0, s0, 2, v0445; GFX10-SDAG-NEXT: ; return to shader part epilog446;447; GFX9-LABEL: shl2_add_u32_vgpr1:448; GFX9: ; %bb.0:449; GFX9-NEXT: s_lshl_b32 s0, s0, 2450; GFX9-NEXT: v_add_u32_e32 v0, s0, v0451; GFX9-NEXT: ; return to shader part epilog452;453; GFX8-LABEL: shl2_add_u32_vgpr1:454; GFX8: ; %bb.0:455; GFX8-NEXT: s_lshl_b32 s0, s0, 2456; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v0457; GFX8-NEXT: ; return to shader part epilog458;459; GFX10-LABEL: shl2_add_u32_vgpr1:460; GFX10: ; %bb.0:461; GFX10-NEXT: s_lshl_b32 s0, s0, 2462; GFX10-NEXT: v_add_nc_u32_e32 v0, s0, v0463; GFX10-NEXT: ; return to shader part epilog464 %shl = shl i32 %src0, 2465 %add = add i32 %shl, %src1466 %cast = bitcast i32 %add to float467 ret float %cast468}469 470define amdgpu_ps float @shl3_add_u32_vgpr1(i32 inreg %src0, i32 %src1) {471; GFX9-SDAG-LABEL: shl3_add_u32_vgpr1:472; GFX9-SDAG: ; %bb.0:473; GFX9-SDAG-NEXT: v_lshl_add_u32 v0, s0, 3, v0474; GFX9-SDAG-NEXT: ; return to shader part epilog475;476; GFX8-SDAG-LABEL: shl3_add_u32_vgpr1:477; GFX8-SDAG: ; %bb.0:478; GFX8-SDAG-NEXT: s_lshl_b32 s0, s0, 3479; GFX8-SDAG-NEXT: v_add_u32_e32 v0, vcc, s0, v0480; GFX8-SDAG-NEXT: ; return to shader part epilog481;482; GFX10-SDAG-LABEL: shl3_add_u32_vgpr1:483; GFX10-SDAG: ; %bb.0:484; GFX10-SDAG-NEXT: v_lshl_add_u32 v0, s0, 3, v0485; GFX10-SDAG-NEXT: ; return to shader part epilog486;487; GFX9-LABEL: shl3_add_u32_vgpr1:488; GFX9: ; %bb.0:489; GFX9-NEXT: s_lshl_b32 s0, s0, 3490; GFX9-NEXT: v_add_u32_e32 v0, s0, v0491; GFX9-NEXT: ; return to shader part epilog492;493; GFX8-LABEL: shl3_add_u32_vgpr1:494; GFX8: ; %bb.0:495; GFX8-NEXT: s_lshl_b32 s0, s0, 3496; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v0497; GFX8-NEXT: ; return to shader part epilog498;499; GFX10-LABEL: shl3_add_u32_vgpr1:500; GFX10: ; %bb.0:501; GFX10-NEXT: s_lshl_b32 s0, s0, 3502; GFX10-NEXT: v_add_nc_u32_e32 v0, s0, v0503; GFX10-NEXT: ; return to shader part epilog504 %shl = shl i32 %src0, 3505 %add = add i32 %shl, %src1506 %cast = bitcast i32 %add to float507 ret float %cast508}509 510define amdgpu_ps float @shl4_add_u32_vgpr1(i32 inreg %src0, i32 %src1) {511; GFX9-SDAG-LABEL: shl4_add_u32_vgpr1:512; GFX9-SDAG: ; %bb.0:513; GFX9-SDAG-NEXT: v_lshl_add_u32 v0, s0, 4, v0514; GFX9-SDAG-NEXT: ; return to shader part epilog515;516; GFX8-SDAG-LABEL: shl4_add_u32_vgpr1:517; GFX8-SDAG: ; %bb.0:518; GFX8-SDAG-NEXT: s_lshl_b32 s0, s0, 4519; GFX8-SDAG-NEXT: v_add_u32_e32 v0, vcc, s0, v0520; GFX8-SDAG-NEXT: ; return to shader part epilog521;522; GFX10-SDAG-LABEL: shl4_add_u32_vgpr1:523; GFX10-SDAG: ; %bb.0:524; GFX10-SDAG-NEXT: v_lshl_add_u32 v0, s0, 4, v0525; GFX10-SDAG-NEXT: ; return to shader part epilog526;527; GFX9-LABEL: shl4_add_u32_vgpr1:528; GFX9: ; %bb.0:529; GFX9-NEXT: s_lshl_b32 s0, s0, 4530; GFX9-NEXT: v_add_u32_e32 v0, s0, v0531; GFX9-NEXT: ; return to shader part epilog532;533; GFX8-LABEL: shl4_add_u32_vgpr1:534; GFX8: ; %bb.0:535; GFX8-NEXT: s_lshl_b32 s0, s0, 4536; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v0537; GFX8-NEXT: ; return to shader part epilog538;539; GFX10-LABEL: shl4_add_u32_vgpr1:540; GFX10: ; %bb.0:541; GFX10-NEXT: s_lshl_b32 s0, s0, 4542; GFX10-NEXT: v_add_nc_u32_e32 v0, s0, v0543; GFX10-NEXT: ; return to shader part epilog544 %shl = shl i32 %src0, 4545 %add = add i32 %shl, %src1546 %cast = bitcast i32 %add to float547 ret float %cast548}549 550define amdgpu_ps float @shl5_add_u32_vgpr1(i32 inreg %src0, i32 %src1) {551; GFX9-SDAG-LABEL: shl5_add_u32_vgpr1:552; GFX9-SDAG: ; %bb.0:553; GFX9-SDAG-NEXT: v_lshl_add_u32 v0, s0, 5, v0554; GFX9-SDAG-NEXT: ; return to shader part epilog555;556; GFX8-SDAG-LABEL: shl5_add_u32_vgpr1:557; GFX8-SDAG: ; %bb.0:558; GFX8-SDAG-NEXT: s_lshl_b32 s0, s0, 5559; GFX8-SDAG-NEXT: v_add_u32_e32 v0, vcc, s0, v0560; GFX8-SDAG-NEXT: ; return to shader part epilog561;562; GFX10-SDAG-LABEL: shl5_add_u32_vgpr1:563; GFX10-SDAG: ; %bb.0:564; GFX10-SDAG-NEXT: v_lshl_add_u32 v0, s0, 5, v0565; GFX10-SDAG-NEXT: ; return to shader part epilog566;567; GFX9-LABEL: shl5_add_u32_vgpr1:568; GFX9: ; %bb.0:569; GFX9-NEXT: s_lshl_b32 s0, s0, 5570; GFX9-NEXT: v_add_u32_e32 v0, s0, v0571; GFX9-NEXT: ; return to shader part epilog572;573; GFX8-LABEL: shl5_add_u32_vgpr1:574; GFX8: ; %bb.0:575; GFX8-NEXT: s_lshl_b32 s0, s0, 5576; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v0577; GFX8-NEXT: ; return to shader part epilog578;579; GFX10-LABEL: shl5_add_u32_vgpr1:580; GFX10: ; %bb.0:581; GFX10-NEXT: s_lshl_b32 s0, s0, 5582; GFX10-NEXT: v_add_nc_u32_e32 v0, s0, v0583; GFX10-NEXT: ; return to shader part epilog584 %shl = shl i32 %src0, 5585 %add = add i32 %shl, %src1586 %cast = bitcast i32 %add to float587 ret float %cast588}589 590define amdgpu_ps <2 x i32> @s_shl1_add_u32_v2(<2 x i32> inreg %src0, <2 x i32> inreg %src1) {591; GFX9-SDAG-LABEL: s_shl1_add_u32_v2:592; GFX9-SDAG: ; %bb.0:593; GFX9-SDAG-NEXT: s_lshl1_add_u32 s1, s1, s3594; GFX9-SDAG-NEXT: s_lshl1_add_u32 s0, s0, s2595; GFX9-SDAG-NEXT: ; return to shader part epilog596;597; GFX8-SDAG-LABEL: s_shl1_add_u32_v2:598; GFX8-SDAG: ; %bb.0:599; GFX8-SDAG-NEXT: s_lshl_b32 s0, s0, 1600; GFX8-SDAG-NEXT: s_lshl_b32 s1, s1, 1601; GFX8-SDAG-NEXT: s_add_i32 s1, s1, s3602; GFX8-SDAG-NEXT: s_add_i32 s0, s0, s2603; GFX8-SDAG-NEXT: ; return to shader part epilog604;605; GFX10-SDAG-LABEL: s_shl1_add_u32_v2:606; GFX10-SDAG: ; %bb.0:607; GFX10-SDAG-NEXT: s_lshl1_add_u32 s0, s0, s2608; GFX10-SDAG-NEXT: s_lshl1_add_u32 s1, s1, s3609; GFX10-SDAG-NEXT: ; return to shader part epilog610;611; GFX9-LABEL: s_shl1_add_u32_v2:612; GFX9: ; %bb.0:613; GFX9-NEXT: s_lshl1_add_u32 s0, s0, s2614; GFX9-NEXT: s_lshl1_add_u32 s1, s1, s3615; GFX9-NEXT: ; return to shader part epilog616;617; GFX8-LABEL: s_shl1_add_u32_v2:618; GFX8: ; %bb.0:619; GFX8-NEXT: s_lshl_b32 s0, s0, 1620; GFX8-NEXT: s_lshl_b32 s1, s1, 1621; GFX8-NEXT: s_add_i32 s0, s0, s2622; GFX8-NEXT: s_add_i32 s1, s1, s3623; GFX8-NEXT: ; return to shader part epilog624;625; GFX10-LABEL: s_shl1_add_u32_v2:626; GFX10: ; %bb.0:627; GFX10-NEXT: s_lshl1_add_u32 s0, s0, s2628; GFX10-NEXT: s_lshl1_add_u32 s1, s1, s3629; GFX10-NEXT: ; return to shader part epilog630 %shl = shl <2 x i32> %src0, <i32 1, i32 1>631 %add = add <2 x i32> %shl, %src1632 ret <2 x i32> %add633}634 635define amdgpu_ps <2 x i32> @s_shl2_add_u32_v2(<2 x i32> inreg %src0, <2 x i32> inreg %src1) {636; GFX9-SDAG-LABEL: s_shl2_add_u32_v2:637; GFX9-SDAG: ; %bb.0:638; GFX9-SDAG-NEXT: s_lshl2_add_u32 s1, s1, s3639; GFX9-SDAG-NEXT: s_lshl2_add_u32 s0, s0, s2640; GFX9-SDAG-NEXT: ; return to shader part epilog641;642; GFX8-SDAG-LABEL: s_shl2_add_u32_v2:643; GFX8-SDAG: ; %bb.0:644; GFX8-SDAG-NEXT: s_lshl_b32 s0, s0, 2645; GFX8-SDAG-NEXT: s_lshl_b32 s1, s1, 2646; GFX8-SDAG-NEXT: s_add_i32 s1, s1, s3647; GFX8-SDAG-NEXT: s_add_i32 s0, s0, s2648; GFX8-SDAG-NEXT: ; return to shader part epilog649;650; GFX10-SDAG-LABEL: s_shl2_add_u32_v2:651; GFX10-SDAG: ; %bb.0:652; GFX10-SDAG-NEXT: s_lshl2_add_u32 s0, s0, s2653; GFX10-SDAG-NEXT: s_lshl2_add_u32 s1, s1, s3654; GFX10-SDAG-NEXT: ; return to shader part epilog655;656; GFX9-LABEL: s_shl2_add_u32_v2:657; GFX9: ; %bb.0:658; GFX9-NEXT: s_lshl2_add_u32 s0, s0, s2659; GFX9-NEXT: s_lshl2_add_u32 s1, s1, s3660; GFX9-NEXT: ; return to shader part epilog661;662; GFX8-LABEL: s_shl2_add_u32_v2:663; GFX8: ; %bb.0:664; GFX8-NEXT: s_lshl_b32 s0, s0, 2665; GFX8-NEXT: s_lshl_b32 s1, s1, 2666; GFX8-NEXT: s_add_i32 s0, s0, s2667; GFX8-NEXT: s_add_i32 s1, s1, s3668; GFX8-NEXT: ; return to shader part epilog669;670; GFX10-LABEL: s_shl2_add_u32_v2:671; GFX10: ; %bb.0:672; GFX10-NEXT: s_lshl2_add_u32 s0, s0, s2673; GFX10-NEXT: s_lshl2_add_u32 s1, s1, s3674; GFX10-NEXT: ; return to shader part epilog675 %shl = shl <2 x i32> %src0, <i32 2, i32 2>676 %add = add <2 x i32> %shl, %src1677 ret <2 x i32> %add678}679 680define amdgpu_ps <2 x i32> @s_shl3_add_u32_v2(<2 x i32> inreg %src0, <2 x i32> inreg %src1) {681; GFX9-SDAG-LABEL: s_shl3_add_u32_v2:682; GFX9-SDAG: ; %bb.0:683; GFX9-SDAG-NEXT: s_lshl3_add_u32 s1, s1, s3684; GFX9-SDAG-NEXT: s_lshl3_add_u32 s0, s0, s2685; GFX9-SDAG-NEXT: ; return to shader part epilog686;687; GFX8-SDAG-LABEL: s_shl3_add_u32_v2:688; GFX8-SDAG: ; %bb.0:689; GFX8-SDAG-NEXT: s_lshl_b32 s0, s0, 3690; GFX8-SDAG-NEXT: s_lshl_b32 s1, s1, 3691; GFX8-SDAG-NEXT: s_add_i32 s1, s1, s3692; GFX8-SDAG-NEXT: s_add_i32 s0, s0, s2693; GFX8-SDAG-NEXT: ; return to shader part epilog694;695; GFX10-SDAG-LABEL: s_shl3_add_u32_v2:696; GFX10-SDAG: ; %bb.0:697; GFX10-SDAG-NEXT: s_lshl3_add_u32 s0, s0, s2698; GFX10-SDAG-NEXT: s_lshl3_add_u32 s1, s1, s3699; GFX10-SDAG-NEXT: ; return to shader part epilog700;701; GFX9-LABEL: s_shl3_add_u32_v2:702; GFX9: ; %bb.0:703; GFX9-NEXT: s_lshl3_add_u32 s0, s0, s2704; GFX9-NEXT: s_lshl3_add_u32 s1, s1, s3705; GFX9-NEXT: ; return to shader part epilog706;707; GFX8-LABEL: s_shl3_add_u32_v2:708; GFX8: ; %bb.0:709; GFX8-NEXT: s_lshl_b32 s0, s0, 3710; GFX8-NEXT: s_lshl_b32 s1, s1, 3711; GFX8-NEXT: s_add_i32 s0, s0, s2712; GFX8-NEXT: s_add_i32 s1, s1, s3713; GFX8-NEXT: ; return to shader part epilog714;715; GFX10-LABEL: s_shl3_add_u32_v2:716; GFX10: ; %bb.0:717; GFX10-NEXT: s_lshl3_add_u32 s0, s0, s2718; GFX10-NEXT: s_lshl3_add_u32 s1, s1, s3719; GFX10-NEXT: ; return to shader part epilog720 %shl = shl <2 x i32> %src0, <i32 3, i32 3>721 %add = add <2 x i32> %shl, %src1722 ret <2 x i32> %add723}724 725define amdgpu_ps <2 x i32> @s_shl4_add_u32_v2(<2 x i32> inreg %src0, <2 x i32> inreg %src1) {726; GFX9-SDAG-LABEL: s_shl4_add_u32_v2:727; GFX9-SDAG: ; %bb.0:728; GFX9-SDAG-NEXT: s_lshl4_add_u32 s1, s1, s3729; GFX9-SDAG-NEXT: s_lshl4_add_u32 s0, s0, s2730; GFX9-SDAG-NEXT: ; return to shader part epilog731;732; GFX8-SDAG-LABEL: s_shl4_add_u32_v2:733; GFX8-SDAG: ; %bb.0:734; GFX8-SDAG-NEXT: s_lshl_b32 s0, s0, 4735; GFX8-SDAG-NEXT: s_lshl_b32 s1, s1, 4736; GFX8-SDAG-NEXT: s_add_i32 s1, s1, s3737; GFX8-SDAG-NEXT: s_add_i32 s0, s0, s2738; GFX8-SDAG-NEXT: ; return to shader part epilog739;740; GFX10-SDAG-LABEL: s_shl4_add_u32_v2:741; GFX10-SDAG: ; %bb.0:742; GFX10-SDAG-NEXT: s_lshl4_add_u32 s0, s0, s2743; GFX10-SDAG-NEXT: s_lshl4_add_u32 s1, s1, s3744; GFX10-SDAG-NEXT: ; return to shader part epilog745;746; GFX9-LABEL: s_shl4_add_u32_v2:747; GFX9: ; %bb.0:748; GFX9-NEXT: s_lshl4_add_u32 s0, s0, s2749; GFX9-NEXT: s_lshl4_add_u32 s1, s1, s3750; GFX9-NEXT: ; return to shader part epilog751;752; GFX8-LABEL: s_shl4_add_u32_v2:753; GFX8: ; %bb.0:754; GFX8-NEXT: s_lshl_b32 s0, s0, 4755; GFX8-NEXT: s_lshl_b32 s1, s1, 4756; GFX8-NEXT: s_add_i32 s0, s0, s2757; GFX8-NEXT: s_add_i32 s1, s1, s3758; GFX8-NEXT: ; return to shader part epilog759;760; GFX10-LABEL: s_shl4_add_u32_v2:761; GFX10: ; %bb.0:762; GFX10-NEXT: s_lshl4_add_u32 s0, s0, s2763; GFX10-NEXT: s_lshl4_add_u32 s1, s1, s3764; GFX10-NEXT: ; return to shader part epilog765 %shl = shl <2 x i32> %src0, <i32 4, i32 4>766 %add = add <2 x i32> %shl, %src1767 ret <2 x i32> %add768}769 770define amdgpu_ps <2 x i32> @s_shl_2_4_add_u32_v2(<2 x i32> inreg %src0, <2 x i32> inreg %src1) {771; GFX9-SDAG-LABEL: s_shl_2_4_add_u32_v2:772; GFX9-SDAG: ; %bb.0:773; GFX9-SDAG-NEXT: s_lshl4_add_u32 s1, s1, s3774; GFX9-SDAG-NEXT: s_lshl2_add_u32 s0, s0, s2775; GFX9-SDAG-NEXT: ; return to shader part epilog776;777; GFX8-SDAG-LABEL: s_shl_2_4_add_u32_v2:778; GFX8-SDAG: ; %bb.0:779; GFX8-SDAG-NEXT: s_lshl_b32 s0, s0, 2780; GFX8-SDAG-NEXT: s_lshl_b32 s1, s1, 4781; GFX8-SDAG-NEXT: s_add_i32 s1, s1, s3782; GFX8-SDAG-NEXT: s_add_i32 s0, s0, s2783; GFX8-SDAG-NEXT: ; return to shader part epilog784;785; GFX10-SDAG-LABEL: s_shl_2_4_add_u32_v2:786; GFX10-SDAG: ; %bb.0:787; GFX10-SDAG-NEXT: s_lshl2_add_u32 s0, s0, s2788; GFX10-SDAG-NEXT: s_lshl4_add_u32 s1, s1, s3789; GFX10-SDAG-NEXT: ; return to shader part epilog790;791; GFX9-LABEL: s_shl_2_4_add_u32_v2:792; GFX9: ; %bb.0:793; GFX9-NEXT: s_lshl2_add_u32 s0, s0, s2794; GFX9-NEXT: s_lshl4_add_u32 s1, s1, s3795; GFX9-NEXT: ; return to shader part epilog796;797; GFX8-LABEL: s_shl_2_4_add_u32_v2:798; GFX8: ; %bb.0:799; GFX8-NEXT: s_lshl_b32 s0, s0, 2800; GFX8-NEXT: s_lshl_b32 s1, s1, 4801; GFX8-NEXT: s_add_i32 s0, s0, s2802; GFX8-NEXT: s_add_i32 s1, s1, s3803; GFX8-NEXT: ; return to shader part epilog804;805; GFX10-LABEL: s_shl_2_4_add_u32_v2:806; GFX10: ; %bb.0:807; GFX10-NEXT: s_lshl2_add_u32 s0, s0, s2808; GFX10-NEXT: s_lshl4_add_u32 s1, s1, s3809; GFX10-NEXT: ; return to shader part epilog810 %shl = shl <2 x i32> %src0, <i32 2, i32 4>811 %add = add <2 x i32> %shl, %src1812 ret <2 x i32> %add813}814 815define amdgpu_ps { i32, i32 } @s_shl4_add_u32_multi_use(i32 inreg %src0, i32 inreg %src1) {816; GCN-LABEL: s_shl4_add_u32_multi_use:817; GCN: ; %bb.0:818; GCN-NEXT: s_lshl_b32 s0, s0, 4819; GCN-NEXT: s_add_i32 s1, s0, s1820; GCN-NEXT: ; return to shader part epilog821 %shl = shl i32 %src0, 4822 %add = add i32 %shl, %src1823 %insert0 = insertvalue { i32, i32 } poison, i32 %shl, 0824 %insert1 = insertvalue { i32, i32 } %insert0, i32 %add, 1825 ret { i32, i32 } %insert1826}827 828define amdgpu_ps { i32, i32 } @s_shl3_add_u32_multi_use(i32 inreg %src0, i32 inreg %src1) {829; GCN-LABEL: s_shl3_add_u32_multi_use:830; GCN: ; %bb.0:831; GCN-NEXT: s_lshl_b32 s0, s0, 3832; GCN-NEXT: s_add_i32 s1, s0, s1833; GCN-NEXT: ; return to shader part epilog834 %shl = shl i32 %src0, 3835 %add = add i32 %shl, %src1836 %insert0 = insertvalue { i32, i32 } poison, i32 %shl, 0837 %insert1 = insertvalue { i32, i32 } %insert0, i32 %add, 1838 ret { i32, i32 } %insert1839}840 841define amdgpu_ps { i32, i32 } @s_shl2_add_u32_multi_use(i32 inreg %src0, i32 inreg %src1) {842; GCN-LABEL: s_shl2_add_u32_multi_use:843; GCN: ; %bb.0:844; GCN-NEXT: s_lshl_b32 s0, s0, 2845; GCN-NEXT: s_add_i32 s1, s0, s1846; GCN-NEXT: ; return to shader part epilog847 %shl = shl i32 %src0, 2848 %add = add i32 %shl, %src1849 %insert0 = insertvalue { i32, i32 } poison, i32 %shl, 0850 %insert1 = insertvalue { i32, i32 } %insert0, i32 %add, 1851 ret { i32, i32 } %insert1852}853 854 855define amdgpu_ps { i32, i32 } @s_shl1_add_u32_multi_use(i32 inreg %src0, i32 inreg %src1) {856; GCN-LABEL: s_shl1_add_u32_multi_use:857; GCN: ; %bb.0:858; GCN-NEXT: s_lshl_b32 s0, s0, 1859; GCN-NEXT: s_add_i32 s1, s0, s1860; GCN-NEXT: ; return to shader part epilog861 %shl = shl i32 %src0, 1862 %add = add i32 %shl, %src1863 %insert0 = insertvalue { i32, i32 } poison, i32 %shl, 0864 %insert1 = insertvalue { i32, i32 } %insert0, i32 %add, 1865 ret { i32, i32 } %insert1866}867