122 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=fiji | FileCheck -check-prefix=VI %s3; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 | FileCheck -check-prefix=GFX9 %s4; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 | FileCheck -check-prefix=GFX10 %s5; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 | FileCheck -check-prefix=GFX10 %s6 7; ===================================================================================8; V_LSHL_ADD_U329; ===================================================================================10 11define amdgpu_ps float @shl_add(i32 %a, i32 %b, i32 %c) {12; VI-LABEL: shl_add:13; VI: ; %bb.0:14; VI-NEXT: v_lshlrev_b32_e32 v0, v1, v015; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v216; VI-NEXT: ; return to shader part epilog17;18; GFX9-LABEL: shl_add:19; GFX9: ; %bb.0:20; GFX9-NEXT: v_lshl_add_u32 v0, v0, v1, v221; GFX9-NEXT: ; return to shader part epilog22;23; GFX10-LABEL: shl_add:24; GFX10: ; %bb.0:25; GFX10-NEXT: v_lshl_add_u32 v0, v0, v1, v226; GFX10-NEXT: ; return to shader part epilog27 %x = shl i32 %a, %b28 %result = add i32 %x, %c29 %bc = bitcast i32 %result to float30 ret float %bc31}32 33; ThreeOp instruction variant not used due to Constant Bus Limitations34define amdgpu_ps float @shl_add_vgpr_a(i32 %a, i32 inreg %b, i32 inreg %c) {35; VI-LABEL: shl_add_vgpr_a:36; VI: ; %bb.0:37; VI-NEXT: v_lshlrev_b32_e32 v0, s2, v038; VI-NEXT: v_add_u32_e32 v0, vcc, s3, v039; VI-NEXT: ; return to shader part epilog40;41; GFX9-LABEL: shl_add_vgpr_a:42; GFX9: ; %bb.0:43; GFX9-NEXT: v_lshlrev_b32_e32 v0, s2, v044; GFX9-NEXT: v_add_u32_e32 v0, s3, v045; GFX9-NEXT: ; return to shader part epilog46;47; GFX10-LABEL: shl_add_vgpr_a:48; GFX10: ; %bb.0:49; GFX10-NEXT: v_lshl_add_u32 v0, v0, s2, s350; GFX10-NEXT: ; return to shader part epilog51 %x = shl i32 %a, %b52 %result = add i32 %x, %c53 %bc = bitcast i32 %result to float54 ret float %bc55}56 57define amdgpu_ps float @shl_add_vgpr_all(i32 %a, i32 %b, i32 %c) {58; VI-LABEL: shl_add_vgpr_all:59; VI: ; %bb.0:60; VI-NEXT: v_lshlrev_b32_e32 v0, v1, v061; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v262; VI-NEXT: ; return to shader part epilog63;64; GFX9-LABEL: shl_add_vgpr_all:65; GFX9: ; %bb.0:66; GFX9-NEXT: v_lshl_add_u32 v0, v0, v1, v267; GFX9-NEXT: ; return to shader part epilog68;69; GFX10-LABEL: shl_add_vgpr_all:70; GFX10: ; %bb.0:71; GFX10-NEXT: v_lshl_add_u32 v0, v0, v1, v272; GFX10-NEXT: ; return to shader part epilog73 %x = shl i32 %a, %b74 %result = add i32 %x, %c75 %bc = bitcast i32 %result to float76 ret float %bc77}78 79define amdgpu_ps float @shl_add_vgpr_ab(i32 %a, i32 %b, i32 inreg %c) {80; VI-LABEL: shl_add_vgpr_ab:81; VI: ; %bb.0:82; VI-NEXT: v_lshlrev_b32_e32 v0, v1, v083; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v084; VI-NEXT: ; return to shader part epilog85;86; GFX9-LABEL: shl_add_vgpr_ab:87; GFX9: ; %bb.0:88; GFX9-NEXT: v_lshl_add_u32 v0, v0, v1, s289; GFX9-NEXT: ; return to shader part epilog90;91; GFX10-LABEL: shl_add_vgpr_ab:92; GFX10: ; %bb.0:93; GFX10-NEXT: v_lshl_add_u32 v0, v0, v1, s294; GFX10-NEXT: ; return to shader part epilog95 %x = shl i32 %a, %b96 %result = add i32 %x, %c97 %bc = bitcast i32 %result to float98 ret float %bc99}100 101define amdgpu_ps float @shl_add_vgpr_const(i32 %a, i32 %b) {102; VI-LABEL: shl_add_vgpr_const:103; VI: ; %bb.0:104; VI-NEXT: v_lshlrev_b32_e32 v0, 3, v0105; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v1106; VI-NEXT: ; return to shader part epilog107;108; GFX9-LABEL: shl_add_vgpr_const:109; GFX9: ; %bb.0:110; GFX9-NEXT: v_lshl_add_u32 v0, v0, 3, v1111; GFX9-NEXT: ; return to shader part epilog112;113; GFX10-LABEL: shl_add_vgpr_const:114; GFX10: ; %bb.0:115; GFX10-NEXT: v_lshl_add_u32 v0, v0, 3, v1116; GFX10-NEXT: ; return to shader part epilog117 %x = shl i32 %a, 3118 %result = add i32 %x, %b119 %bc = bitcast i32 %result to float120 ret float %bc121}122