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1; RUN: llc -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=SI %s2 3declare i32 @llvm.amdgcn.workitem.id.x() #14 5; Test with inline immediate6 7; SI-LABEL: {{^}}shl_2_add_9_i32:8; SI: v_lshlrev_b32_e32 [[REG:v[0-9]+]], 2, {{v[0-9]+}}9; SI: v_add_i32_e32 [[RESULT:v[0-9]+]], vcc, 36, [[REG]]10; SI: buffer_store_dword [[RESULT]]11; SI: s_endpgm12define amdgpu_kernel void @shl_2_add_9_i32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {13 %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #114 %ptr = getelementptr i32, ptr addrspace(1) %in, i32 %tid.x15 %val = load i32, ptr addrspace(1) %ptr, align 416 %add = add i32 %val, 917 %result = shl i32 %add, 218 store i32 %result, ptr addrspace(1) %out, align 419 ret void20}21 22; SI-LABEL: {{^}}shl_2_add_9_i32_2_add_uses:23; SI-DAG: v_add_i32_e32 [[ADDREG:v[0-9]+]], vcc, 9, {{v[0-9]+}}24; SI-DAG: v_lshlrev_b32_e32 [[SHLREG:v[0-9]+]], 2, {{v[0-9]+}}25; SI-DAG: buffer_store_dword [[ADDREG]]26; SI-DAG: buffer_store_dword [[SHLREG]]27; SI: s_endpgm28define amdgpu_kernel void @shl_2_add_9_i32_2_add_uses(ptr addrspace(1) %out0, ptr addrspace(1) %out1, ptr addrspace(1) %in) #0 {29 %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #130 %ptr = getelementptr i32, ptr addrspace(1) %in, i32 %tid.x31 %val = load i32, ptr addrspace(1) %ptr, align 432 %add = add i32 %val, 933 %result = shl i32 %add, 234 store i32 %result, ptr addrspace(1) %out0, align 435 store i32 %add, ptr addrspace(1) %out1, align 436 ret void37}38 39; Test with add literal constant40 41; SI-LABEL: {{^}}shl_2_add_999_i32:42; SI: v_lshlrev_b32_e32 [[REG:v[0-9]+]], 2, {{v[0-9]+}}43; SI: v_add_i32_e32 [[RESULT:v[0-9]+]], vcc, 0xf9c, [[REG]]44; SI: buffer_store_dword [[RESULT]]45; SI: s_endpgm46define amdgpu_kernel void @shl_2_add_999_i32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {47 %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #148 %ptr = getelementptr i32, ptr addrspace(1) %in, i32 %tid.x49 %val = load i32, ptr addrspace(1) %ptr, align 450 %shl = add i32 %val, 99951 %result = shl i32 %shl, 252 store i32 %result, ptr addrspace(1) %out, align 453 ret void54}55 56; SI-LABEL: {{^}}test_add_shl_add_constant:57; SI-DAG: s_load_dwordx2 s[[[X:[0-9]+]]:[[Y:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, 0x1358; SI-DAG: s_lshl_b32 [[SHL3:s[0-9]+]], s[[X]], 359; SI: s_add_i32 [[RESULT:s[0-9]+]], [[SHL3]], s[[Y]]60; SI: s_addk_i32 [[RESULT]], 0x3d861; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[RESULT]]62; SI: buffer_store_dword [[VRESULT]]63define amdgpu_kernel void @test_add_shl_add_constant(ptr addrspace(1) %out, [8 x i32], i32 %x, i32 %y) #0 {64 %add.0 = add i32 %x, 12365 %shl = shl i32 %add.0, 366 %add.1 = add i32 %shl, %y67 store i32 %add.1, ptr addrspace(1) %out, align 468 ret void69}70 71; SI-LABEL: {{^}}test_add_shl_add_constant_inv:72; SI-DAG: s_load_dwordx2 s[[[X:[0-9]+]]:[[Y:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, 0x1373; SI: s_lshl_b32 [[SHL3:s[0-9]+]], s[[X]], 374; SI: s_add_i32 [[TMP:s[0-9]+]], [[SHL3]], s[[Y]]75; SI: s_addk_i32 [[TMP]], 0x3d876; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[TMP]]77; SI: buffer_store_dword [[VRESULT]]78 79define amdgpu_kernel void @test_add_shl_add_constant_inv(ptr addrspace(1) %out, [8 x i32], i32 %x, i32 %y) #0 {80 %add.0 = add i32 %x, 12381 %shl = shl i32 %add.0, 382 %add.1 = add i32 %y, %shl83 store i32 %add.1, ptr addrspace(1) %out, align 484 ret void85}86 87attributes #0 = { nounwind }88attributes #1 = { nounwind readnone }89