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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=amdgcn -mcpu=bonaire < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI %s3; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s4 5; Test that doing a shift of a pointer with a constant add will be6; folded into the constant offset addressing mode even if the add has7; multiple uses. This is relevant to accessing 2 separate, adjacent8; LDS globals.9 10declare i32 @llvm.amdgcn.workitem.id.x() #111 12@lds0 = addrspace(3) global [512 x float] poison, align 413@lds1 = addrspace(3) global [512 x float] poison, align 414 15 16; Make sure the (add tid, 2) << 2 gets folded into the ds's offset as (tid << 2) + 817define amdgpu_kernel void @load_shl_base_lds_0(ptr addrspace(1) %out, ptr addrspace(1) %add_use) #0 {18; CI-LABEL: load_shl_base_lds_0:19; CI: ; %bb.0:20; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x921; CI-NEXT: v_lshlrev_b32_e32 v1, 2, v022; CI-NEXT: s_mov_b32 m0, -123; CI-NEXT: ds_read_b32 v1, v1 offset:824; CI-NEXT: s_mov_b32 s7, 0xf00025; CI-NEXT: s_mov_b32 s6, -126; CI-NEXT: s_waitcnt lgkmcnt(0)27; CI-NEXT: s_mov_b32 s4, s028; CI-NEXT: s_mov_b32 s5, s129; CI-NEXT: s_mov_b32 s0, s230; CI-NEXT: s_mov_b32 s1, s331; CI-NEXT: s_mov_b32 s2, s632; CI-NEXT: s_mov_b32 s3, s733; CI-NEXT: v_add_i32_e32 v0, vcc, 2, v034; CI-NEXT: buffer_store_dword v0, off, s[0:3], 035; CI-NEXT: buffer_store_dword v1, off, s[4:7], 036; CI-NEXT: s_endpgm37;38; VI-LABEL: load_shl_base_lds_0:39; VI: ; %bb.0:40; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2441; VI-NEXT: v_lshlrev_b32_e32 v1, 2, v042; VI-NEXT: s_mov_b32 m0, -143; VI-NEXT: ds_read_b32 v1, v1 offset:844; VI-NEXT: s_mov_b32 s7, 0xf00045; VI-NEXT: s_mov_b32 s6, -146; VI-NEXT: s_waitcnt lgkmcnt(0)47; VI-NEXT: s_mov_b32 s4, s048; VI-NEXT: s_mov_b32 s5, s149; VI-NEXT: s_mov_b32 s0, s250; VI-NEXT: s_mov_b32 s1, s351; VI-NEXT: s_mov_b32 s2, s652; VI-NEXT: s_mov_b32 s3, s753; VI-NEXT: v_add_u32_e32 v0, vcc, 2, v054; VI-NEXT: buffer_store_dword v0, off, s[0:3], 055; VI-NEXT: buffer_store_dword v1, off, s[4:7], 056; VI-NEXT: s_endpgm57 %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #158 %idx.0 = add nsw i32 %tid.x, 259 %arrayidx0 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds0, i32 0, i32 %idx.060 %val0 = load float, ptr addrspace(3) %arrayidx0, align 461 store i32 %idx.0, ptr addrspace(1) %add_use, align 462 store float %val0, ptr addrspace(1) %out63 ret void64}65 66; Make sure once the first use is folded into the addressing mode, the67; remaining add use goes through the normal shl + add constant fold.68define amdgpu_kernel void @load_shl_base_lds_1(ptr addrspace(1) %out, ptr addrspace(1) %add_use) #0 {69; CI-LABEL: load_shl_base_lds_1:70; CI: ; %bb.0:71; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x972; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v073; CI-NEXT: s_mov_b32 m0, -174; CI-NEXT: ds_read_b32 v1, v0 offset:875; CI-NEXT: s_mov_b32 s7, 0xf00076; CI-NEXT: s_mov_b32 s6, -177; CI-NEXT: s_waitcnt lgkmcnt(0)78; CI-NEXT: s_mov_b32 s4, s079; CI-NEXT: s_mov_b32 s5, s180; CI-NEXT: s_mov_b32 s0, s281; CI-NEXT: s_mov_b32 s1, s382; CI-NEXT: s_mov_b32 s2, s683; CI-NEXT: s_mov_b32 s3, s784; CI-NEXT: v_add_i32_e32 v0, vcc, 8, v085; CI-NEXT: buffer_store_dword v0, off, s[0:3], 086; CI-NEXT: buffer_store_dword v1, off, s[4:7], 087; CI-NEXT: s_endpgm88;89; VI-LABEL: load_shl_base_lds_1:90; VI: ; %bb.0:91; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2492; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v093; VI-NEXT: s_mov_b32 m0, -194; VI-NEXT: ds_read_b32 v1, v0 offset:895; VI-NEXT: s_mov_b32 s7, 0xf00096; VI-NEXT: s_mov_b32 s6, -197; VI-NEXT: s_waitcnt lgkmcnt(0)98; VI-NEXT: s_mov_b32 s4, s099; VI-NEXT: s_mov_b32 s5, s1100; VI-NEXT: s_mov_b32 s0, s2101; VI-NEXT: s_mov_b32 s1, s3102; VI-NEXT: s_mov_b32 s2, s6103; VI-NEXT: s_mov_b32 s3, s7104; VI-NEXT: v_add_u32_e32 v0, vcc, 8, v0105; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0106; VI-NEXT: buffer_store_dword v1, off, s[4:7], 0107; VI-NEXT: s_endpgm108 %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1109 %idx.0 = add nsw i32 %tid.x, 2110 %arrayidx0 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds0, i32 0, i32 %idx.0111 %val0 = load float, ptr addrspace(3) %arrayidx0, align 4112 %shl_add_use = shl i32 %idx.0, 2113 store i32 %shl_add_use, ptr addrspace(1) %add_use, align 4114 store float %val0, ptr addrspace(1) %out115 ret void116}117 118@maxlds = addrspace(3) global [65536 x i8] poison, align 4119 120define amdgpu_kernel void @load_shl_base_lds_max_offset(ptr addrspace(1) %out, ptr addrspace(3) %lds, ptr addrspace(1) %add_use) #0 {121; CI-LABEL: load_shl_base_lds_max_offset:122; CI: ; %bb.0:123; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9124; CI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd125; CI-NEXT: s_mov_b32 m0, -1126; CI-NEXT: ds_read_u8 v1, v0 offset:65535127; CI-NEXT: s_mov_b32 s3, 0xf000128; CI-NEXT: s_mov_b32 s2, -1129; CI-NEXT: s_mov_b32 s6, s2130; CI-NEXT: s_mov_b32 s7, s3131; CI-NEXT: v_add_i32_e32 v0, vcc, 0xffff, v0132; CI-NEXT: s_waitcnt lgkmcnt(0)133; CI-NEXT: buffer_store_dword v0, off, s[4:7], 0134; CI-NEXT: buffer_store_byte v1, off, s[0:3], 0135; CI-NEXT: s_endpgm136;137; VI-LABEL: load_shl_base_lds_max_offset:138; VI: ; %bb.0:139; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24140; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34141; VI-NEXT: s_mov_b32 m0, -1142; VI-NEXT: ds_read_u8 v1, v0 offset:65535143; VI-NEXT: s_mov_b32 s3, 0xf000144; VI-NEXT: s_mov_b32 s2, -1145; VI-NEXT: s_mov_b32 s6, s2146; VI-NEXT: s_mov_b32 s7, s3147; VI-NEXT: v_add_u32_e32 v0, vcc, 0xffff, v0148; VI-NEXT: s_waitcnt lgkmcnt(0)149; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0150; VI-NEXT: buffer_store_byte v1, off, s[0:3], 0151; VI-NEXT: s_endpgm152 %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1153 %idx.0 = add nsw i32 %tid.x, 65535154 %arrayidx0 = getelementptr inbounds [65536 x i8], ptr addrspace(3) @maxlds, i32 0, i32 %idx.0155 %val0 = load i8, ptr addrspace(3) %arrayidx0156 store i32 %idx.0, ptr addrspace(1) %add_use157 store i8 %val0, ptr addrspace(1) %out158 ret void159}160 161; The two globals are placed adjacent in memory, so the same base162; pointer can be used with an offset into the second one.163define amdgpu_kernel void @load_shl_base_lds_2(ptr addrspace(1) %out) #0 {164; CI-LABEL: load_shl_base_lds_2:165; CI: ; %bb.0:166; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0167; CI-NEXT: s_mov_b32 m0, -1168; CI-NEXT: ds_read2st64_b32 v[0:1], v0 offset0:1 offset1:9169; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9170; CI-NEXT: s_mov_b32 s3, 0xf000171; CI-NEXT: s_mov_b32 s2, -1172; CI-NEXT: s_waitcnt lgkmcnt(0)173; CI-NEXT: v_add_f32_e32 v0, v0, v1174; CI-NEXT: buffer_store_dword v0, off, s[0:3], 0175; CI-NEXT: s_endpgm176;177; VI-LABEL: load_shl_base_lds_2:178; VI: ; %bb.0:179; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0180; VI-NEXT: s_mov_b32 m0, -1181; VI-NEXT: ds_read2st64_b32 v[0:1], v0 offset0:1 offset1:9182; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24183; VI-NEXT: s_mov_b32 s3, 0xf000184; VI-NEXT: s_mov_b32 s2, -1185; VI-NEXT: s_waitcnt lgkmcnt(0)186; VI-NEXT: v_add_f32_e32 v0, v0, v1187; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0188; VI-NEXT: s_endpgm189 %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1190 %idx.0 = add nsw i32 %tid.x, 64191 %arrayidx0 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds0, i32 0, i32 %idx.0192 %val0 = load float, ptr addrspace(3) %arrayidx0, align 4193 %arrayidx1 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds1, i32 0, i32 %idx.0194 %val1 = load float, ptr addrspace(3) %arrayidx1, align 4195 %sum = fadd float %val0, %val1196 store float %sum, ptr addrspace(1) %out, align 4197 ret void198}199 200define amdgpu_kernel void @store_shl_base_lds_0(ptr addrspace(1) %out, ptr addrspace(1) %add_use) #0 {201; CI-LABEL: store_shl_base_lds_0:202; CI: ; %bb.0:203; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xb204; CI-NEXT: s_mov_b32 s3, 0xf000205; CI-NEXT: s_mov_b32 s2, -1206; CI-NEXT: v_add_i32_e32 v1, vcc, 2, v0207; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0208; CI-NEXT: v_mov_b32_e32 v2, 1.0209; CI-NEXT: s_mov_b32 m0, -1210; CI-NEXT: ds_write_b32 v0, v2 offset:8211; CI-NEXT: s_waitcnt lgkmcnt(0)212; CI-NEXT: buffer_store_dword v1, off, s[0:3], 0213; CI-NEXT: s_endpgm214;215; VI-LABEL: store_shl_base_lds_0:216; VI: ; %bb.0:217; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2c218; VI-NEXT: s_mov_b32 s3, 0xf000219; VI-NEXT: s_mov_b32 s2, -1220; VI-NEXT: v_add_u32_e32 v1, vcc, 2, v0221; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0222; VI-NEXT: v_mov_b32_e32 v2, 1.0223; VI-NEXT: s_mov_b32 m0, -1224; VI-NEXT: ds_write_b32 v0, v2 offset:8225; VI-NEXT: s_waitcnt lgkmcnt(0)226; VI-NEXT: buffer_store_dword v1, off, s[0:3], 0227; VI-NEXT: s_endpgm228 %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1229 %idx.0 = add nsw i32 %tid.x, 2230 %arrayidx0 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds0, i32 0, i32 %idx.0231 store float 1.0, ptr addrspace(3) %arrayidx0, align 4232 store i32 %idx.0, ptr addrspace(1) %add_use, align 4233 ret void234}235 236 237; --------------------------------------------------------------------------------238; Atomics.239 240@lds2 = addrspace(3) global [512 x i32] poison, align 4241 242; define amdgpu_kernel void @atomic_load_shl_base_lds_0(ptr addrspace(1) %out, ptr addrspace(1) %add_use) #0 {243; %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1244; %idx.0 = add nsw i32 %tid.x, 2245; %arrayidx0 = getelementptr inbounds [512 x i32], ptr addrspace(3) @lds2, i32 0, i32 %idx.0246; %val = load atomic i32, ptr addrspace(3) %arrayidx0 seq_cst, align 4247; store i32 %val, ptr addrspace(1) %out, align 4248; store i32 %idx.0, ptr addrspace(1) %add_use, align 4249; ret void250; }251 252define amdgpu_kernel void @atomic_cmpxchg_shl_base_lds_0(ptr addrspace(1) %out, ptr addrspace(1) %add_use, i32 %swap) #0 {253; CI-LABEL: atomic_cmpxchg_shl_base_lds_0:254; CI: ; %bb.0:255; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9256; CI-NEXT: s_load_dword s8, s[4:5], 0xd257; CI-NEXT: v_lshlrev_b32_e32 v1, 2, v0258; CI-NEXT: v_mov_b32_e32 v2, 7259; CI-NEXT: s_mov_b32 m0, -1260; CI-NEXT: s_mov_b32 s7, 0xf000261; CI-NEXT: s_waitcnt lgkmcnt(0)262; CI-NEXT: v_mov_b32_e32 v3, s8263; CI-NEXT: ds_cmpst_rtn_b32 v1, v1, v2, v3 offset:8264; CI-NEXT: s_waitcnt lgkmcnt(0)265; CI-NEXT: s_mov_b32 s6, -1266; CI-NEXT: s_mov_b32 s4, s0267; CI-NEXT: s_mov_b32 s5, s1268; CI-NEXT: s_mov_b32 s0, s2269; CI-NEXT: s_mov_b32 s1, s3270; CI-NEXT: s_mov_b32 s2, s6271; CI-NEXT: s_mov_b32 s3, s7272; CI-NEXT: v_add_i32_e32 v0, vcc, 2, v0273; CI-NEXT: buffer_store_dword v1, off, s[4:7], 0274; CI-NEXT: buffer_store_dword v0, off, s[0:3], 0275; CI-NEXT: s_endpgm276;277; VI-LABEL: atomic_cmpxchg_shl_base_lds_0:278; VI: ; %bb.0:279; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24280; VI-NEXT: s_load_dword s8, s[4:5], 0x34281; VI-NEXT: v_lshlrev_b32_e32 v1, 2, v0282; VI-NEXT: v_mov_b32_e32 v2, 7283; VI-NEXT: s_mov_b32 m0, -1284; VI-NEXT: s_mov_b32 s7, 0xf000285; VI-NEXT: s_waitcnt lgkmcnt(0)286; VI-NEXT: v_mov_b32_e32 v3, s8287; VI-NEXT: ds_cmpst_rtn_b32 v1, v1, v2, v3 offset:8288; VI-NEXT: s_waitcnt lgkmcnt(0)289; VI-NEXT: s_mov_b32 s6, -1290; VI-NEXT: s_mov_b32 s4, s0291; VI-NEXT: s_mov_b32 s5, s1292; VI-NEXT: s_mov_b32 s0, s2293; VI-NEXT: s_mov_b32 s1, s3294; VI-NEXT: s_mov_b32 s2, s6295; VI-NEXT: s_mov_b32 s3, s7296; VI-NEXT: v_add_u32_e32 v0, vcc, 2, v0297; VI-NEXT: buffer_store_dword v1, off, s[4:7], 0298; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0299; VI-NEXT: s_endpgm300 %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1301 %idx.0 = add nsw i32 %tid.x, 2302 %arrayidx0 = getelementptr inbounds [512 x i32], ptr addrspace(3) @lds2, i32 0, i32 %idx.0303 %pair = cmpxchg ptr addrspace(3) %arrayidx0, i32 7, i32 %swap seq_cst monotonic304 %result = extractvalue { i32, i1 } %pair, 0305 store i32 %result, ptr addrspace(1) %out, align 4306 store i32 %idx.0, ptr addrspace(1) %add_use, align 4307 ret void308}309 310define amdgpu_kernel void @atomic_swap_shl_base_lds_0(ptr addrspace(1) %out, ptr addrspace(1) %add_use) #0 {311; CI-LABEL: atomic_swap_shl_base_lds_0:312; CI: ; %bb.0:313; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9314; CI-NEXT: v_lshlrev_b32_e32 v1, 2, v0315; CI-NEXT: v_mov_b32_e32 v2, 3316; CI-NEXT: s_mov_b32 m0, -1317; CI-NEXT: s_waitcnt lgkmcnt(0)318; CI-NEXT: ds_wrxchg_rtn_b32 v1, v1, v2 offset:8319; CI-NEXT: s_waitcnt lgkmcnt(0)320; CI-NEXT: s_mov_b32 s7, 0xf000321; CI-NEXT: s_mov_b32 s6, -1322; CI-NEXT: s_mov_b32 s4, s0323; CI-NEXT: s_mov_b32 s5, s1324; CI-NEXT: s_mov_b32 s0, s2325; CI-NEXT: s_mov_b32 s1, s3326; CI-NEXT: s_mov_b32 s2, s6327; CI-NEXT: s_mov_b32 s3, s7328; CI-NEXT: v_add_i32_e32 v0, vcc, 2, v0329; CI-NEXT: buffer_store_dword v1, off, s[4:7], 0330; CI-NEXT: buffer_store_dword v0, off, s[0:3], 0331; CI-NEXT: s_endpgm332;333; VI-LABEL: atomic_swap_shl_base_lds_0:334; VI: ; %bb.0:335; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24336; VI-NEXT: v_lshlrev_b32_e32 v1, 2, v0337; VI-NEXT: v_mov_b32_e32 v2, 3338; VI-NEXT: s_mov_b32 m0, -1339; VI-NEXT: s_waitcnt lgkmcnt(0)340; VI-NEXT: ds_wrxchg_rtn_b32 v1, v1, v2 offset:8341; VI-NEXT: s_waitcnt lgkmcnt(0)342; VI-NEXT: s_mov_b32 s7, 0xf000343; VI-NEXT: s_mov_b32 s6, -1344; VI-NEXT: s_mov_b32 s4, s0345; VI-NEXT: s_mov_b32 s5, s1346; VI-NEXT: s_mov_b32 s0, s2347; VI-NEXT: s_mov_b32 s1, s3348; VI-NEXT: s_mov_b32 s2, s6349; VI-NEXT: s_mov_b32 s3, s7350; VI-NEXT: v_add_u32_e32 v0, vcc, 2, v0351; VI-NEXT: buffer_store_dword v1, off, s[4:7], 0352; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0353; VI-NEXT: s_endpgm354 %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1355 %idx.0 = add nsw i32 %tid.x, 2356 %arrayidx0 = getelementptr inbounds [512 x i32], ptr addrspace(3) @lds2, i32 0, i32 %idx.0357 %val = atomicrmw xchg ptr addrspace(3) %arrayidx0, i32 3 seq_cst358 store i32 %val, ptr addrspace(1) %out, align 4359 store i32 %idx.0, ptr addrspace(1) %add_use, align 4360 ret void361}362 363define amdgpu_kernel void @atomic_add_shl_base_lds_0(ptr addrspace(1) %out, ptr addrspace(1) %add_use) #0 {364; CI-LABEL: atomic_add_shl_base_lds_0:365; CI: ; %bb.0:366; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9367; CI-NEXT: v_lshlrev_b32_e32 v1, 2, v0368; CI-NEXT: v_mov_b32_e32 v2, 3369; CI-NEXT: s_mov_b32 m0, -1370; CI-NEXT: s_waitcnt lgkmcnt(0)371; CI-NEXT: ds_add_rtn_u32 v1, v1, v2 offset:8372; CI-NEXT: s_waitcnt lgkmcnt(0)373; CI-NEXT: s_mov_b32 s7, 0xf000374; CI-NEXT: s_mov_b32 s6, -1375; CI-NEXT: s_mov_b32 s4, s0376; CI-NEXT: s_mov_b32 s5, s1377; CI-NEXT: s_mov_b32 s0, s2378; CI-NEXT: s_mov_b32 s1, s3379; CI-NEXT: s_mov_b32 s2, s6380; CI-NEXT: s_mov_b32 s3, s7381; CI-NEXT: v_add_i32_e32 v0, vcc, 2, v0382; CI-NEXT: buffer_store_dword v1, off, s[4:7], 0383; CI-NEXT: buffer_store_dword v0, off, s[0:3], 0384; CI-NEXT: s_endpgm385;386; VI-LABEL: atomic_add_shl_base_lds_0:387; VI: ; %bb.0:388; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24389; VI-NEXT: v_lshlrev_b32_e32 v1, 2, v0390; VI-NEXT: v_mov_b32_e32 v2, 3391; VI-NEXT: s_mov_b32 m0, -1392; VI-NEXT: s_waitcnt lgkmcnt(0)393; VI-NEXT: ds_add_rtn_u32 v1, v1, v2 offset:8394; VI-NEXT: s_waitcnt lgkmcnt(0)395; VI-NEXT: s_mov_b32 s7, 0xf000396; VI-NEXT: s_mov_b32 s6, -1397; VI-NEXT: s_mov_b32 s4, s0398; VI-NEXT: s_mov_b32 s5, s1399; VI-NEXT: s_mov_b32 s0, s2400; VI-NEXT: s_mov_b32 s1, s3401; VI-NEXT: s_mov_b32 s2, s6402; VI-NEXT: s_mov_b32 s3, s7403; VI-NEXT: v_add_u32_e32 v0, vcc, 2, v0404; VI-NEXT: buffer_store_dword v1, off, s[4:7], 0405; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0406; VI-NEXT: s_endpgm407 %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1408 %idx.0 = add nsw i32 %tid.x, 2409 %arrayidx0 = getelementptr inbounds [512 x i32], ptr addrspace(3) @lds2, i32 0, i32 %idx.0410 %val = atomicrmw add ptr addrspace(3) %arrayidx0, i32 3 seq_cst411 store i32 %val, ptr addrspace(1) %out, align 4412 store i32 %idx.0, ptr addrspace(1) %add_use, align 4413 ret void414}415 416define amdgpu_kernel void @atomic_sub_shl_base_lds_0(ptr addrspace(1) %out, ptr addrspace(1) %add_use) #0 {417; CI-LABEL: atomic_sub_shl_base_lds_0:418; CI: ; %bb.0:419; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9420; CI-NEXT: v_lshlrev_b32_e32 v1, 2, v0421; CI-NEXT: v_mov_b32_e32 v2, 3422; CI-NEXT: s_mov_b32 m0, -1423; CI-NEXT: s_waitcnt lgkmcnt(0)424; CI-NEXT: ds_sub_rtn_u32 v1, v1, v2 offset:8425; CI-NEXT: s_waitcnt lgkmcnt(0)426; CI-NEXT: s_mov_b32 s7, 0xf000427; CI-NEXT: s_mov_b32 s6, -1428; CI-NEXT: s_mov_b32 s4, s0429; CI-NEXT: s_mov_b32 s5, s1430; CI-NEXT: s_mov_b32 s0, s2431; CI-NEXT: s_mov_b32 s1, s3432; CI-NEXT: s_mov_b32 s2, s6433; CI-NEXT: s_mov_b32 s3, s7434; CI-NEXT: v_add_i32_e32 v0, vcc, 2, v0435; CI-NEXT: buffer_store_dword v1, off, s[4:7], 0436; CI-NEXT: buffer_store_dword v0, off, s[0:3], 0437; CI-NEXT: s_endpgm438;439; VI-LABEL: atomic_sub_shl_base_lds_0:440; VI: ; %bb.0:441; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24442; VI-NEXT: v_lshlrev_b32_e32 v1, 2, v0443; VI-NEXT: v_mov_b32_e32 v2, 3444; VI-NEXT: s_mov_b32 m0, -1445; VI-NEXT: s_waitcnt lgkmcnt(0)446; VI-NEXT: ds_sub_rtn_u32 v1, v1, v2 offset:8447; VI-NEXT: s_waitcnt lgkmcnt(0)448; VI-NEXT: s_mov_b32 s7, 0xf000449; VI-NEXT: s_mov_b32 s6, -1450; VI-NEXT: s_mov_b32 s4, s0451; VI-NEXT: s_mov_b32 s5, s1452; VI-NEXT: s_mov_b32 s0, s2453; VI-NEXT: s_mov_b32 s1, s3454; VI-NEXT: s_mov_b32 s2, s6455; VI-NEXT: s_mov_b32 s3, s7456; VI-NEXT: v_add_u32_e32 v0, vcc, 2, v0457; VI-NEXT: buffer_store_dword v1, off, s[4:7], 0458; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0459; VI-NEXT: s_endpgm460 %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1461 %idx.0 = add nsw i32 %tid.x, 2462 %arrayidx0 = getelementptr inbounds [512 x i32], ptr addrspace(3) @lds2, i32 0, i32 %idx.0463 %val = atomicrmw sub ptr addrspace(3) %arrayidx0, i32 3 seq_cst464 store i32 %val, ptr addrspace(1) %out, align 4465 store i32 %idx.0, ptr addrspace(1) %add_use, align 4466 ret void467}468 469define amdgpu_kernel void @atomic_and_shl_base_lds_0(ptr addrspace(1) %out, ptr addrspace(1) %add_use) #0 {470; CI-LABEL: atomic_and_shl_base_lds_0:471; CI: ; %bb.0:472; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9473; CI-NEXT: v_lshlrev_b32_e32 v1, 2, v0474; CI-NEXT: v_mov_b32_e32 v2, 3475; CI-NEXT: s_mov_b32 m0, -1476; CI-NEXT: s_waitcnt lgkmcnt(0)477; CI-NEXT: ds_and_rtn_b32 v1, v1, v2 offset:8478; CI-NEXT: s_waitcnt lgkmcnt(0)479; CI-NEXT: s_mov_b32 s7, 0xf000480; CI-NEXT: s_mov_b32 s6, -1481; CI-NEXT: s_mov_b32 s4, s0482; CI-NEXT: s_mov_b32 s5, s1483; CI-NEXT: s_mov_b32 s0, s2484; CI-NEXT: s_mov_b32 s1, s3485; CI-NEXT: s_mov_b32 s2, s6486; CI-NEXT: s_mov_b32 s3, s7487; CI-NEXT: v_add_i32_e32 v0, vcc, 2, v0488; CI-NEXT: buffer_store_dword v1, off, s[4:7], 0489; CI-NEXT: buffer_store_dword v0, off, s[0:3], 0490; CI-NEXT: s_endpgm491;492; VI-LABEL: atomic_and_shl_base_lds_0:493; VI: ; %bb.0:494; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24495; VI-NEXT: v_lshlrev_b32_e32 v1, 2, v0496; VI-NEXT: v_mov_b32_e32 v2, 3497; VI-NEXT: s_mov_b32 m0, -1498; VI-NEXT: s_waitcnt lgkmcnt(0)499; VI-NEXT: ds_and_rtn_b32 v1, v1, v2 offset:8500; VI-NEXT: s_waitcnt lgkmcnt(0)501; VI-NEXT: s_mov_b32 s7, 0xf000502; VI-NEXT: s_mov_b32 s6, -1503; VI-NEXT: s_mov_b32 s4, s0504; VI-NEXT: s_mov_b32 s5, s1505; VI-NEXT: s_mov_b32 s0, s2506; VI-NEXT: s_mov_b32 s1, s3507; VI-NEXT: s_mov_b32 s2, s6508; VI-NEXT: s_mov_b32 s3, s7509; VI-NEXT: v_add_u32_e32 v0, vcc, 2, v0510; VI-NEXT: buffer_store_dword v1, off, s[4:7], 0511; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0512; VI-NEXT: s_endpgm513 %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1514 %idx.0 = add nsw i32 %tid.x, 2515 %arrayidx0 = getelementptr inbounds [512 x i32], ptr addrspace(3) @lds2, i32 0, i32 %idx.0516 %val = atomicrmw and ptr addrspace(3) %arrayidx0, i32 3 seq_cst517 store i32 %val, ptr addrspace(1) %out, align 4518 store i32 %idx.0, ptr addrspace(1) %add_use, align 4519 ret void520}521 522define amdgpu_kernel void @atomic_or_shl_base_lds_0(ptr addrspace(1) %out, ptr addrspace(1) %add_use) #0 {523; CI-LABEL: atomic_or_shl_base_lds_0:524; CI: ; %bb.0:525; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9526; CI-NEXT: v_lshlrev_b32_e32 v1, 2, v0527; CI-NEXT: v_mov_b32_e32 v2, 3528; CI-NEXT: s_mov_b32 m0, -1529; CI-NEXT: s_waitcnt lgkmcnt(0)530; CI-NEXT: ds_or_rtn_b32 v1, v1, v2 offset:8531; CI-NEXT: s_waitcnt lgkmcnt(0)532; CI-NEXT: s_mov_b32 s7, 0xf000533; CI-NEXT: s_mov_b32 s6, -1534; CI-NEXT: s_mov_b32 s4, s0535; CI-NEXT: s_mov_b32 s5, s1536; CI-NEXT: s_mov_b32 s0, s2537; CI-NEXT: s_mov_b32 s1, s3538; CI-NEXT: s_mov_b32 s2, s6539; CI-NEXT: s_mov_b32 s3, s7540; CI-NEXT: v_add_i32_e32 v0, vcc, 2, v0541; CI-NEXT: buffer_store_dword v1, off, s[4:7], 0542; CI-NEXT: buffer_store_dword v0, off, s[0:3], 0543; CI-NEXT: s_endpgm544;545; VI-LABEL: atomic_or_shl_base_lds_0:546; VI: ; %bb.0:547; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24548; VI-NEXT: v_lshlrev_b32_e32 v1, 2, v0549; VI-NEXT: v_mov_b32_e32 v2, 3550; VI-NEXT: s_mov_b32 m0, -1551; VI-NEXT: s_waitcnt lgkmcnt(0)552; VI-NEXT: ds_or_rtn_b32 v1, v1, v2 offset:8553; VI-NEXT: s_waitcnt lgkmcnt(0)554; VI-NEXT: s_mov_b32 s7, 0xf000555; VI-NEXT: s_mov_b32 s6, -1556; VI-NEXT: s_mov_b32 s4, s0557; VI-NEXT: s_mov_b32 s5, s1558; VI-NEXT: s_mov_b32 s0, s2559; VI-NEXT: s_mov_b32 s1, s3560; VI-NEXT: s_mov_b32 s2, s6561; VI-NEXT: s_mov_b32 s3, s7562; VI-NEXT: v_add_u32_e32 v0, vcc, 2, v0563; VI-NEXT: buffer_store_dword v1, off, s[4:7], 0564; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0565; VI-NEXT: s_endpgm566 %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1567 %idx.0 = add nsw i32 %tid.x, 2568 %arrayidx0 = getelementptr inbounds [512 x i32], ptr addrspace(3) @lds2, i32 0, i32 %idx.0569 %val = atomicrmw or ptr addrspace(3) %arrayidx0, i32 3 seq_cst570 store i32 %val, ptr addrspace(1) %out, align 4571 store i32 %idx.0, ptr addrspace(1) %add_use, align 4572 ret void573}574 575define amdgpu_kernel void @atomic_xor_shl_base_lds_0(ptr addrspace(1) %out, ptr addrspace(1) %add_use) #0 {576; CI-LABEL: atomic_xor_shl_base_lds_0:577; CI: ; %bb.0:578; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9579; CI-NEXT: v_lshlrev_b32_e32 v1, 2, v0580; CI-NEXT: v_mov_b32_e32 v2, 3581; CI-NEXT: s_mov_b32 m0, -1582; CI-NEXT: s_waitcnt lgkmcnt(0)583; CI-NEXT: ds_xor_rtn_b32 v1, v1, v2 offset:8584; CI-NEXT: s_waitcnt lgkmcnt(0)585; CI-NEXT: s_mov_b32 s7, 0xf000586; CI-NEXT: s_mov_b32 s6, -1587; CI-NEXT: s_mov_b32 s4, s0588; CI-NEXT: s_mov_b32 s5, s1589; CI-NEXT: s_mov_b32 s0, s2590; CI-NEXT: s_mov_b32 s1, s3591; CI-NEXT: s_mov_b32 s2, s6592; CI-NEXT: s_mov_b32 s3, s7593; CI-NEXT: v_add_i32_e32 v0, vcc, 2, v0594; CI-NEXT: buffer_store_dword v1, off, s[4:7], 0595; CI-NEXT: buffer_store_dword v0, off, s[0:3], 0596; CI-NEXT: s_endpgm597;598; VI-LABEL: atomic_xor_shl_base_lds_0:599; VI: ; %bb.0:600; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24601; VI-NEXT: v_lshlrev_b32_e32 v1, 2, v0602; VI-NEXT: v_mov_b32_e32 v2, 3603; VI-NEXT: s_mov_b32 m0, -1604; VI-NEXT: s_waitcnt lgkmcnt(0)605; VI-NEXT: ds_xor_rtn_b32 v1, v1, v2 offset:8606; VI-NEXT: s_waitcnt lgkmcnt(0)607; VI-NEXT: s_mov_b32 s7, 0xf000608; VI-NEXT: s_mov_b32 s6, -1609; VI-NEXT: s_mov_b32 s4, s0610; VI-NEXT: s_mov_b32 s5, s1611; VI-NEXT: s_mov_b32 s0, s2612; VI-NEXT: s_mov_b32 s1, s3613; VI-NEXT: s_mov_b32 s2, s6614; VI-NEXT: s_mov_b32 s3, s7615; VI-NEXT: v_add_u32_e32 v0, vcc, 2, v0616; VI-NEXT: buffer_store_dword v1, off, s[4:7], 0617; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0618; VI-NEXT: s_endpgm619 %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1620 %idx.0 = add nsw i32 %tid.x, 2621 %arrayidx0 = getelementptr inbounds [512 x i32], ptr addrspace(3) @lds2, i32 0, i32 %idx.0622 %val = atomicrmw xor ptr addrspace(3) %arrayidx0, i32 3 seq_cst623 store i32 %val, ptr addrspace(1) %out, align 4624 store i32 %idx.0, ptr addrspace(1) %add_use, align 4625 ret void626}627 628; define amdgpu_kernel void @atomic_nand_shl_base_lds_0(ptr addrspace(1) %out, ptr addrspace(1) %add_use) #0 {629; %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1630; %idx.0 = add nsw i32 %tid.x, 2631; %arrayidx0 = getelementptr inbounds [512 x i32], ptr addrspace(3) @lds2, i32 0, i32 %idx.0632; %val = atomicrmw nand ptr addrspace(3) %arrayidx0, i32 3 seq_cst633; store i32 %val, ptr addrspace(1) %out, align 4634; store i32 %idx.0, ptr addrspace(1) %add_use, align 4635; ret void636; }637 638define amdgpu_kernel void @atomic_min_shl_base_lds_0(ptr addrspace(1) %out, ptr addrspace(1) %add_use) #0 {639; CI-LABEL: atomic_min_shl_base_lds_0:640; CI: ; %bb.0:641; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9642; CI-NEXT: v_lshlrev_b32_e32 v1, 2, v0643; CI-NEXT: v_mov_b32_e32 v2, 3644; CI-NEXT: s_mov_b32 m0, -1645; CI-NEXT: s_waitcnt lgkmcnt(0)646; CI-NEXT: ds_min_rtn_i32 v1, v1, v2 offset:8647; CI-NEXT: s_waitcnt lgkmcnt(0)648; CI-NEXT: s_mov_b32 s7, 0xf000649; CI-NEXT: s_mov_b32 s6, -1650; CI-NEXT: s_mov_b32 s4, s0651; CI-NEXT: s_mov_b32 s5, s1652; CI-NEXT: s_mov_b32 s0, s2653; CI-NEXT: s_mov_b32 s1, s3654; CI-NEXT: s_mov_b32 s2, s6655; CI-NEXT: s_mov_b32 s3, s7656; CI-NEXT: v_add_i32_e32 v0, vcc, 2, v0657; CI-NEXT: buffer_store_dword v1, off, s[4:7], 0658; CI-NEXT: buffer_store_dword v0, off, s[0:3], 0659; CI-NEXT: s_endpgm660;661; VI-LABEL: atomic_min_shl_base_lds_0:662; VI: ; %bb.0:663; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24664; VI-NEXT: v_lshlrev_b32_e32 v1, 2, v0665; VI-NEXT: v_mov_b32_e32 v2, 3666; VI-NEXT: s_mov_b32 m0, -1667; VI-NEXT: s_waitcnt lgkmcnt(0)668; VI-NEXT: ds_min_rtn_i32 v1, v1, v2 offset:8669; VI-NEXT: s_waitcnt lgkmcnt(0)670; VI-NEXT: s_mov_b32 s7, 0xf000671; VI-NEXT: s_mov_b32 s6, -1672; VI-NEXT: s_mov_b32 s4, s0673; VI-NEXT: s_mov_b32 s5, s1674; VI-NEXT: s_mov_b32 s0, s2675; VI-NEXT: s_mov_b32 s1, s3676; VI-NEXT: s_mov_b32 s2, s6677; VI-NEXT: s_mov_b32 s3, s7678; VI-NEXT: v_add_u32_e32 v0, vcc, 2, v0679; VI-NEXT: buffer_store_dword v1, off, s[4:7], 0680; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0681; VI-NEXT: s_endpgm682 %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1683 %idx.0 = add nsw i32 %tid.x, 2684 %arrayidx0 = getelementptr inbounds [512 x i32], ptr addrspace(3) @lds2, i32 0, i32 %idx.0685 %val = atomicrmw min ptr addrspace(3) %arrayidx0, i32 3 seq_cst686 store i32 %val, ptr addrspace(1) %out, align 4687 store i32 %idx.0, ptr addrspace(1) %add_use, align 4688 ret void689}690 691define amdgpu_kernel void @atomic_max_shl_base_lds_0(ptr addrspace(1) %out, ptr addrspace(1) %add_use) #0 {692; CI-LABEL: atomic_max_shl_base_lds_0:693; CI: ; %bb.0:694; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9695; CI-NEXT: v_lshlrev_b32_e32 v1, 2, v0696; CI-NEXT: v_mov_b32_e32 v2, 3697; CI-NEXT: s_mov_b32 m0, -1698; CI-NEXT: s_waitcnt lgkmcnt(0)699; CI-NEXT: ds_max_rtn_i32 v1, v1, v2 offset:8700; CI-NEXT: s_waitcnt lgkmcnt(0)701; CI-NEXT: s_mov_b32 s7, 0xf000702; CI-NEXT: s_mov_b32 s6, -1703; CI-NEXT: s_mov_b32 s4, s0704; CI-NEXT: s_mov_b32 s5, s1705; CI-NEXT: s_mov_b32 s0, s2706; CI-NEXT: s_mov_b32 s1, s3707; CI-NEXT: s_mov_b32 s2, s6708; CI-NEXT: s_mov_b32 s3, s7709; CI-NEXT: v_add_i32_e32 v0, vcc, 2, v0710; CI-NEXT: buffer_store_dword v1, off, s[4:7], 0711; CI-NEXT: buffer_store_dword v0, off, s[0:3], 0712; CI-NEXT: s_endpgm713;714; VI-LABEL: atomic_max_shl_base_lds_0:715; VI: ; %bb.0:716; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24717; VI-NEXT: v_lshlrev_b32_e32 v1, 2, v0718; VI-NEXT: v_mov_b32_e32 v2, 3719; VI-NEXT: s_mov_b32 m0, -1720; VI-NEXT: s_waitcnt lgkmcnt(0)721; VI-NEXT: ds_max_rtn_i32 v1, v1, v2 offset:8722; VI-NEXT: s_waitcnt lgkmcnt(0)723; VI-NEXT: s_mov_b32 s7, 0xf000724; VI-NEXT: s_mov_b32 s6, -1725; VI-NEXT: s_mov_b32 s4, s0726; VI-NEXT: s_mov_b32 s5, s1727; VI-NEXT: s_mov_b32 s0, s2728; VI-NEXT: s_mov_b32 s1, s3729; VI-NEXT: s_mov_b32 s2, s6730; VI-NEXT: s_mov_b32 s3, s7731; VI-NEXT: v_add_u32_e32 v0, vcc, 2, v0732; VI-NEXT: buffer_store_dword v1, off, s[4:7], 0733; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0734; VI-NEXT: s_endpgm735 %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1736 %idx.0 = add nsw i32 %tid.x, 2737 %arrayidx0 = getelementptr inbounds [512 x i32], ptr addrspace(3) @lds2, i32 0, i32 %idx.0738 %val = atomicrmw max ptr addrspace(3) %arrayidx0, i32 3 seq_cst739 store i32 %val, ptr addrspace(1) %out, align 4740 store i32 %idx.0, ptr addrspace(1) %add_use, align 4741 ret void742}743 744define amdgpu_kernel void @atomic_umin_shl_base_lds_0(ptr addrspace(1) %out, ptr addrspace(1) %add_use) #0 {745; CI-LABEL: atomic_umin_shl_base_lds_0:746; CI: ; %bb.0:747; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9748; CI-NEXT: v_lshlrev_b32_e32 v1, 2, v0749; CI-NEXT: v_mov_b32_e32 v2, 3750; CI-NEXT: s_mov_b32 m0, -1751; CI-NEXT: s_waitcnt lgkmcnt(0)752; CI-NEXT: ds_min_rtn_u32 v1, v1, v2 offset:8753; CI-NEXT: s_waitcnt lgkmcnt(0)754; CI-NEXT: s_mov_b32 s7, 0xf000755; CI-NEXT: s_mov_b32 s6, -1756; CI-NEXT: s_mov_b32 s4, s0757; CI-NEXT: s_mov_b32 s5, s1758; CI-NEXT: s_mov_b32 s0, s2759; CI-NEXT: s_mov_b32 s1, s3760; CI-NEXT: s_mov_b32 s2, s6761; CI-NEXT: s_mov_b32 s3, s7762; CI-NEXT: v_add_i32_e32 v0, vcc, 2, v0763; CI-NEXT: buffer_store_dword v1, off, s[4:7], 0764; CI-NEXT: buffer_store_dword v0, off, s[0:3], 0765; CI-NEXT: s_endpgm766;767; VI-LABEL: atomic_umin_shl_base_lds_0:768; VI: ; %bb.0:769; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24770; VI-NEXT: v_lshlrev_b32_e32 v1, 2, v0771; VI-NEXT: v_mov_b32_e32 v2, 3772; VI-NEXT: s_mov_b32 m0, -1773; VI-NEXT: s_waitcnt lgkmcnt(0)774; VI-NEXT: ds_min_rtn_u32 v1, v1, v2 offset:8775; VI-NEXT: s_waitcnt lgkmcnt(0)776; VI-NEXT: s_mov_b32 s7, 0xf000777; VI-NEXT: s_mov_b32 s6, -1778; VI-NEXT: s_mov_b32 s4, s0779; VI-NEXT: s_mov_b32 s5, s1780; VI-NEXT: s_mov_b32 s0, s2781; VI-NEXT: s_mov_b32 s1, s3782; VI-NEXT: s_mov_b32 s2, s6783; VI-NEXT: s_mov_b32 s3, s7784; VI-NEXT: v_add_u32_e32 v0, vcc, 2, v0785; VI-NEXT: buffer_store_dword v1, off, s[4:7], 0786; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0787; VI-NEXT: s_endpgm788 %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1789 %idx.0 = add nsw i32 %tid.x, 2790 %arrayidx0 = getelementptr inbounds [512 x i32], ptr addrspace(3) @lds2, i32 0, i32 %idx.0791 %val = atomicrmw umin ptr addrspace(3) %arrayidx0, i32 3 seq_cst792 store i32 %val, ptr addrspace(1) %out, align 4793 store i32 %idx.0, ptr addrspace(1) %add_use, align 4794 ret void795}796 797define amdgpu_kernel void @atomic_umax_shl_base_lds_0(ptr addrspace(1) %out, ptr addrspace(1) %add_use) #0 {798; CI-LABEL: atomic_umax_shl_base_lds_0:799; CI: ; %bb.0:800; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9801; CI-NEXT: v_lshlrev_b32_e32 v1, 2, v0802; CI-NEXT: v_mov_b32_e32 v2, 3803; CI-NEXT: s_mov_b32 m0, -1804; CI-NEXT: s_waitcnt lgkmcnt(0)805; CI-NEXT: ds_max_rtn_u32 v1, v1, v2 offset:8806; CI-NEXT: s_waitcnt lgkmcnt(0)807; CI-NEXT: s_mov_b32 s7, 0xf000808; CI-NEXT: s_mov_b32 s6, -1809; CI-NEXT: s_mov_b32 s4, s0810; CI-NEXT: s_mov_b32 s5, s1811; CI-NEXT: s_mov_b32 s0, s2812; CI-NEXT: s_mov_b32 s1, s3813; CI-NEXT: s_mov_b32 s2, s6814; CI-NEXT: s_mov_b32 s3, s7815; CI-NEXT: v_add_i32_e32 v0, vcc, 2, v0816; CI-NEXT: buffer_store_dword v1, off, s[4:7], 0817; CI-NEXT: buffer_store_dword v0, off, s[0:3], 0818; CI-NEXT: s_endpgm819;820; VI-LABEL: atomic_umax_shl_base_lds_0:821; VI: ; %bb.0:822; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24823; VI-NEXT: v_lshlrev_b32_e32 v1, 2, v0824; VI-NEXT: v_mov_b32_e32 v2, 3825; VI-NEXT: s_mov_b32 m0, -1826; VI-NEXT: s_waitcnt lgkmcnt(0)827; VI-NEXT: ds_max_rtn_u32 v1, v1, v2 offset:8828; VI-NEXT: s_waitcnt lgkmcnt(0)829; VI-NEXT: s_mov_b32 s7, 0xf000830; VI-NEXT: s_mov_b32 s6, -1831; VI-NEXT: s_mov_b32 s4, s0832; VI-NEXT: s_mov_b32 s5, s1833; VI-NEXT: s_mov_b32 s0, s2834; VI-NEXT: s_mov_b32 s1, s3835; VI-NEXT: s_mov_b32 s2, s6836; VI-NEXT: s_mov_b32 s3, s7837; VI-NEXT: v_add_u32_e32 v0, vcc, 2, v0838; VI-NEXT: buffer_store_dword v1, off, s[4:7], 0839; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0840; VI-NEXT: s_endpgm841 %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1842 %idx.0 = add nsw i32 %tid.x, 2843 %arrayidx0 = getelementptr inbounds [512 x i32], ptr addrspace(3) @lds2, i32 0, i32 %idx.0844 %val = atomicrmw umax ptr addrspace(3) %arrayidx0, i32 3 seq_cst845 store i32 %val, ptr addrspace(1) %out, align 4846 store i32 %idx.0, ptr addrspace(1) %add_use, align 4847 ret void848}849 850define amdgpu_kernel void @atomic_inc_shl_base_lds_0(ptr addrspace(1) %out, ptr addrspace(1) %add_use) #0 {851; CI-LABEL: atomic_inc_shl_base_lds_0:852; CI: ; %bb.0:853; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9854; CI-NEXT: v_lshlrev_b32_e32 v1, 2, v0855; CI-NEXT: v_mov_b32_e32 v2, 31856; CI-NEXT: s_mov_b32 m0, -1857; CI-NEXT: s_waitcnt lgkmcnt(0)858; CI-NEXT: ds_inc_rtn_u32 v1, v1, v2 offset:8859; CI-NEXT: s_waitcnt lgkmcnt(0)860; CI-NEXT: s_mov_b32 s7, 0xf000861; CI-NEXT: s_mov_b32 s6, -1862; CI-NEXT: s_mov_b32 s4, s0863; CI-NEXT: s_mov_b32 s5, s1864; CI-NEXT: s_mov_b32 s0, s2865; CI-NEXT: s_mov_b32 s1, s3866; CI-NEXT: s_mov_b32 s2, s6867; CI-NEXT: s_mov_b32 s3, s7868; CI-NEXT: v_add_i32_e32 v0, vcc, 2, v0869; CI-NEXT: buffer_store_dword v1, off, s[4:7], 0870; CI-NEXT: buffer_store_dword v0, off, s[0:3], 0871; CI-NEXT: s_endpgm872;873; VI-LABEL: atomic_inc_shl_base_lds_0:874; VI: ; %bb.0:875; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24876; VI-NEXT: v_lshlrev_b32_e32 v1, 2, v0877; VI-NEXT: v_mov_b32_e32 v2, 31878; VI-NEXT: s_mov_b32 m0, -1879; VI-NEXT: s_waitcnt lgkmcnt(0)880; VI-NEXT: ds_inc_rtn_u32 v1, v1, v2 offset:8881; VI-NEXT: s_waitcnt lgkmcnt(0)882; VI-NEXT: s_mov_b32 s7, 0xf000883; VI-NEXT: s_mov_b32 s6, -1884; VI-NEXT: s_mov_b32 s4, s0885; VI-NEXT: s_mov_b32 s5, s1886; VI-NEXT: s_mov_b32 s0, s2887; VI-NEXT: s_mov_b32 s1, s3888; VI-NEXT: s_mov_b32 s2, s6889; VI-NEXT: s_mov_b32 s3, s7890; VI-NEXT: v_add_u32_e32 v0, vcc, 2, v0891; VI-NEXT: buffer_store_dword v1, off, s[4:7], 0892; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0893; VI-NEXT: s_endpgm894 %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1895 %idx.0 = add nsw i32 %tid.x, 2896 %arrayidx0 = getelementptr inbounds [512 x i32], ptr addrspace(3) @lds2, i32 0, i32 %idx.0897 %val = atomicrmw uinc_wrap ptr addrspace(3) %arrayidx0, i32 31 seq_cst898 store i32 %val, ptr addrspace(1) %out, align 4899 store i32 %idx.0, ptr addrspace(1) %add_use, align 4900 ret void901}902 903define amdgpu_kernel void @atomic_dec_shl_base_lds_0(ptr addrspace(1) %out, ptr addrspace(1) %add_use) #0 {904; CI-LABEL: atomic_dec_shl_base_lds_0:905; CI: ; %bb.0:906; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9907; CI-NEXT: v_lshlrev_b32_e32 v1, 2, v0908; CI-NEXT: v_mov_b32_e32 v2, 31909; CI-NEXT: s_mov_b32 m0, -1910; CI-NEXT: s_waitcnt lgkmcnt(0)911; CI-NEXT: ds_dec_rtn_u32 v1, v1, v2 offset:8912; CI-NEXT: s_waitcnt lgkmcnt(0)913; CI-NEXT: s_mov_b32 s7, 0xf000914; CI-NEXT: s_mov_b32 s6, -1915; CI-NEXT: s_mov_b32 s4, s0916; CI-NEXT: s_mov_b32 s5, s1917; CI-NEXT: s_mov_b32 s0, s2918; CI-NEXT: s_mov_b32 s1, s3919; CI-NEXT: s_mov_b32 s2, s6920; CI-NEXT: s_mov_b32 s3, s7921; CI-NEXT: v_add_i32_e32 v0, vcc, 2, v0922; CI-NEXT: buffer_store_dword v1, off, s[4:7], 0923; CI-NEXT: buffer_store_dword v0, off, s[0:3], 0924; CI-NEXT: s_endpgm925;926; VI-LABEL: atomic_dec_shl_base_lds_0:927; VI: ; %bb.0:928; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24929; VI-NEXT: v_lshlrev_b32_e32 v1, 2, v0930; VI-NEXT: v_mov_b32_e32 v2, 31931; VI-NEXT: s_mov_b32 m0, -1932; VI-NEXT: s_waitcnt lgkmcnt(0)933; VI-NEXT: ds_dec_rtn_u32 v1, v1, v2 offset:8934; VI-NEXT: s_waitcnt lgkmcnt(0)935; VI-NEXT: s_mov_b32 s7, 0xf000936; VI-NEXT: s_mov_b32 s6, -1937; VI-NEXT: s_mov_b32 s4, s0938; VI-NEXT: s_mov_b32 s5, s1939; VI-NEXT: s_mov_b32 s0, s2940; VI-NEXT: s_mov_b32 s1, s3941; VI-NEXT: s_mov_b32 s2, s6942; VI-NEXT: s_mov_b32 s3, s7943; VI-NEXT: v_add_u32_e32 v0, vcc, 2, v0944; VI-NEXT: buffer_store_dword v1, off, s[4:7], 0945; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0946; VI-NEXT: s_endpgm947 %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1948 %idx.0 = add nsw i32 %tid.x, 2949 %arrayidx0 = getelementptr inbounds [512 x i32], ptr addrspace(3) @lds2, i32 0, i32 %idx.0950 %val = atomicrmw udec_wrap ptr addrspace(3) %arrayidx0, i32 31 seq_cst951 store i32 %val, ptr addrspace(1) %out, align 4952 store i32 %idx.0, ptr addrspace(1) %add_use, align 4953 ret void954}955 956define void @shl_add_ptr_combine_2use_lds(i32 %idx) #0 {957; GCN-LABEL: shl_add_ptr_combine_2use_lds:958; GCN: ; %bb.0:959; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)960; GCN-NEXT: v_lshlrev_b32_e32 v1, 3, v0961; GCN-NEXT: v_mov_b32_e32 v2, 9962; GCN-NEXT: s_mov_b32 m0, -1963; GCN-NEXT: v_lshlrev_b32_e32 v0, 4, v0964; GCN-NEXT: ds_write_b32 v1, v2 offset:32965; GCN-NEXT: v_mov_b32_e32 v1, 10966; GCN-NEXT: ds_write_b32 v0, v1 offset:64967; GCN-NEXT: s_waitcnt lgkmcnt(0)968; GCN-NEXT: s_setpc_b64 s[30:31]969 %idx.add = add nuw i32 %idx, 4970 %shl0 = shl i32 %idx.add, 3971 %shl1 = shl i32 %idx.add, 4972 %ptr0 = inttoptr i32 %shl0 to ptr addrspace(3)973 %ptr1 = inttoptr i32 %shl1 to ptr addrspace(3)974 store volatile i32 9, ptr addrspace(3) %ptr0975 store volatile i32 10, ptr addrspace(3) %ptr1976 ret void977}978 979define void @shl_add_ptr_combine_2use_max_lds_offset(i32 %idx) #0 {980; CI-LABEL: shl_add_ptr_combine_2use_max_lds_offset:981; CI: ; %bb.0:982; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)983; CI-NEXT: v_lshlrev_b32_e32 v1, 4, v0984; CI-NEXT: v_lshlrev_b32_e32 v0, 3, v0985; CI-NEXT: v_mov_b32_e32 v2, 9986; CI-NEXT: s_mov_b32 m0, -1987; CI-NEXT: v_add_i32_e32 v1, vcc, 0x1fff0, v1988; CI-NEXT: ds_write_b32 v0, v2 offset:65528989; CI-NEXT: v_mov_b32_e32 v0, 10990; CI-NEXT: ds_write_b32 v1, v0991; CI-NEXT: s_waitcnt lgkmcnt(0)992; CI-NEXT: s_setpc_b64 s[30:31]993;994; VI-LABEL: shl_add_ptr_combine_2use_max_lds_offset:995; VI: ; %bb.0:996; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)997; VI-NEXT: v_lshlrev_b32_e32 v1, 4, v0998; VI-NEXT: v_lshlrev_b32_e32 v0, 3, v0999; VI-NEXT: v_mov_b32_e32 v2, 91000; VI-NEXT: s_mov_b32 m0, -11001; VI-NEXT: v_add_u32_e32 v1, vcc, 0x1fff0, v11002; VI-NEXT: ds_write_b32 v0, v2 offset:655281003; VI-NEXT: v_mov_b32_e32 v0, 101004; VI-NEXT: ds_write_b32 v1, v01005; VI-NEXT: s_waitcnt lgkmcnt(0)1006; VI-NEXT: s_setpc_b64 s[30:31]1007 %idx.add = add nuw i32 %idx, 81911008 %shl0 = shl i32 %idx.add, 31009 %shl1 = shl i32 %idx.add, 41010 %ptr0 = inttoptr i32 %shl0 to ptr addrspace(3)1011 %ptr1 = inttoptr i32 %shl1 to ptr addrspace(3)1012 store volatile i32 9, ptr addrspace(3) %ptr01013 store volatile i32 10, ptr addrspace(3) %ptr11014 ret void1015}1016 1017define void @shl_add_ptr_combine_2use_both_max_lds_offset(i32 %idx) #0 {1018; CI-LABEL: shl_add_ptr_combine_2use_both_max_lds_offset:1019; CI: ; %bb.0:1020; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1021; CI-NEXT: v_add_i32_e32 v0, vcc, 0x1000, v01022; CI-NEXT: v_lshlrev_b32_e32 v1, 4, v01023; CI-NEXT: v_mov_b32_e32 v2, 91024; CI-NEXT: s_mov_b32 m0, -11025; CI-NEXT: v_lshlrev_b32_e32 v0, 5, v01026; CI-NEXT: ds_write_b32 v1, v21027; CI-NEXT: v_mov_b32_e32 v1, 101028; CI-NEXT: ds_write_b32 v0, v11029; CI-NEXT: s_waitcnt lgkmcnt(0)1030; CI-NEXT: s_setpc_b64 s[30:31]1031;1032; VI-LABEL: shl_add_ptr_combine_2use_both_max_lds_offset:1033; VI: ; %bb.0:1034; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1035; VI-NEXT: v_add_u32_e32 v0, vcc, 0x1000, v01036; VI-NEXT: v_lshlrev_b32_e32 v1, 4, v01037; VI-NEXT: v_mov_b32_e32 v2, 91038; VI-NEXT: s_mov_b32 m0, -11039; VI-NEXT: v_lshlrev_b32_e32 v0, 5, v01040; VI-NEXT: ds_write_b32 v1, v21041; VI-NEXT: v_mov_b32_e32 v1, 101042; VI-NEXT: ds_write_b32 v0, v11043; VI-NEXT: s_waitcnt lgkmcnt(0)1044; VI-NEXT: s_setpc_b64 s[30:31]1045 %idx.add = add nuw i32 %idx, 40961046 %shl0 = shl i32 %idx.add, 41047 %shl1 = shl i32 %idx.add, 51048 %ptr0 = inttoptr i32 %shl0 to ptr addrspace(3)1049 %ptr1 = inttoptr i32 %shl1 to ptr addrspace(3)1050 store volatile i32 9, ptr addrspace(3) %ptr01051 store volatile i32 10, ptr addrspace(3) %ptr11052 ret void1053}1054 1055define void @shl_add_ptr_combine_2use_private(i16 zeroext %idx.arg) #0 {1056; GCN-LABEL: shl_add_ptr_combine_2use_private:1057; GCN: ; %bb.0:1058; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1059; GCN-NEXT: v_lshlrev_b32_e32 v1, 2, v01060; GCN-NEXT: v_mov_b32_e32 v2, 91061; GCN-NEXT: v_lshlrev_b32_e32 v0, 3, v01062; GCN-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen offset:161063; GCN-NEXT: s_waitcnt vmcnt(0)1064; GCN-NEXT: v_mov_b32_e32 v1, 101065; GCN-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:321066; GCN-NEXT: s_waitcnt vmcnt(0)1067; GCN-NEXT: s_setpc_b64 s[30:31]1068 %idx = zext i16 %idx.arg to i321069 %idx.add = add nuw i32 %idx, 41070 %shl0 = shl i32 %idx.add, 21071 %shl1 = shl i32 %idx.add, 31072 %ptr0 = inttoptr i32 %shl0 to ptr addrspace(5)1073 %ptr1 = inttoptr i32 %shl1 to ptr addrspace(5)1074 store volatile i32 9, ptr addrspace(5) %ptr01075 store volatile i32 10, ptr addrspace(5) %ptr11076 ret void1077}1078 1079define void @shl_add_ptr_combine_2use_max_private_offset(i16 zeroext %idx.arg) #0 {1080; CI-LABEL: shl_add_ptr_combine_2use_max_private_offset:1081; CI: ; %bb.0:1082; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1083; CI-NEXT: v_lshlrev_b32_e32 v1, 4, v01084; CI-NEXT: v_lshlrev_b32_e32 v0, 3, v01085; CI-NEXT: v_mov_b32_e32 v2, 91086; CI-NEXT: v_add_i32_e32 v1, vcc, 0x1ff0, v11087; CI-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:40881088; CI-NEXT: s_waitcnt vmcnt(0)1089; CI-NEXT: v_mov_b32_e32 v0, 101090; CI-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen1091; CI-NEXT: s_waitcnt vmcnt(0)1092; CI-NEXT: s_setpc_b64 s[30:31]1093;1094; VI-LABEL: shl_add_ptr_combine_2use_max_private_offset:1095; VI: ; %bb.0:1096; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1097; VI-NEXT: v_lshlrev_b32_e32 v1, 4, v01098; VI-NEXT: v_lshlrev_b32_e32 v0, 3, v01099; VI-NEXT: v_mov_b32_e32 v2, 91100; VI-NEXT: v_add_u32_e32 v1, vcc, 0x1ff0, v11101; VI-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:40881102; VI-NEXT: s_waitcnt vmcnt(0)1103; VI-NEXT: v_mov_b32_e32 v0, 101104; VI-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen1105; VI-NEXT: s_waitcnt vmcnt(0)1106; VI-NEXT: s_setpc_b64 s[30:31]1107 %idx = zext i16 %idx.arg to i321108 %idx.add = add nuw i32 %idx, 5111109 %shl0 = shl i32 %idx.add, 31110 %shl1 = shl i32 %idx.add, 41111 %ptr0 = inttoptr i32 %shl0 to ptr addrspace(5)1112 %ptr1 = inttoptr i32 %shl1 to ptr addrspace(5)1113 store volatile i32 9, ptr addrspace(5) %ptr01114 store volatile i32 10, ptr addrspace(5) %ptr11115 ret void1116}1117 1118define void @shl_add_ptr_combine_2use_both_max_private_offset(i16 zeroext %idx.arg) #0 {1119; CI-LABEL: shl_add_ptr_combine_2use_both_max_private_offset:1120; CI: ; %bb.0:1121; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1122; CI-NEXT: v_add_i32_e32 v0, vcc, 0x100, v01123; CI-NEXT: v_lshlrev_b32_e32 v1, 4, v01124; CI-NEXT: v_mov_b32_e32 v2, 91125; CI-NEXT: v_lshlrev_b32_e32 v0, 5, v01126; CI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen1127; CI-NEXT: s_waitcnt vmcnt(0)1128; CI-NEXT: v_mov_b32_e32 v1, 101129; CI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen1130; CI-NEXT: s_waitcnt vmcnt(0)1131; CI-NEXT: s_setpc_b64 s[30:31]1132;1133; VI-LABEL: shl_add_ptr_combine_2use_both_max_private_offset:1134; VI: ; %bb.0:1135; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1136; VI-NEXT: v_add_u32_e32 v0, vcc, 0x100, v01137; VI-NEXT: v_lshlrev_b32_e32 v1, 4, v01138; VI-NEXT: v_mov_b32_e32 v2, 91139; VI-NEXT: v_lshlrev_b32_e32 v0, 5, v01140; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen1141; VI-NEXT: s_waitcnt vmcnt(0)1142; VI-NEXT: v_mov_b32_e32 v1, 101143; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen1144; VI-NEXT: s_waitcnt vmcnt(0)1145; VI-NEXT: s_setpc_b64 s[30:31]1146 %idx = zext i16 %idx.arg to i321147 %idx.add = add nuw i32 %idx, 2561148 %shl0 = shl i32 %idx.add, 41149 %shl1 = shl i32 %idx.add, 51150 %ptr0 = inttoptr i32 %shl0 to ptr addrspace(5)1151 %ptr1 = inttoptr i32 %shl1 to ptr addrspace(5)1152 store volatile i32 9, ptr addrspace(5) %ptr01153 store volatile i32 10, ptr addrspace(5) %ptr11154 ret void1155}1156 1157define void @shl_or_ptr_combine_2use_lds(i32 %idx) #0 {1158; GCN-LABEL: shl_or_ptr_combine_2use_lds:1159; GCN: ; %bb.0:1160; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1161; GCN-NEXT: v_lshlrev_b32_e32 v1, 1, v01162; GCN-NEXT: v_lshlrev_b32_e32 v0, 4, v01163; GCN-NEXT: v_mov_b32_e32 v2, 91164; GCN-NEXT: s_mov_b32 m0, -11165; GCN-NEXT: v_lshlrev_b32_e32 v1, 4, v11166; GCN-NEXT: ds_write_b32 v0, v2 offset:81167; GCN-NEXT: v_mov_b32_e32 v0, 101168; GCN-NEXT: ds_write_b32 v1, v0 offset:161169; GCN-NEXT: s_waitcnt lgkmcnt(0)1170; GCN-NEXT: s_setpc_b64 s[30:31]1171 %idx.shl = shl i32 %idx, 11172 %idx.add = or i32 %idx.shl, 11173 %shl0 = shl i32 %idx.add, 31174 %shl1 = shl i32 %idx.add, 41175 %ptr0 = inttoptr i32 %shl0 to ptr addrspace(3)1176 %ptr1 = inttoptr i32 %shl1 to ptr addrspace(3)1177 store volatile i32 9, ptr addrspace(3) %ptr01178 store volatile i32 10, ptr addrspace(3) %ptr11179 ret void1180}1181 1182define void @shl_or_ptr_not_combine_2use_lds(i32 %idx) #0 {1183; GCN-LABEL: shl_or_ptr_not_combine_2use_lds:1184; GCN: ; %bb.0:1185; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1186; GCN-NEXT: v_or_b32_e32 v0, 1, v01187; GCN-NEXT: v_lshlrev_b32_e32 v1, 3, v01188; GCN-NEXT: v_mov_b32_e32 v2, 91189; GCN-NEXT: s_mov_b32 m0, -11190; GCN-NEXT: v_lshlrev_b32_e32 v0, 4, v01191; GCN-NEXT: ds_write_b32 v1, v21192; GCN-NEXT: v_mov_b32_e32 v1, 101193; GCN-NEXT: ds_write_b32 v0, v11194; GCN-NEXT: s_waitcnt lgkmcnt(0)1195; GCN-NEXT: s_setpc_b64 s[30:31]1196 %idx.add = or i32 %idx, 11197 %shl0 = shl i32 %idx.add, 31198 %shl1 = shl i32 %idx.add, 41199 %ptr0 = inttoptr i32 %shl0 to ptr addrspace(3)1200 %ptr1 = inttoptr i32 %shl1 to ptr addrspace(3)1201 store volatile i32 9, ptr addrspace(3) %ptr01202 store volatile i32 10, ptr addrspace(3) %ptr11203 ret void1204}1205 1206attributes #0 = { nounwind }1207attributes #1 = { nounwind readnone }1208