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1; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 < %s | FileCheck -enable-var-scope --check-prefix=GCN %s2 3; GCN-LABEL: {{^}}shl_base_atomicrmw_global_atomic_csub_ptr:4; GCN-DAG: v_lshlrev_b64 v[[[LO:[0-9]+]]:[[HI:[0-9]+]]], 2, v[4:5]5; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 436; GCN: v_add_co_u32 v[[EXTRA_LO:[0-9]+]], vcc_lo, 0x80, v47; GCN: v_add_co_ci_u32_e64 v[[EXTRA_HI:[0-9]+]], null, 0, v5, vcc_lo8; GCN: global_atomic_csub v{{[0-9]+}}, v[[[LO]]:[[HI]]], [[K]], off offset:512 glc9; GCN: global_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v[[[EXTRA_LO]]:[[EXTRA_HI]]]10define i32 @shl_base_atomicrmw_global_atomic_csub_ptr(ptr addrspace(1) %out, ptr addrspace(1) %extra.use, ptr addrspace(1) %ptr) #0 {11 %arrayidx0 = getelementptr inbounds [512 x i32], ptr addrspace(1) %ptr, i64 0, i64 3212 %cast = ptrtoint ptr addrspace(1) %arrayidx0 to i6413 %shl = shl i64 %cast, 214 %castback = inttoptr i64 %shl to ptr addrspace(1)15 %val = call i32 @llvm.amdgcn.global.atomic.csub.p1(ptr addrspace(1) %castback, i32 43)16 store volatile i64 %cast, ptr addrspace(1) %extra.use, align 417 ret i32 %val18}19 20declare i32 @llvm.amdgcn.global.atomic.csub.p1(ptr addrspace(1) nocapture, i32) #021 22attributes #0 = { argmemonly nounwind }23