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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=fiji | FileCheck -check-prefix=VI %s3; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 | FileCheck -check-prefix=GFX9 %s4; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 | FileCheck -check-prefix=GFX10 %s5; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 | FileCheck -check-prefix=GFX10 %s6 7; ===================================================================================8; V_LSHL_OR_B329; ===================================================================================10 11define amdgpu_ps float @shl_or(i32 %a, i32 %b, i32 %c) {12; VI-LABEL: shl_or:13; VI: ; %bb.0:14; VI-NEXT: v_lshlrev_b32_e32 v0, v1, v015; VI-NEXT: v_or_b32_e32 v0, v0, v216; VI-NEXT: ; return to shader part epilog17;18; GFX9-LABEL: shl_or:19; GFX9: ; %bb.0:20; GFX9-NEXT: v_lshl_or_b32 v0, v0, v1, v221; GFX9-NEXT: ; return to shader part epilog22;23; GFX10-LABEL: shl_or:24; GFX10: ; %bb.0:25; GFX10-NEXT: v_lshl_or_b32 v0, v0, v1, v226; GFX10-NEXT: ; return to shader part epilog27 %x = shl i32 %a, %b28 %result = or i32 %x, %c29 %bc = bitcast i32 %result to float30 ret float %bc31}32 33define amdgpu_ps float @shl_or_vgpr_c(i32 inreg %a, i32 inreg %b, i32 %c) {34; VI-LABEL: shl_or_vgpr_c:35; VI: ; %bb.0:36; VI-NEXT: s_lshl_b32 s0, s2, s337; VI-NEXT: v_or_b32_e32 v0, s0, v038; VI-NEXT: ; return to shader part epilog39;40; GFX9-LABEL: shl_or_vgpr_c:41; GFX9: ; %bb.0:42; GFX9-NEXT: s_lshl_b32 s0, s2, s343; GFX9-NEXT: v_or_b32_e32 v0, s0, v044; GFX9-NEXT: ; return to shader part epilog45;46; GFX10-LABEL: shl_or_vgpr_c:47; GFX10: ; %bb.0:48; GFX10-NEXT: v_lshl_or_b32 v0, s2, s3, v049; GFX10-NEXT: ; return to shader part epilog50 %x = shl i32 %a, %b51 %result = or i32 %x, %c52 %bc = bitcast i32 %result to float53 ret float %bc54}55 56define amdgpu_ps float @shl_or_vgpr_all2(i32 %a, i32 %b, i32 %c) {57; VI-LABEL: shl_or_vgpr_all2:58; VI: ; %bb.0:59; VI-NEXT: v_lshlrev_b32_e32 v0, v1, v060; VI-NEXT: v_or_b32_e32 v0, v2, v061; VI-NEXT: ; return to shader part epilog62;63; GFX9-LABEL: shl_or_vgpr_all2:64; GFX9: ; %bb.0:65; GFX9-NEXT: v_lshl_or_b32 v0, v0, v1, v266; GFX9-NEXT: ; return to shader part epilog67;68; GFX10-LABEL: shl_or_vgpr_all2:69; GFX10: ; %bb.0:70; GFX10-NEXT: v_lshl_or_b32 v0, v0, v1, v271; GFX10-NEXT: ; return to shader part epilog72 %x = shl i32 %a, %b73 %result = or i32 %c, %x74 %bc = bitcast i32 %result to float75 ret float %bc76}77 78define amdgpu_ps float @shl_or_vgpr_ac(i32 %a, i32 inreg %b, i32 %c) {79; VI-LABEL: shl_or_vgpr_ac:80; VI: ; %bb.0:81; VI-NEXT: v_lshlrev_b32_e32 v0, s2, v082; VI-NEXT: v_or_b32_e32 v0, v0, v183; VI-NEXT: ; return to shader part epilog84;85; GFX9-LABEL: shl_or_vgpr_ac:86; GFX9: ; %bb.0:87; GFX9-NEXT: v_lshl_or_b32 v0, v0, s2, v188; GFX9-NEXT: ; return to shader part epilog89;90; GFX10-LABEL: shl_or_vgpr_ac:91; GFX10: ; %bb.0:92; GFX10-NEXT: v_lshl_or_b32 v0, v0, s2, v193; GFX10-NEXT: ; return to shader part epilog94 %x = shl i32 %a, %b95 %result = or i32 %x, %c96 %bc = bitcast i32 %result to float97 ret float %bc98}99 100define amdgpu_ps float @shl_or_vgpr_const(i32 %a, i32 %b) {101; VI-LABEL: shl_or_vgpr_const:102; VI: ; %bb.0:103; VI-NEXT: v_lshlrev_b32_e32 v0, v1, v0104; VI-NEXT: v_or_b32_e32 v0, 6, v0105; VI-NEXT: ; return to shader part epilog106;107; GFX9-LABEL: shl_or_vgpr_const:108; GFX9: ; %bb.0:109; GFX9-NEXT: v_lshl_or_b32 v0, v0, v1, 6110; GFX9-NEXT: ; return to shader part epilog111;112; GFX10-LABEL: shl_or_vgpr_const:113; GFX10: ; %bb.0:114; GFX10-NEXT: v_lshl_or_b32 v0, v0, v1, 6115; GFX10-NEXT: ; return to shader part epilog116 %x = shl i32 %a, %b117 %result = or i32 %x, 6118 %bc = bitcast i32 %result to float119 ret float %bc120}121 122define amdgpu_ps float @shl_or_vgpr_const2(i32 %a, i32 %b) {123; VI-LABEL: shl_or_vgpr_const2:124; VI: ; %bb.0:125; VI-NEXT: v_lshlrev_b32_e32 v0, 6, v0126; VI-NEXT: v_or_b32_e32 v0, v0, v1127; VI-NEXT: ; return to shader part epilog128;129; GFX9-LABEL: shl_or_vgpr_const2:130; GFX9: ; %bb.0:131; GFX9-NEXT: v_lshl_or_b32 v0, v0, 6, v1132; GFX9-NEXT: ; return to shader part epilog133;134; GFX10-LABEL: shl_or_vgpr_const2:135; GFX10: ; %bb.0:136; GFX10-NEXT: v_lshl_or_b32 v0, v0, 6, v1137; GFX10-NEXT: ; return to shader part epilog138 %x = shl i32 %a, 6139 %result = or i32 %x, %b140 %bc = bitcast i32 %result to float141 ret float %bc142}143 144define amdgpu_ps float @shl_or_vgpr_const_scalar1(i32 inreg %a, i32 %b) {145; VI-LABEL: shl_or_vgpr_const_scalar1:146; VI: ; %bb.0:147; VI-NEXT: s_lshl_b32 s0, s2, 6148; VI-NEXT: v_or_b32_e32 v0, s0, v0149; VI-NEXT: ; return to shader part epilog150;151; GFX9-LABEL: shl_or_vgpr_const_scalar1:152; GFX9: ; %bb.0:153; GFX9-NEXT: v_lshl_or_b32 v0, s2, 6, v0154; GFX9-NEXT: ; return to shader part epilog155;156; GFX10-LABEL: shl_or_vgpr_const_scalar1:157; GFX10: ; %bb.0:158; GFX10-NEXT: v_lshl_or_b32 v0, s2, 6, v0159; GFX10-NEXT: ; return to shader part epilog160 %x = shl i32 %a, 6161 %result = or i32 %x, %b162 %bc = bitcast i32 %result to float163 ret float %bc164}165 166define amdgpu_ps float @shl_or_vgpr_const_scalar2(i32 %a, i32 inreg %b) {167; VI-LABEL: shl_or_vgpr_const_scalar2:168; VI: ; %bb.0:169; VI-NEXT: v_lshlrev_b32_e32 v0, 6, v0170; VI-NEXT: v_or_b32_e32 v0, s2, v0171; VI-NEXT: ; return to shader part epilog172;173; GFX9-LABEL: shl_or_vgpr_const_scalar2:174; GFX9: ; %bb.0:175; GFX9-NEXT: v_lshl_or_b32 v0, v0, 6, s2176; GFX9-NEXT: ; return to shader part epilog177;178; GFX10-LABEL: shl_or_vgpr_const_scalar2:179; GFX10: ; %bb.0:180; GFX10-NEXT: v_lshl_or_b32 v0, v0, 6, s2181; GFX10-NEXT: ; return to shader part epilog182 %x = shl i32 %a, 6183 %result = or i32 %x, %b184 %bc = bitcast i32 %result to float185 ret float %bc186}187