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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=amdgcn -mcpu=verde | FileCheck --check-prefix=SI %s3; RUN: llc < %s -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global | FileCheck --check-prefix=FLAT %s4 5define amdgpu_kernel void @break_inserted_outside_of_loop(ptr addrspace(1) %out, i32 %a) {6; SI-LABEL: break_inserted_outside_of_loop:7; SI: ; %bb.0: ; %main_body8; SI-NEXT: s_load_dword s0, s[4:5], 0xb9; SI-NEXT: v_mbcnt_lo_u32_b32_e64 v0, -1, 010; SI-NEXT: s_waitcnt lgkmcnt(0)11; SI-NEXT: v_and_b32_e32 v0, s0, v012; SI-NEXT: v_and_b32_e32 v0, 1, v013; SI-NEXT: v_cmp_eq_u32_e32 vcc, 1, v014; SI-NEXT: s_mov_b64 s[0:1], 015; SI-NEXT: .LBB0_1: ; %ENDIF16; SI-NEXT: ; =>This Inner Loop Header: Depth=117; SI-NEXT: s_and_b64 s[2:3], exec, vcc18; SI-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1]19; SI-NEXT: s_andn2_b64 exec, exec, s[0:1]20; SI-NEXT: s_cbranch_execnz .LBB0_121; SI-NEXT: ; %bb.2: ; %ENDLOOP22; SI-NEXT: s_or_b64 exec, exec, s[0:1]23; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x924; SI-NEXT: s_mov_b32 s3, 0xf00025; SI-NEXT: s_mov_b32 s2, -126; SI-NEXT: v_mov_b32_e32 v0, 027; SI-NEXT: s_waitcnt lgkmcnt(0)28; SI-NEXT: buffer_store_dword v0, off, s[0:3], 029; SI-NEXT: s_endpgm30;31; FLAT-LABEL: break_inserted_outside_of_loop:32; FLAT: ; %bb.0: ; %main_body33; FLAT-NEXT: s_load_dword s0, s[4:5], 0x2c34; FLAT-NEXT: v_mbcnt_lo_u32_b32 v0, -1, 035; FLAT-NEXT: s_waitcnt lgkmcnt(0)36; FLAT-NEXT: v_and_b32_e32 v0, s0, v037; FLAT-NEXT: v_and_b32_e32 v0, 1, v038; FLAT-NEXT: v_cmp_eq_u32_e32 vcc, 1, v039; FLAT-NEXT: s_mov_b64 s[0:1], 040; FLAT-NEXT: .LBB0_1: ; %ENDIF41; FLAT-NEXT: ; =>This Inner Loop Header: Depth=142; FLAT-NEXT: s_and_b64 s[2:3], exec, vcc43; FLAT-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1]44; FLAT-NEXT: s_andn2_b64 exec, exec, s[0:1]45; FLAT-NEXT: s_cbranch_execnz .LBB0_146; FLAT-NEXT: ; %bb.2: ; %ENDLOOP47; FLAT-NEXT: s_or_b64 exec, exec, s[0:1]48; FLAT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2449; FLAT-NEXT: s_mov_b32 s3, 0xf00050; FLAT-NEXT: s_mov_b32 s2, -151; FLAT-NEXT: v_mov_b32_e32 v0, 052; FLAT-NEXT: s_waitcnt lgkmcnt(0)53; FLAT-NEXT: buffer_store_dword v0, off, s[0:3], 054; FLAT-NEXT: s_endpgm55main_body:56 %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #057 %0 = and i32 %a, %tid58 %1 = trunc i32 %0 to i159 br label %ENDIF60 61ENDLOOP:62 store i32 0, ptr addrspace(1) %out63 ret void64 65ENDIF:66 br i1 %1, label %ENDLOOP, label %ENDIF67}68 69define amdgpu_kernel void @phi_cond_outside_loop(i32 %b) {70; SI-LABEL: phi_cond_outside_loop:71; SI: ; %bb.0: ; %entry72; SI-NEXT: v_mbcnt_lo_u32_b32_e64 v0, -1, 073; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v074; SI-NEXT: s_mov_b64 s[0:1], 075; SI-NEXT: s_mov_b64 s[2:3], 076; SI-NEXT: s_and_saveexec_b64 s[6:7], vcc77; SI-NEXT: s_cbranch_execz .LBB1_278; SI-NEXT: ; %bb.1: ; %else79; SI-NEXT: s_load_dword s2, s[4:5], 0x980; SI-NEXT: s_waitcnt lgkmcnt(0)81; SI-NEXT: s_cmp_eq_u32 s2, 082; SI-NEXT: s_cselect_b64 s[2:3], -1, 083; SI-NEXT: s_and_b64 s[2:3], s[2:3], exec84; SI-NEXT: .LBB1_2: ; %endif85; SI-NEXT: s_or_b64 exec, exec, s[6:7]86; SI-NEXT: .LBB1_3: ; %loop87; SI-NEXT: ; =>This Inner Loop Header: Depth=188; SI-NEXT: s_and_b64 s[4:5], exec, s[2:3]89; SI-NEXT: s_or_b64 s[0:1], s[4:5], s[0:1]90; SI-NEXT: s_andn2_b64 exec, exec, s[0:1]91; SI-NEXT: s_cbranch_execnz .LBB1_392; SI-NEXT: ; %bb.4: ; %exit93; SI-NEXT: s_endpgm94;95; FLAT-LABEL: phi_cond_outside_loop:96; FLAT: ; %bb.0: ; %entry97; FLAT-NEXT: v_mbcnt_lo_u32_b32 v0, -1, 098; FLAT-NEXT: v_cmp_ne_u32_e32 vcc, 0, v099; FLAT-NEXT: s_mov_b64 s[0:1], 0100; FLAT-NEXT: s_mov_b64 s[2:3], 0101; FLAT-NEXT: s_and_saveexec_b64 s[6:7], vcc102; FLAT-NEXT: s_cbranch_execz .LBB1_2103; FLAT-NEXT: ; %bb.1: ; %else104; FLAT-NEXT: s_load_dword s2, s[4:5], 0x24105; FLAT-NEXT: s_waitcnt lgkmcnt(0)106; FLAT-NEXT: s_cmp_eq_u32 s2, 0107; FLAT-NEXT: s_cselect_b64 s[2:3], -1, 0108; FLAT-NEXT: s_and_b64 s[2:3], s[2:3], exec109; FLAT-NEXT: .LBB1_2: ; %endif110; FLAT-NEXT: s_or_b64 exec, exec, s[6:7]111; FLAT-NEXT: .LBB1_3: ; %loop112; FLAT-NEXT: ; =>This Inner Loop Header: Depth=1113; FLAT-NEXT: s_and_b64 s[4:5], exec, s[2:3]114; FLAT-NEXT: s_or_b64 s[0:1], s[4:5], s[0:1]115; FLAT-NEXT: s_andn2_b64 exec, exec, s[0:1]116; FLAT-NEXT: s_cbranch_execnz .LBB1_3117; FLAT-NEXT: ; %bb.4: ; %exit118; FLAT-NEXT: s_endpgm119entry:120 %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0121 %0 = icmp eq i32 %tid , 0122 br i1 %0, label %if, label %else123 124if:125 br label %endif126 127else:128 %1 = icmp eq i32 %b, 0129 br label %endif130 131endif:132 %2 = phi i1 [0, %if], [%1, %else]133 br label %loop134 135loop:136 br i1 %2, label %exit, label %loop137 138exit:139 ret void140}141 142define amdgpu_kernel void @switch_unreachable(ptr addrspace(1) %g, ptr addrspace(3) %l, i32 %x) nounwind {143; SI-LABEL: switch_unreachable:144; SI: ; %bb.0: ; %centry145;146; FLAT-LABEL: switch_unreachable:147; FLAT: ; %bb.0: ; %centry148centry:149 switch i32 %x, label %sw.default [150 i32 0, label %sw.bb151 i32 60, label %sw.bb152 ]153 154sw.bb:155 unreachable156 157sw.default:158 unreachable159 160sw.epilog:161 ret void162}163 164declare float @llvm.fabs.f32(float) nounwind readnone165 166define amdgpu_kernel void @loop_land_info_assert(i32 %c0, i32 %c1, i32 %c2, i32 %c3, i32 %x, i32 %y, i1 %arg) nounwind {167; SI-LABEL: loop_land_info_assert:168; SI: ; %bb.0: ; %entry169; SI-NEXT: s_load_dword s0, s[4:5], 0xa170; SI-NEXT: s_waitcnt lgkmcnt(0)171; SI-NEXT: s_cmp_lt_i32 s0, 4172; SI-NEXT: s_cbranch_scc1 .LBB3_4173; SI-NEXT: ; %bb.1: ; %for.cond.preheader174; SI-NEXT: s_load_dword s0, s[4:5], 0xc175; SI-NEXT: s_waitcnt lgkmcnt(0)176; SI-NEXT: s_cmpk_lt_i32 s0, 0x3e8177; SI-NEXT: s_cbranch_scc0 .LBB3_4178; SI-NEXT: ; %bb.2: ; %for.body179; SI-NEXT: s_and_b64 vcc, exec, 0180; SI-NEXT: .LBB3_3: ; %self.loop181; SI-NEXT: ; =>This Inner Loop Header: Depth=1182; SI-NEXT: s_mov_b64 vcc, vcc183; SI-NEXT: s_cbranch_vccz .LBB3_3184; SI-NEXT: .LBB3_4: ; %DummyReturnBlock185; SI-NEXT: s_endpgm186;187; FLAT-LABEL: loop_land_info_assert:188; FLAT: ; %bb.0: ; %entry189; FLAT-NEXT: s_load_dword s0, s[4:5], 0x28190; FLAT-NEXT: s_waitcnt lgkmcnt(0)191; FLAT-NEXT: s_cmp_lt_i32 s0, 4192; FLAT-NEXT: s_cbranch_scc1 .LBB3_4193; FLAT-NEXT: ; %bb.1: ; %for.cond.preheader194; FLAT-NEXT: s_load_dword s0, s[4:5], 0x30195; FLAT-NEXT: s_waitcnt lgkmcnt(0)196; FLAT-NEXT: s_cmpk_lt_i32 s0, 0x3e8197; FLAT-NEXT: s_cbranch_scc0 .LBB3_4198; FLAT-NEXT: ; %bb.2: ; %for.body199; FLAT-NEXT: s_and_b64 vcc, exec, 0200; FLAT-NEXT: .LBB3_3: ; %self.loop201; FLAT-NEXT: ; =>This Inner Loop Header: Depth=1202; FLAT-NEXT: s_mov_b64 vcc, vcc203; FLAT-NEXT: s_cbranch_vccz .LBB3_3204; FLAT-NEXT: .LBB3_4: ; %DummyReturnBlock205; FLAT-NEXT: s_endpgm206entry:207 %cmp = icmp sgt i32 %c0, 0208 br label %while.cond.outer209 210while.cond.outer:211 %tmp = load float, ptr addrspace(1) poison212 br label %while.cond213 214while.cond:215 %cmp1 = icmp slt i32 %c1, 4216 br i1 %cmp1, label %convex.exit, label %for.cond217 218convex.exit:219 %or = or i1 %cmp, %cmp1220 br i1 %or, label %return, label %if.end221 222if.end:223 %tmp3 = call float @llvm.fabs.f32(float %tmp) nounwind readnone224 %cmp2 = fcmp olt float %tmp3, 0x3E80000000000000225 br i1 %cmp2, label %if.else, label %while.cond.outer226 227if.else:228 store volatile i32 3, ptr addrspace(1) poison, align 4229 br label %while.cond230 231for.cond:232 %cmp3 = icmp slt i32 %c3, 1000233 br i1 %cmp3, label %for.body, label %return234 235for.body:236 br i1 %cmp3, label %self.loop, label %if.end.2237 238if.end.2:239 %or.cond2 = or i1 %cmp3, %arg240 br i1 %or.cond2, label %return, label %for.cond241 242self.loop:243 br label %self.loop244 245return:246 ret void247}248 249declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #0250 251attributes #0 = { nounwind readnone }252