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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 62# RUN: llc -mtriple=amdgcn -mcpu=gfx90a -run-pass=si-fix-sgpr-copies -verify-machineinstrs -o - %s | FileCheck %s3 4---5name: constrain_readfirstlane_av6tracksRegLiveness: true7body: |8 ; CHECK-LABEL: name: constrain_readfirstlane_av9 ; CHECK: bb.0:10 ; CHECK-NEXT: successors: %bb.1(0x80000000)11 ; CHECK-NEXT: liveins: $vgpr012 ; CHECK-NEXT: {{ $}}13 ; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF14 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr015 ; CHECK-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY]], implicit $exec16 ; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[V_READFIRSTLANE_B32_]], [[DEF]], implicit-def dead $scc17 ; CHECK-NEXT: {{ $}}18 ; CHECK-NEXT: bb.1:19 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)20 ; CHECK-NEXT: {{ $}}21 ; CHECK-NEXT: [[S_MUL_I32_:%[0-9]+]]:sreg_32 = S_MUL_I32 [[S_AND_B32_]], [[S_AND_B32_]]22 ; CHECK-NEXT: [[S_MUL_HI_U32_:%[0-9]+]]:sreg_32 = S_MUL_HI_U32 [[S_AND_B32_]], [[S_MUL_I32_]]23 ; CHECK-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_MUL_HI_U32_]], [[S_MUL_I32_]], implicit-def dead $scc24 ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit undef $vcc25 ; CHECK-NEXT: S_BRANCH %bb.226 ; CHECK-NEXT: {{ $}}27 ; CHECK-NEXT: bb.2:28 ; CHECK-NEXT: S_ENDPGM 029 bb.0:30 liveins: $vgpr031 32 %0:sreg_32 = IMPLICIT_DEF33 %1:av_32 = COPY $vgpr034 %2:sreg_32 = COPY %135 %3:sreg_32 = S_AND_B32 %2, %0, implicit-def dead $scc36 37 bb.1:38 %4:sreg_32 = S_MUL_I32 %3, %339 %5:sreg_32 = S_MUL_HI_U32 %3, %440 %6:sreg_32 = S_ADD_I32 %5, %4, implicit-def dead $scc41 S_CBRANCH_VCCNZ %bb.1, implicit undef $vcc42 S_BRANCH %bb.243 44 bb.2:45 S_ENDPGM 046...47 48# Need to respect subregister on copy source49---50name: constrain_readfirstlane_av6451tracksRegLiveness: true52body: |53 ; CHECK-LABEL: name: constrain_readfirstlane_av6454 ; CHECK: bb.0:55 ; CHECK-NEXT: successors: %bb.1(0x80000000)56 ; CHECK-NEXT: liveins: $vgpr0_vgpr157 ; CHECK-NEXT: {{ $}}58 ; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF59 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr160 ; CHECK-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY]].sub0, implicit $exec61 ; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[V_READFIRSTLANE_B32_]], [[DEF]], implicit-def dead $scc62 ; CHECK-NEXT: {{ $}}63 ; CHECK-NEXT: bb.1:64 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)65 ; CHECK-NEXT: {{ $}}66 ; CHECK-NEXT: [[S_MUL_I32_:%[0-9]+]]:sreg_32 = S_MUL_I32 [[S_AND_B32_]], [[S_AND_B32_]]67 ; CHECK-NEXT: [[S_MUL_HI_U32_:%[0-9]+]]:sreg_32 = S_MUL_HI_U32 [[S_AND_B32_]], [[S_MUL_I32_]]68 ; CHECK-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_MUL_HI_U32_]], [[S_MUL_I32_]], implicit-def dead $scc69 ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit undef $vcc70 ; CHECK-NEXT: S_BRANCH %bb.271 ; CHECK-NEXT: {{ $}}72 ; CHECK-NEXT: bb.2:73 ; CHECK-NEXT: S_ENDPGM 074 bb.0:75 liveins: $vgpr0_vgpr176 77 %0:sreg_32 = IMPLICIT_DEF78 %1:av_64 = COPY $vgpr0_vgpr179 %2:sreg_32 = COPY %1.sub080 %3:sreg_32 = S_AND_B32 %2, %0, implicit-def dead $scc81 82 bb.1:83 %4:sreg_32 = S_MUL_I32 %3, %384 %5:sreg_32 = S_MUL_HI_U32 %3, %485 %6:sreg_32 = S_ADD_I32 %5, %4, implicit-def dead $scc86 S_CBRANCH_VCCNZ %bb.1, implicit undef $vcc87 S_BRANCH %bb.288 89 bb.2:90 S_ENDPGM 091...92 93---94name: constrain_readfirstlane_av64_subreg_m095tracksRegLiveness: true96body: |97 bb.0:98 liveins: $vgpr0_vgpr199 100 ; CHECK-LABEL: name: constrain_readfirstlane_av64_subreg_m0101 ; CHECK: liveins: $vgpr0_vgpr1102 ; CHECK-NEXT: {{ $}}103 ; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF104 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1105 ; CHECK-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY]].sub0, implicit $exec106 ; CHECK-NEXT: $m0 = COPY [[V_READFIRSTLANE_B32_]]107 %0:sreg_32 = IMPLICIT_DEF108 %1:av_64 = COPY $vgpr0_vgpr1109 $m0 = COPY %1.sub0110...111 112