178 lines · plain
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 52# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -run-pass=si-fold-operands -o - %s | FileCheck %s3 4# Make sure materializes of 64-bit immediates fold the correct value5# into subregister uses.6 7---8name: s_mov_b64_sub1_folds_wrong_value_09tracksRegLiveness: true10body: |11 bb.0:12 liveins: $sgpr8_sgpr913 14 ; CHECK-LABEL: name: s_mov_b64_sub1_folds_wrong_value_015 ; CHECK: liveins: $sgpr8_sgpr916 ; CHECK-NEXT: {{ $}}17 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr918 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]].sub0, %subreg.sub0, [[COPY]].sub1, %subreg.sub119 ; CHECK-NEXT: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[REG_SEQUENCE]].sub0, 8, implicit-def $scc20 ; CHECK-NEXT: [[S_ADDC_U32_:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[REG_SEQUENCE]].sub1, 0, implicit-def $scc, implicit $scc21 ; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_ADD_U32_]], %subreg.sub0, [[S_ADDC_U32_]], %subreg.sub122 ; CHECK-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE1]]23 %0:sgpr_64 = COPY $sgpr8_sgpr924 %1:sreg_64 = REG_SEQUENCE %0.sub0, %subreg.sub0, %0.sub1, %subreg.sub125 %2:sreg_64 = S_MOV_B64 826 %3:sreg_32 = S_ADD_U32 %1.sub0, %2.sub0, implicit-def $scc27 %4:sreg_32 = S_ADDC_U32 %1.sub1, %2.sub1, implicit-def $scc, implicit $scc28 %5:sreg_64 = REG_SEQUENCE %3, %subreg.sub0, %4, %subreg.sub129 S_ENDPGM 0, implicit %530 31...32 33---34name: v_mov_b64_pseudo_sub1_folds_wrong_value35tracksRegLiveness: true36body: |37 bb.0:38 liveins: $vgpr8_vgpr939 40 ; CHECK-LABEL: name: v_mov_b64_pseudo_sub1_folds_wrong_value41 ; CHECK: liveins: $vgpr8_vgpr942 ; CHECK-NEXT: {{ $}}43 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr8_vgpr944 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]].sub0, %subreg.sub0, [[COPY]].sub1, %subreg.sub145 ; CHECK-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[REG_SEQUENCE]].sub0, 3, 0, implicit $exec46 ; CHECK-NEXT: [[V_ADDC_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADDC_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADDC_U32_e64 [[REG_SEQUENCE]].sub1, 7, [[V_ADD_CO_U32_e64_1]], 0, implicit $exec47 ; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_CO_U32_e64_]], %subreg.sub0, [[V_ADDC_U32_e64_]], %subreg.sub148 ; CHECK-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE1]]49 %0:vreg_64 = COPY $vgpr8_vgpr950 %1:vreg_64 = REG_SEQUENCE %0.sub0, %subreg.sub0, %0.sub1, %subreg.sub151 %2:vreg_64 = V_MOV_B64_PSEUDO 30064771075, implicit $exec52 %3:vgpr_32, %6:sreg_64_xexec = V_ADD_CO_U32_e64 %1.sub0, %2.sub0, 0, implicit $exec53 %4:vgpr_32, %7:sreg_64_xexec = V_ADDC_U32_e64 %1.sub1, %2.sub1, %6, 0, implicit $exec54 %5:vreg_64 = REG_SEQUENCE %3, %subreg.sub0, %4, %subreg.sub155 S_ENDPGM 0, implicit %556 57...58 59---60name: subreg_fold_imm61tracksRegLiveness: true62body: |63 bb.0:64 liveins: $sgpr8_sgpr9, $vgpr8_vgpr965 66 ; CHECK-LABEL: name: subreg_fold_imm67 ; CHECK: liveins: $sgpr8_sgpr9, $vgpr8_vgpr968 ; CHECK-NEXT: {{ $}}69 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr970 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]].sub0, %subreg.sub0, [[COPY]].sub1, %subreg.sub171 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_64 = COPY [[COPY]]72 ; CHECK-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[REG_SEQUENCE]].sub1, [[COPY1]].sub1, 0, implicit $exec73 ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e64_]]74 %0:sgpr_64 = COPY $sgpr8_sgpr975 %1:sreg_64 = REG_SEQUENCE %0.sub0, %subreg.sub0, %0.sub1, %subreg.sub176 %2:vreg_64 = COPY %077 %3:vgpr_32, dead %6:sreg_64_xexec = V_ADD_CO_U32_e64 %1.sub1, %2.sub1, 0, implicit $exec78 S_ENDPGM 0, implicit %379 80...81 82---83name: s_mov_b64_into_reg_sequence_user84tracksRegLiveness: true85body: |86 bb.0:87 liveins: $sgpr8_sgpr988 89 ; CHECK-LABEL: name: s_mov_b64_into_reg_sequence_user90 ; CHECK: liveins: $sgpr8_sgpr991 ; CHECK-NEXT: {{ $}}92 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr993 ; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 894 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B64_]].sub1, %subreg.sub0, [[S_MOV_B64_]].sub0, %subreg.sub195 ; CHECK-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY]], [[REG_SEQUENCE]], implicit-def $scc96 ; CHECK-NEXT: S_ENDPGM 0, implicit [[S_AND_B64_]]97 %0:sgpr_64 = COPY $sgpr8_sgpr998 %1:sreg_64 = S_MOV_B64 899 %2:sreg_64 = REG_SEQUENCE %1.sub1, %subreg.sub0, %1.sub0, %subreg.sub1100 %3:sreg_64 = S_AND_B64 %0, %2, implicit-def $scc101 S_ENDPGM 0, implicit %3102 103...104 105---106name: s_mov_b64_into_reg_sequence_user_with_subregs107tracksRegLiveness: true108body: |109 bb.0:110 liveins: $sgpr8_sgpr9111 112 ; CHECK-LABEL: name: s_mov_b64_into_reg_sequence_user_with_subregs113 ; CHECK: liveins: $sgpr8_sgpr9114 ; CHECK-NEXT: {{ $}}115 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9116 ; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 8117 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B64_]].sub1, %subreg.sub0, [[S_MOV_B64_]].sub0, %subreg.sub1118 ; CHECK-NEXT: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]].sub0, 0, implicit-def $scc119 ; CHECK-NEXT: [[S_ADDC_U32_:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[COPY]].sub1, 8, implicit-def $scc, implicit $scc120 ; CHECK-NEXT: S_ENDPGM 0, implicit [[S_ADD_U32_]], implicit [[S_ADDC_U32_]]121 %0:sgpr_64 = COPY $sgpr8_sgpr9122 %1:sreg_64 = S_MOV_B64 8123 %2:sreg_64 = REG_SEQUENCE %1.sub1, %subreg.sub0, %1.sub0, %subreg.sub1124 %3:sreg_32 = S_ADD_U32 %0.sub0, %2.sub0, implicit-def $scc125 %4:sreg_32 = S_ADDC_U32 %0.sub1, %2.sub1, implicit-def $scc, implicit $scc126 S_ENDPGM 0, implicit %3, implicit %4127 128...129 130---131name: issue139908_wrong_splat_constant_handling132tracksRegLiveness: true133body: |134 bb.0:135 liveins: $sgpr8_sgpr9136 137 ; CHECK-LABEL: name: issue139908_wrong_splat_constant_handling138 ; CHECK: liveins: $sgpr8_sgpr9139 ; CHECK-NEXT: {{ $}}140 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9141 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 42142 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_]], %subreg.sub1143 ; CHECK-NEXT: S_CMP_EQ_U64 [[COPY]], [[REG_SEQUENCE]], implicit-def $scc144 ; CHECK-NEXT: S_ENDPGM 0, implicit $scc145 %0:sgpr_64 = COPY $sgpr8_sgpr9146 %1:sreg_32 = S_MOV_B32 42147 %2:sreg_64 = REG_SEQUENCE %1, %subreg.sub0, %1, %subreg.sub1148 S_CMP_EQ_U64 %0, %2, implicit-def $scc149 S_ENDPGM 0, implicit $scc150 151...152 153---154name: s_mov_b64_copy_subreg_into_reg_sequence_user155tracksRegLiveness: true156body: |157 bb.0:158 liveins: $sgpr8, $sgpr9159 160 ; CHECK-LABEL: name: s_mov_b64_copy_subreg_into_reg_sequence_user161 ; CHECK: liveins: $sgpr8, $sgpr9162 ; CHECK-NEXT: {{ $}}163 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr8164 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr9165 ; CHECK-NEXT: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]], 16, implicit-def $scc166 ; CHECK-NEXT: [[S_ADDC_U32_:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[COPY1]], 0, implicit-def $scc, implicit $scc167 ; CHECK-NEXT: S_ENDPGM 0, implicit [[S_ADD_U32_]], implicit [[S_ADDC_U32_]]168 %0:sreg_32 = COPY $sgpr8169 %1:sreg_32 = COPY $sgpr9170 %2:sreg_64 = S_MOV_B64 16171 %3:sreg_32 = COPY %2.sub0172 %4:sreg_32 = COPY %2.sub1173 %5:sreg_32 = S_ADD_U32 %0, %3, implicit-def $scc174 %6:sreg_32 = S_ADDC_U32 %1, %4, implicit-def $scc, implicit $scc175 S_ENDPGM 0, implicit %5, implicit %6176 177...178