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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 52# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -verify-machineinstrs -run-pass si-wqm -o - %s | FileCheck %s3# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -passes=si-wqm -o - %s | FileCheck %s4 5---6# Test that we don't do silly things when there is no whole wave mode in the7# shader (aka bb.1).8#9name: test_no_wwm10alignment: 111exposesReturnsTwice: false12tracksRegLiveness: true13body: |14 ; CHECK-LABEL: name: test_no_wwm15 ; CHECK: bb.0:16 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)17 ; CHECK-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr818 ; CHECK-NEXT: {{ $}}19 ; CHECK-NEXT: [[S_OR_SAVEEXEC_B32_:%[0-9]+]]:sreg_32 = S_OR_SAVEEXEC_B32 -1, implicit-def $exec, implicit-def $scc, implicit $exec20 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr021 ; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0:ccr_sgpr_64 = COPY $sgpr122 ; CHECK-NEXT: [[COPY1:%[0-9]+]].sub1:ccr_sgpr_64 = COPY $sgpr223 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr824 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sreg_32_xm0_xexec = COPY $exec_lo, implicit-def $exec_lo25 ; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY3]], [[S_OR_SAVEEXEC_B32_]], implicit-def dead $scc26 ; CHECK-NEXT: $exec_lo = S_MOV_B32_term [[S_AND_B32_]]27 ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.2, implicit $exec28 ; CHECK-NEXT: S_BRANCH %bb.129 ; CHECK-NEXT: {{ $}}30 ; CHECK-NEXT: bb.1:31 ; CHECK-NEXT: successors: %bb.2(0x80000000)32 ; CHECK-NEXT: {{ $}}33 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 5, [[COPY2]], 0, implicit $exec34 ; CHECK-NEXT: {{ $}}35 ; CHECK-NEXT: bb.2:36 ; CHECK-NEXT: $exec_lo = S_OR_B32 $exec_lo, [[COPY3]], implicit-def $scc37 ; CHECK-NEXT: $vgpr8 = COPY [[COPY2]]38 ; CHECK-NEXT: $sgpr0 = COPY [[COPY]]39 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr040 ; CHECK-NEXT: SI_CS_CHAIN_TC_W32 [[COPY1]], 0, 0, [[COPY4]], amdgpu_allvgprs, implicit $sgpr0, implicit $vgpr841 bb.0:42 successors: %bb.1, %bb.243 liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr844 %9:sreg_32 = COPY $sgpr045 undef %1.sub0:ccr_sgpr_64 = COPY $sgpr146 %1.sub1:ccr_sgpr_64 = COPY $sgpr247 %37:vgpr_32 = COPY $vgpr848 %14:sreg_32_xm0_xexec = SI_INIT_WHOLE_WAVE implicit-def $exec, implicit $exec49 %16:sreg_32_xm0_xexec = COPY $exec_lo, implicit-def $exec_lo50 %38:sreg_32 = S_AND_B32 %16:sreg_32_xm0_xexec, %14:sreg_32_xm0_xexec, implicit-def dead $scc51 $exec_lo = S_MOV_B32_term %38:sreg_3252 S_CBRANCH_EXECZ %bb.2, implicit $exec53 S_BRANCH %bb.154 55 bb.1:56 %37:vgpr_32 = V_ADD_U32_e64 5, %37:vgpr_32, 0, implicit $exec57 58 bb.2:59 $exec_lo = S_OR_B32 $exec_lo, %16:sreg_32_xm0_xexec, implicit-def $scc60 $vgpr8 = COPY %37:vgpr_3261 $sgpr0 = COPY %9:sreg_3262 %2:sreg_32 = COPY $sgpr063 SI_CS_CHAIN_TC_W32 %1:ccr_sgpr_64, 0, 0, %2:sreg_32, amdgpu_allvgprs, implicit $sgpr0, implicit $vgpr864...65 66---67# Test that we handle WWM in the shader correctly.68#69name: test_wwm_bb170alignment: 171exposesReturnsTwice: false72tracksRegLiveness: true73body: |74 ; CHECK-LABEL: name: test_wwm_bb175 ; CHECK: bb.0:76 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)77 ; CHECK-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr8, $vgpr978 ; CHECK-NEXT: {{ $}}79 ; CHECK-NEXT: [[S_OR_SAVEEXEC_B32_:%[0-9]+]]:sreg_32 = S_OR_SAVEEXEC_B32 -1, implicit-def $exec, implicit-def $scc, implicit $exec80 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr081 ; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0:ccr_sgpr_64 = COPY $sgpr182 ; CHECK-NEXT: [[COPY1:%[0-9]+]].sub1:ccr_sgpr_64 = COPY $sgpr283 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr984 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr885 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sreg_32_xm0_xexec = COPY $exec_lo, implicit-def $exec_lo86 ; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY4]], [[S_OR_SAVEEXEC_B32_]], implicit-def dead $scc87 ; CHECK-NEXT: $exec_lo = S_MOV_B32_term [[S_AND_B32_]]88 ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.2, implicit $exec89 ; CHECK-NEXT: S_BRANCH %bb.190 ; CHECK-NEXT: {{ $}}91 ; CHECK-NEXT: bb.1:92 ; CHECK-NEXT: successors: %bb.2(0x80000000)93 ; CHECK-NEXT: {{ $}}94 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 24, [[COPY3]], 0, implicit $exec95 ; CHECK-NEXT: [[ENTER_STRICT_WWM:%[0-9]+]]:sreg_32_xm0_xexec = ENTER_STRICT_WWM -1, implicit-def $exec, implicit-def $scc, implicit $exec96 ; CHECK-NEXT: dead [[DEF:%[0-9]+]]:sreg_32_xm0_xexec = IMPLICIT_DEF97 ; CHECK-NEXT: [[V_SET_INACTIVE_B32_:%[0-9]+]]:vgpr_32 = V_SET_INACTIVE_B32 0, [[COPY3]], 0, 71, undef [[ENTER_STRICT_WWM]], implicit $exec, implicit-def $scc98 ; CHECK-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 42, [[V_SET_INACTIVE_B32_]], 0, implicit $exec99 ; CHECK-NEXT: $exec_lo = EXIT_STRICT_WWM [[ENTER_STRICT_WWM]]100 ; CHECK-NEXT: early-clobber [[COPY2]]:vgpr_32 = V_MOV_B32_e32 [[V_ADD_U32_e64_]], implicit $exec101 ; CHECK-NEXT: {{ $}}102 ; CHECK-NEXT: bb.2:103 ; CHECK-NEXT: $exec_lo = S_OR_B32 $exec_lo, [[COPY4]], implicit-def $scc104 ; CHECK-NEXT: $vgpr8 = COPY [[COPY2]]105 ; CHECK-NEXT: $vgpr9 = COPY [[COPY3]]106 ; CHECK-NEXT: $sgpr0 = COPY [[COPY]]107 ; CHECK-NEXT: SI_CS_CHAIN_TC_W32 [[COPY1]], 0, 0, [[COPY]], amdgpu_allvgprs, implicit $sgpr0, implicit $vgpr8, implicit $vgpr9108 bb.0:109 successors: %bb.1, %bb.2110 liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr8, $vgpr9111 %9:sreg_32 = COPY $sgpr0112 undef %1.sub0:ccr_sgpr_64 = COPY $sgpr1113 %1.sub1:ccr_sgpr_64 = COPY $sgpr2114 %40:vgpr_32 = COPY $vgpr9115 %36:vgpr_32 = COPY $vgpr8116 %14:sreg_32_xm0_xexec = SI_INIT_WHOLE_WAVE implicit-def $exec, implicit $exec117 %16:sreg_32_xm0_xexec = COPY $exec_lo, implicit-def $exec_lo118 %38:sreg_32 = S_AND_B32 %16:sreg_32_xm0_xexec, %14:sreg_32_xm0_xexec, implicit-def dead $scc119 $exec_lo = S_MOV_B32_term %38:sreg_32120 S_CBRANCH_EXECZ %bb.2, implicit $exec121 S_BRANCH %bb.1122 123 bb.1:124 %36:vgpr_32 = V_ADD_U32_e64 24, %36:vgpr_32, 0, implicit $exec125 %20:sreg_32_xm0_xexec = IMPLICIT_DEF126 %19:vgpr_32 = V_SET_INACTIVE_B32 0, %36:vgpr_32, 0, 71, undef %20, implicit $exec, implicit-def $scc127 %18:vgpr_32 = V_ADD_U32_e64 42, %19:vgpr_32, 0, implicit $exec128 %40:vgpr_32 = STRICT_WWM %18:vgpr_32, implicit $exec129 130 bb.2:131 $exec_lo = S_OR_B32 $exec_lo, %16:sreg_32_xm0_xexec, implicit-def $scc132 $vgpr8 = COPY %40:vgpr_32133 $vgpr9 = COPY %36:vgpr_32134 $sgpr0 = COPY %9:sreg_32135 SI_CS_CHAIN_TC_W32 %1:ccr_sgpr_64, 0, 0, %9:sreg_32, amdgpu_allvgprs, implicit $sgpr0, implicit $vgpr8, implicit $vgpr9136...137