152 lines · plain
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 32# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs -run-pass=si-i1-copies -o - %s | FileCheck -check-prefixes=GCN %s3 4# Order in which SILowerI1Copies build instructions to merge lane masks should5# not depend on order of incoming operands in phi instruction.6# SDAG adds phi incomings as it processes basic blocks in reversed post order7# traversal. Because of that, incomings in phis created by SDAG are sorted,8# compared to the how phi looked in IR, in convenient way for lowerPhis.9 10# Here incomings for %20:vreg_1 = PHI %19, %bb.1, %26, %bb.2 are swapped11# to verify that SILowerI1Copies sorts incomings from phi appropriately before12# it starts merging lane masks.13 14---15name: phi16tracksRegLiveness: true17body: |18 ; GCN-LABEL: name: phi19 ; GCN: bb.0:20 ; GCN-NEXT: successors: %bb.1(0x80000000)21 ; GCN-NEXT: liveins: $vgpr1, $vgpr2, $vgpr3, $vgpr422 ; GCN-NEXT: {{ $}}23 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr424 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr325 ; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr226 ; GCN-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr127 ; GCN-NEXT: [[DEF:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF28 ; GCN-NEXT: [[DEF1:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF29 ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY]], %subreg.sub130 ; GCN-NEXT: [[DEF2:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF31 ; GCN-NEXT: [[DEF3:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF32 ; GCN-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY3]], %subreg.sub0, [[COPY2]], %subreg.sub133 ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -134 ; GCN-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 -135 ; GCN-NEXT: [[COPY4:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]]36 ; GCN-NEXT: [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE1]]37 ; GCN-NEXT: [[DEF4:%[0-9]+]]:sreg_32 = IMPLICIT_DEF38 ; GCN-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $exec_lo39 ; GCN-NEXT: [[DEF5:%[0-9]+]]:sreg_32 = IMPLICIT_DEF40 ; GCN-NEXT: {{ $}}41 ; GCN-NEXT: bb.1:42 ; GCN-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)43 ; GCN-NEXT: {{ $}}44 ; GCN-NEXT: [[PHI:%[0-9]+]]:sreg_32 = PHI [[DEF5]], %bb.0, %20, %bb.345 ; GCN-NEXT: [[PHI1:%[0-9]+]]:sreg_32 = PHI [[COPY6]], %bb.0, %37, %bb.346 ; GCN-NEXT: [[PHI2:%[0-9]+]]:sreg_32 = PHI [[S_MOV_B32_1]], %bb.0, %16, %bb.347 ; GCN-NEXT: [[PHI3:%[0-9]+]]:vreg_64 = PHI [[COPY5]], %bb.0, %18, %bb.348 ; GCN-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY [[PHI1]]49 ; GCN-NEXT: [[S_ANDN2_B32_:%[0-9]+]]:sreg_32 = S_ANDN2_B32 [[PHI]], $exec_lo, implicit-def $scc50 ; GCN-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[PHI1]], $exec_lo, implicit-def $scc51 ; GCN-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[S_ANDN2_B32_]], [[S_AND_B32_]], implicit-def $scc52 ; GCN-NEXT: [[SI_IF:%[0-9]+]]:sreg_32 = SI_IF [[COPY7]], %bb.3, implicit-def dead $exec, implicit-def dead $scc, implicit $exec53 ; GCN-NEXT: S_BRANCH %bb.254 ; GCN-NEXT: {{ $}}55 ; GCN-NEXT: bb.2:56 ; GCN-NEXT: successors: %bb.3(0x80000000)57 ; GCN-NEXT: {{ $}}58 ; GCN-NEXT: [[GLOBAL_LOAD_DWORD:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[PHI3]], 0, 0, implicit $exec :: (load (s32), addrspace 1)59 ; GCN-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 060 ; GCN-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_EQ_U32_e64 killed [[GLOBAL_LOAD_DWORD]], killed [[S_MOV_B32_2]], implicit $exec61 ; GCN-NEXT: [[S_ANDN2_B32_1:%[0-9]+]]:sreg_32 = S_ANDN2_B32 [[S_OR_B32_]], $exec_lo, implicit-def $scc62 ; GCN-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32 = S_AND_B32 [[V_CMP_EQ_U32_e64_]], $exec_lo, implicit-def $scc63 ; GCN-NEXT: [[S_OR_B32_1:%[0-9]+]]:sreg_32 = S_OR_B32 [[S_ANDN2_B32_1]], [[S_AND_B32_1]], implicit-def $scc64 ; GCN-NEXT: {{ $}}65 ; GCN-NEXT: bb.3:66 ; GCN-NEXT: successors: %bb.4(0x04000000), %bb.1(0x7c000000)67 ; GCN-NEXT: {{ $}}68 ; GCN-NEXT: [[PHI4:%[0-9]+]]:sreg_32 = PHI [[S_OR_B32_]], %bb.1, [[S_OR_B32_1]], %bb.269 ; GCN-NEXT: SI_END_CF [[SI_IF]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec70 ; GCN-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 471 ; GCN-NEXT: [[V_ADD_U:%[0-9]+]]:vreg_64 = V_ADD_U64_PSEUDO [[PHI3]], killed [[S_MOV_B64_]], implicit-def dead $vcc_lo, implicit $exec72 ; GCN-NEXT: [[S_MOV_B32_3:%[0-9]+]]:sreg_32 = S_MOV_B32 173 ; GCN-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = nsw S_ADD_I32 [[PHI2]], killed [[S_MOV_B32_3]], implicit-def dead $scc74 ; GCN-NEXT: [[S_MOV_B32_4:%[0-9]+]]:sreg_32 = S_MOV_B32 975 ; GCN-NEXT: [[S_ANDN2_B32_2:%[0-9]+]]:sreg_32 = S_ANDN2_B32 [[PHI1]], $exec_lo, implicit-def $scc76 ; GCN-NEXT: [[S_AND_B32_2:%[0-9]+]]:sreg_32 = S_AND_B32 [[PHI4]], $exec_lo, implicit-def $scc77 ; GCN-NEXT: [[S_OR_B32_2:%[0-9]+]]:sreg_32 = S_OR_B32 [[S_ANDN2_B32_2]], [[S_AND_B32_2]], implicit-def $scc78 ; GCN-NEXT: S_CMP_GT_I32 [[S_ADD_I32_]], killed [[S_MOV_B32_4]], implicit-def $scc79 ; GCN-NEXT: S_CBRANCH_SCC1 %bb.1, implicit $scc80 ; GCN-NEXT: S_BRANCH %bb.481 ; GCN-NEXT: {{ $}}82 ; GCN-NEXT: bb.4:83 ; GCN-NEXT: [[S_MOV_B32_5:%[0-9]+]]:sgpr_32 = S_MOV_B32 106535321684 ; GCN-NEXT: [[S_MOV_B32_6:%[0-9]+]]:sgpr_32 = S_MOV_B32 085 ; GCN-NEXT: [[COPY8:%[0-9]+]]:sreg_32_xm0_xexec = COPY [[PHI1]]86 ; GCN-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY killed [[S_MOV_B32_5]]87 ; GCN-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, killed [[S_MOV_B32_6]], 0, [[COPY9]], [[COPY8]], implicit $exec88 ; GCN-NEXT: FLAT_STORE_DWORD [[COPY4]], killed [[V_CNDMASK_B32_e64_]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s32))89 ; GCN-NEXT: SI_RETURN90 bb.0:91 successors: %bb.1(0x80000000)92 liveins: $vgpr1, $vgpr2, $vgpr3, $vgpr493 94 %0:vgpr_32 = COPY $vgpr495 %1:vgpr_32 = COPY $vgpr396 %2:vgpr_32 = COPY $vgpr297 %3:vgpr_32 = COPY $vgpr198 %4:sgpr_32 = IMPLICIT_DEF99 %5:sgpr_32 = IMPLICIT_DEF100 %6:vreg_64 = REG_SEQUENCE %1, %subreg.sub0, %0, %subreg.sub1101 %7:sgpr_32 = IMPLICIT_DEF102 %8:sgpr_32 = IMPLICIT_DEF103 %9:vreg_64 = REG_SEQUENCE %3, %subreg.sub0, %2, %subreg.sub1104 %10:sreg_32 = S_MOV_B32 -1105 %11:sreg_32 = S_MOV_B32 -1106 %12:vreg_64 = COPY %6107 %13:vreg_64 = COPY %9108 %14:vreg_1 = COPY %10, implicit $exec109 110 bb.1:111 successors: %bb.2(0x40000000), %bb.3(0x40000000)112 113 %15:sreg_32 = PHI %11, %bb.0, %16, %bb.3114 %17:vreg_64 = PHI %13, %bb.0, %18, %bb.3115 %19:vreg_1 = PHI %14, %bb.0, %20, %bb.3116 %21:sreg_32 = COPY %19117 %22:sreg_32 = SI_IF %21, %bb.3, implicit-def dead $exec, implicit-def dead $scc, implicit $exec118 S_BRANCH %bb.2119 120 bb.2:121 successors: %bb.3(0x80000000)122 123 %23:vgpr_32 = GLOBAL_LOAD_DWORD %17, 0, 0, implicit $exec :: (load (s32), addrspace 1)124 %24:sreg_32 = S_MOV_B32 0125 %25:sreg_32 = V_CMP_EQ_U32_e64 killed %23, killed %24, implicit $exec126 %26:vreg_1 = COPY %25127 128 bb.3:129 successors: %bb.4(0x04000000), %bb.1(0x7c000000)130 131 %20:vreg_1 = PHI %26, %bb.2, %19, %bb.1 ;%20:vreg_1 = PHI %19, %bb.1, %26, %bb.2 - this is original phi created by SDAG132 SI_END_CF %22, implicit-def dead $exec, implicit-def dead $scc, implicit $exec133 %27:sreg_64 = S_MOV_B64 4134 %18:vreg_64 = V_ADD_U64_PSEUDO %17, killed %27, implicit-def dead $vcc, implicit $exec135 %28:sreg_32 = S_MOV_B32 1136 %16:sreg_32 = nsw S_ADD_I32 %15, killed %28, implicit-def dead $scc137 %29:sreg_32 = S_MOV_B32 9138 S_CMP_GT_I32 %16, killed %29, implicit-def $scc139 S_CBRANCH_SCC1 %bb.1, implicit $scc140 S_BRANCH %bb.4141 142 bb.4:143 %30:vreg_1 = PHI %19, %bb.3144 %31:sgpr_32 = S_MOV_B32 1065353216145 %32:sgpr_32 = S_MOV_B32 0146 %33:sreg_32_xm0_xexec = COPY %30147 %34:vgpr_32 = COPY killed %31148 %35:vgpr_32 = V_CNDMASK_B32_e64 0, killed %32, 0, %34, %33, implicit $exec149 FLAT_STORE_DWORD %12, killed %35, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32))150 SI_RETURN151...152