99 lines · plain
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 22# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs -run-pass=si-opt-vgpr-liverange -o - %s | FileCheck -check-prefixes=CHECK %s3# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -passes=si-opt-vgpr-liverange -o - %s | FileCheck -check-prefixes=CHECK %s4 5# Tests a case that used to assert in SIOptimizeVGPRLiveRange when trying to optimize %3 which still appears6# (though in an undef operand) in the REG_SEQUENCE of the "endif block". This undef pattern was caused by7# DetectDeadLanes.8 9--- |10 define dllexport amdgpu_ps void @_amdgpu_ps_main() #0 {11 unreachable12 }13 14 attributes #0 = { "target-cpu"="gfx1100" "target-features"=",+wavefrontsize64,+cumode" "uniform-work-group-size"="false" }15...16---17name: _amdgpu_ps_main18tracksRegLiveness: true19registers:20 - { id: 1, class: vgpr_32, preferred-register: '' }21 - { id: 2, class: vgpr_32, preferred-register: '' }22 - { id: 3, class: vgpr_32, preferred-register: '' }23 - { id: 4, class: sreg_64, preferred-register: '$vcc' }24 - { id: 5, class: vreg_128, preferred-register: '' }25 - { id: 6, class: sgpr_128, preferred-register: '' }26 - { id: 7, class: vgpr_32, preferred-register: '' }27liveins:28 - { reg: '$vgpr0', virtual-reg: '%1' }29body: |30 ; CHECK-LABEL: name: _amdgpu_ps_main31 ; CHECK: bb.0:32 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)33 ; CHECK-NEXT: liveins: $vgpr034 ; CHECK-NEXT: {{ $}}35 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY killed $vgpr036 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec37 ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN killed [[COPY]], undef %5:sgpr_128, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s32))38 ; CHECK-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[BUFFER_LOAD_DWORD_OFFEN]], implicit $exec39 ; CHECK-NEXT: [[SI_IF:%[0-9]+]]:sreg_64 = SI_IF killed [[V_CMP_NE_U32_e64_]], %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec40 ; CHECK-NEXT: S_BRANCH %bb.141 ; CHECK-NEXT: {{ $}}42 ; CHECK-NEXT: bb.1:43 ; CHECK-NEXT: successors: %bb.2(0x80000000)44 ; CHECK-NEXT: {{ $}}45 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE killed [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_]], %subreg.sub1, [[V_MOV_B32_e32_]], %subreg.sub2, undef %4.sub3, %subreg.sub346 ; CHECK-NEXT: {{ $}}47 ; CHECK-NEXT: bb.2:48 ; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.4(0x40000000)49 ; CHECK-NEXT: {{ $}}50 ; CHECK-NEXT: [[PHI:%[0-9]+]]:vreg_128 = PHI undef %10:vreg_128, %bb.0, [[REG_SEQUENCE]], %bb.151 ; CHECK-NEXT: [[PHI1:%[0-9]+]]:vgpr_32 = PHI [[BUFFER_LOAD_DWORD_OFFEN]], %bb.0, undef %15:vgpr_32, %bb.152 ; CHECK-NEXT: [[SI_ELSE:%[0-9]+]]:sreg_64 = SI_ELSE killed [[SI_IF]], %bb.4, implicit-def dead $exec, implicit-def dead $scc, implicit $exec53 ; CHECK-NEXT: S_BRANCH %bb.354 ; CHECK-NEXT: {{ $}}55 ; CHECK-NEXT: bb.3:56 ; CHECK-NEXT: successors: %bb.4(0x80000000)57 ; CHECK-NEXT: {{ $}}58 ; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_128 = REG_SEQUENCE killed [[PHI1]], %subreg.sub0, [[PHI1]], %subreg.sub1, [[PHI1]], %subreg.sub2, undef %6:vgpr_32, %subreg.sub359 ; CHECK-NEXT: {{ $}}60 ; CHECK-NEXT: bb.4:61 ; CHECK-NEXT: [[PHI2:%[0-9]+]]:vreg_128 = PHI [[PHI]], %bb.2, [[REG_SEQUENCE1]], %bb.362 ; CHECK-NEXT: SI_END_CF killed [[SI_ELSE]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec63 ; CHECK-NEXT: dead [[REG_SEQUENCE2:%[0-9]+]]:vreg_128 = REG_SEQUENCE killed [[PHI2]].sub2, %subreg.sub0, [[PHI2]].sub2, %subreg.sub1, [[PHI2]].sub2, %subreg.sub2, undef [[BUFFER_LOAD_DWORD_OFFEN]], %subreg.sub364 ; CHECK-NEXT: S_ENDPGM 065 bb.0:66 successors: %bb.5(0x40000000), %bb.6(0x40000000)67 liveins: $vgpr068 69 %1:vgpr_32 = COPY killed $vgpr070 %2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec71 %3:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN %1, undef %6:sgpr_128, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s32))72 %4:sreg_64 = V_CMP_NE_U32_e64 0, %3, implicit $exec73 %8:sreg_64 = SI_IF killed %4, %bb.6, implicit-def dead $exec, implicit-def dead $scc, implicit $exec74 S_BRANCH %bb.575 76 bb.5:77 successors: %bb.6(0x80000000)78 79 %9:vreg_128 = REG_SEQUENCE %2, %subreg.sub0, %2, %subreg.sub1, %2, %subreg.sub2, undef %5.sub3:vreg_128, %subreg.sub380 81 bb.6:82 successors: %bb.7(0x40000000), %bb.8(0x40000000)83 84 %10:vreg_128 = PHI undef %156:vreg_128, %bb.0, %9, %bb.585 %11:sreg_64 = SI_ELSE killed %8, %bb.8, implicit-def dead $exec, implicit-def dead $scc, implicit $exec86 S_BRANCH %bb.787 88 bb.7:89 successors: %bb.8(0x80000000)90 91 %12:vreg_128 = REG_SEQUENCE %3, %subreg.sub0, %3, %subreg.sub1, killed %3, %subreg.sub2, undef %7, %subreg.sub392 93 bb.8:94 %13:vreg_128 = PHI %10, %bb.6, %12, %bb.795 SI_END_CF killed %11, implicit-def dead $exec, implicit-def dead $scc, implicit $exec96 %5:vreg_128 = REG_SEQUENCE %13.sub2, %subreg.sub0, %13.sub2, %subreg.sub1, killed %13.sub2, %subreg.sub2, undef %3, %subreg.sub397 S_ENDPGM 098...99