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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 52# RUN: llc -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs -run-pass=si-pre-allocate-wwm-regs -o - %s | FileCheck %s3# RUN: llc -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs -amdgpu-prealloc-sgpr-spill-vgprs -run-pass=si-pre-allocate-wwm-regs -o - %s | FileCheck %s --check-prefix=CHECK24 5# RUN: llc -mtriple=amdgcn -passes=si-pre-allocate-wwm-regs -o - -mcpu=tahiti %s | FileCheck %s6# RUN: llc -mtriple=amdgcn -verify-machineinstrs -amdgpu-prealloc-sgpr-spill-vgprs -passes=si-pre-allocate-wwm-regs -o - -mcpu=tahiti %s | FileCheck %s --check-prefix=CHECK27 8# COM: auto-generated updates might remove checks for MachineFunctionInfo reserved registers.9 10---11 12name: pre_allocate_wwm_regs_strict13tracksRegLiveness: true14body: |15 bb.0:16 liveins: $sgpr117 ; CHECK-LABEL: name: pre_allocate_wwm_regs_strict18 ; CHECK: wwmReservedRegs:19 ; CHECK-NEXT: - '$vgpr0'20 ; CHECK: liveins: $sgpr121 ; CHECK-NEXT: {{ $}}22 ; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF23 ; CHECK-NEXT: renamable $sgpr4_sgpr5 = ENTER_STRICT_WWM -1, implicit-def $exec, implicit-def $scc, implicit $exec24 ; CHECK-NEXT: $vgpr0 = V_MOV_B32_e32 0, implicit $exec25 ; CHECK-NEXT: dead $vgpr0 = V_MOV_B32_dpp $vgpr0, [[DEF]], 323, 12, 15, 0, implicit $exec26 ; CHECK-NEXT: $exec = EXIT_STRICT_WWM killed renamable $sgpr4_sgpr527 ; CHECK-NEXT: dead [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]]28 ;29 ; CHECK2-LABEL: name: pre_allocate_wwm_regs_strict30 ; CHECK2: liveins: $sgpr131 ; CHECK2-NEXT: {{ $}}32 ; CHECK2-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF33 ; CHECK2-NEXT: renamable $sgpr4_sgpr5 = ENTER_STRICT_WWM -1, implicit-def $exec, implicit-def $scc, implicit $exec34 ; CHECK2-NEXT: $vgpr0 = V_MOV_B32_e32 0, implicit $exec35 ; CHECK2-NEXT: dead $vgpr0 = V_MOV_B32_dpp $vgpr0, [[DEF]], 323, 12, 15, 0, implicit $exec36 ; CHECK2-NEXT: $exec = EXIT_STRICT_WWM killed renamable $sgpr4_sgpr537 ; CHECK2-NEXT: dead [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]]38 %0:vgpr_32 = IMPLICIT_DEF39 renamable $sgpr4_sgpr5 = ENTER_STRICT_WWM -1, implicit-def $exec, implicit-def $scc, implicit $exec40 %1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec41 %2:vgpr_32 = V_MOV_B32_dpp %1, %0, 323, 12, 15, 0, implicit $exec42 $exec = EXIT_STRICT_WWM killed renamable $sgpr4_sgpr543 %3:vgpr_32 = COPY %044...45---46 47name: pre_allocate_wwm_spill_to_vgpr48tracksRegLiveness: true49body: |50 bb.0:51 liveins: $sgpr152 ; CHECK-LABEL: name: pre_allocate_wwm_spill_to_vgpr53 ; CHECK: liveins: $sgpr154 ; CHECK-NEXT: {{ $}}55 ; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF56 ; CHECK-NEXT: dead [[SI_SPILL_S32_TO_VGPR:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr1, 0, [[DEF]]57 ; CHECK-NEXT: dead [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]]58 ;59 ; CHECK2-LABEL: name: pre_allocate_wwm_spill_to_vgpr60 ; CHECK2: wwmReservedRegs:61 ; CHECK2-NEXT: - '$vgpr0'62 ; CHECK2: liveins: $sgpr163 ; CHECK2-NEXT: {{ $}}64 ; CHECK2-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF65 ; CHECK2-NEXT: dead $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr1, 0, [[DEF]]66 ; CHECK2-NEXT: dead [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]]67 %0:vgpr_32 = IMPLICIT_DEF68 %1:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr1, 0, %069 %2:vgpr_32 = COPY %070...71