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1# RUN: llc %s -o - -mcpu=gfx1030 -O0 -run-pass=si-pre-allocate-wwm-regs | FileCheck %s2 3# Simple regression test to make sure DBG_VALUE $noreg does not assert in the pass4 5# CHECK: $vgpr0 = IMPLICIT_DEF6# CHECK: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr3, 0, $vgpr07 8--- |9 target triple = "amdgcn-amd-amdpal"10 %dx.types.ResRet.f32 = type { float, float, float, float, i32 }11 12 define dllexport amdgpu_cs void @_amdgpu_cs_main(i32 inreg noundef %globalTable, i32 inreg noundef %userdata4, <3 x i32> inreg noundef %WorkgroupId, i32 inreg noundef %MultiDispatchInfo, <3 x i32> noundef %LocalInvocationId) #0 !dbg !5 {13 #dbg_value(i32 poison, !19, !DIExpression(DW_OP_LLVM_fragment, 0, 32), !20)14 #dbg_value(%dx.types.ResRet.f32 poison, !21, !DIExpression(), !23)15 ret void, !dbg !2416 }17 18 attributes #0 = { memory(readwrite) "amdgpu-prealloc-sgpr-spill-vgprs" }19 20 !llvm.dbg.cu = !{!0}21 !llvm.module.flags = !{!3, !4}22 23 !0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus, file: !1, producer: "dxcoob 1.7.2308.16 (52da17e29)", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, globals: !2)24 !1 = !DIFile(filename: "tests\\basic_var.hlsl", directory: "")25 !2 = !{}26 !3 = !{i32 2, !"Dwarf Version", i32 5}27 !4 = !{i32 2, !"Debug Info Version", i32 3}28 !5 = distinct !DISubprogram(name: "main", scope: !1, file: !1, line: 7, type: !6, scopeLine: 7, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !0)29 !6 = !DISubroutineType(types: !7)30 !7 = !{null, !8}31 !8 = !DIDerivedType(tag: DW_TAG_typedef, name: "uint3", file: !1, baseType: !9)32 !9 = !DICompositeType(tag: DW_TAG_class_type, name: "vector<unsigned int, 3>", file: !1, size: 96, align: 32, elements: !10, templateParams: !15)33 !10 = !{!11, !13, !14}34 !11 = !DIDerivedType(tag: DW_TAG_member, name: "x", scope: !9, file: !1, baseType: !12, size: 32, align: 32, flags: DIFlagPublic)35 !12 = !DIBasicType(name: "unsigned int", size: 32, align: 32, encoding: DW_ATE_unsigned)36 !13 = !DIDerivedType(tag: DW_TAG_member, name: "y", scope: !9, file: !1, baseType: !12, size: 32, align: 32, offset: 32, flags: DIFlagPublic)37 !14 = !DIDerivedType(tag: DW_TAG_member, name: "z", scope: !9, file: !1, baseType: !12, size: 32, align: 32, offset: 64, flags: DIFlagPublic)38 !15 = !{!16, !17}39 !16 = !DITemplateTypeParameter(name: "element", type: !12)40 !17 = !DITemplateValueParameter(name: "element_count", type: !18, value: i32 3)41 !18 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed)42 !19 = !DILocalVariable(name: "dtid", arg: 1, scope: !5, file: !1, line: 7, type: !8)43 !20 = !DILocation(line: 7, column: 17, scope: !5)44 !21 = !DILocalVariable(name: "my_var", scope: !5, file: !1, line: 11, type: !22)45 !22 = !DIBasicType(name: "float", size: 32, align: 32, encoding: DW_ATE_float)46 !23 = !DILocation(line: 11, column: 9, scope: !5)47 !24 = !DILocation(line: 19, column: 1, scope: !5)48...49---50name: _amdgpu_cs_main51tracksRegLiveness: true52machineFunctionInfo:53 isEntryFunction: true54 hasSpilledSGPRs: true55 stackPtrOffsetReg: '$sgpr32'56 occupancy: 1657 sgprForEXECCopy: '$sgpr12_sgpr13'58body: |59 bb.0 (%ir-block.0):60 liveins: $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr261 62 %0:vgpr_32 = IMPLICIT_DEF63 %2:vgpr_32 = IMPLICIT_DEF64 %2:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr3, 0, %265 renamable $sgpr3 = COPY killed $sgpr266 renamable $sgpr4 = S_MOV_B32 667 %3:vgpr_32 = V_LSHL_ADD_U32_e64 killed $sgpr3, killed $sgpr4, %0, implicit $exec68 DBG_VALUE %3, $noreg, !19, !DIExpression(DW_OP_LLVM_fragment, 0, 32), debug-location !2069 DBG_VALUE $noreg, $noreg, !21, !DIExpression(), debug-location !2370 S_ENDPGM 071...72