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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 --misched=si -mattr=si-scheduler < %s | FileCheck %s3 4define amdgpu_gs void @_amdgpu_gs_main() {5; CHECK-LABEL: _amdgpu_gs_main:6; CHECK: ; %bb.0: ; %entry7; CHECK-NEXT: v_mov_b32_e32 v0, 08; CHECK-NEXT: s_mov_b32 s0, 09; CHECK-NEXT: s_mov_b32 s1, s010; CHECK-NEXT: s_mov_b32 s2, s011; CHECK-NEXT: v_mov_b32_e32 v1, v012; CHECK-NEXT: v_mov_b32_e32 v2, v013; CHECK-NEXT: v_mov_b32_e32 v3, v014; CHECK-NEXT: s_mov_b32 s3, s015; CHECK-NEXT: exp mrt0 off, off, off, off16; CHECK-NEXT: buffer_store_dwordx4 v[0:3], v0, s[0:3], 0 idxen17; CHECK-NEXT: s_endpgm18entry:19 call void @llvm.amdgcn.exp.f32(i32 0, i32 0, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, i1 false, i1 false)20 call void @llvm.amdgcn.struct.ptr.buffer.store.v4f32(<4 x float> zeroinitializer, ptr addrspace(8) zeroinitializer, i32 0, i32 0, i32 0, i32 0)21 ret void22}23 24declare void @llvm.amdgcn.exp.f32(i32 immarg, i32 immarg, float, float, float, float, i1 immarg, i1 immarg)25declare void @llvm.amdgcn.struct.ptr.buffer.store.v4f32(<4 x float>, ptr addrspace(8), i32, i32, i32, i32 immarg)26