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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn-- -amdgpu-scalarize-global-loads=false -mcpu=tahiti < %s | FileCheck %s -allow-deprecated-dag-overlap -enable-var-scope --check-prefix=SI3; RUN: llc -mtriple=amdgcn-- -amdgpu-scalarize-global-loads=false -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck %s -allow-deprecated-dag-overlap -enable-var-scope --check-prefix=VI4 5define amdgpu_kernel void @s_sext_i1_to_i32(ptr addrspace(1) %out, i32 %a, i32 %b) nounwind {6; SI-LABEL: s_sext_i1_to_i32:7; SI: ; %bb.0:8; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x99; SI-NEXT: s_waitcnt lgkmcnt(0)10; SI-NEXT: s_mov_b64 s[4:5], s[2:3]11; SI-NEXT: s_cmp_eq_u32 s4, s512; SI-NEXT: s_cselect_b64 s[4:5], -1, 013; SI-NEXT: s_mov_b32 s3, 0xf00014; SI-NEXT: s_mov_b32 s2, -115; SI-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[4:5]16; SI-NEXT: buffer_store_dword v0, off, s[0:3], 017; SI-NEXT: s_endpgm18;19; VI-LABEL: s_sext_i1_to_i32:20; VI: ; %bb.0:21; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2422; VI-NEXT: s_waitcnt lgkmcnt(0)23; VI-NEXT: s_mov_b64 s[4:5], s[2:3]24; VI-NEXT: s_cmp_eq_u32 s4, s525; VI-NEXT: s_cselect_b64 s[4:5], -1, 026; VI-NEXT: s_mov_b32 s3, 0xf00027; VI-NEXT: s_mov_b32 s2, -128; VI-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[4:5]29; VI-NEXT: buffer_store_dword v0, off, s[0:3], 030; VI-NEXT: s_endpgm31 %cmp = icmp eq i32 %a, %b32 %sext = sext i1 %cmp to i3233 store i32 %sext, ptr addrspace(1) %out, align 434 ret void35}36 37define amdgpu_kernel void @test_s_sext_i32_to_i64(ptr addrspace(1) %out, i32 %a, i32 %b, i32 %c) nounwind {38; SI-LABEL: test_s_sext_i32_to_i64:39; SI: ; %bb.0: ; %entry40; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xb41; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x942; SI-NEXT: s_mov_b32 s7, 0xf00043; SI-NEXT: s_mov_b32 s6, -144; SI-NEXT: s_waitcnt lgkmcnt(0)45; SI-NEXT: s_mul_i32 s0, s0, s146; SI-NEXT: s_add_i32 s0, s0, s247; SI-NEXT: s_ashr_i32 s1, s0, 3148; SI-NEXT: v_mov_b32_e32 v0, s049; SI-NEXT: v_mov_b32_e32 v1, s150; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 051; SI-NEXT: s_endpgm52;53; VI-LABEL: test_s_sext_i32_to_i64:54; VI: ; %bb.0: ; %entry55; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c56; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x2457; VI-NEXT: s_mov_b32 s7, 0xf00058; VI-NEXT: s_mov_b32 s6, -159; VI-NEXT: s_waitcnt lgkmcnt(0)60; VI-NEXT: s_mul_i32 s0, s0, s161; VI-NEXT: s_add_i32 s0, s0, s262; VI-NEXT: s_ashr_i32 s1, s0, 3163; VI-NEXT: v_mov_b32_e32 v0, s064; VI-NEXT: v_mov_b32_e32 v1, s165; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 066; VI-NEXT: s_endpgm67entry:68 %mul = mul i32 %a, %b69 %add = add i32 %mul, %c70 %sext = sext i32 %add to i6471 store i64 %sext, ptr addrspace(1) %out, align 872 ret void73}74 75define amdgpu_kernel void @s_sext_i1_to_i64(ptr addrspace(1) %out, i32 %a, i32 %b) nounwind {76; SI-LABEL: s_sext_i1_to_i64:77; SI: ; %bb.0:78; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x979; SI-NEXT: s_waitcnt lgkmcnt(0)80; SI-NEXT: s_mov_b64 s[4:5], s[2:3]81; SI-NEXT: s_cmp_eq_u32 s4, s582; SI-NEXT: s_cselect_b64 s[4:5], -1, 083; SI-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[4:5]84; SI-NEXT: s_mov_b32 s3, 0xf00085; SI-NEXT: s_mov_b32 s2, -186; SI-NEXT: v_mov_b32_e32 v1, v087; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 088; SI-NEXT: s_endpgm89;90; VI-LABEL: s_sext_i1_to_i64:91; VI: ; %bb.0:92; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2493; VI-NEXT: s_waitcnt lgkmcnt(0)94; VI-NEXT: s_mov_b64 s[4:5], s[2:3]95; VI-NEXT: s_cmp_eq_u32 s4, s596; VI-NEXT: s_cselect_b64 s[4:5], -1, 097; VI-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[4:5]98; VI-NEXT: s_mov_b32 s3, 0xf00099; VI-NEXT: s_mov_b32 s2, -1100; VI-NEXT: v_mov_b32_e32 v1, v0101; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0102; VI-NEXT: s_endpgm103 %cmp = icmp eq i32 %a, %b104 %sext = sext i1 %cmp to i64105 store i64 %sext, ptr addrspace(1) %out, align 8106 ret void107}108 109define amdgpu_kernel void @s_sext_i32_to_i64(ptr addrspace(1) %out, i32 %a) nounwind {110; SI-LABEL: s_sext_i32_to_i64:111; SI: ; %bb.0:112; SI-NEXT: s_load_dword s6, s[4:5], 0xb113; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9114; SI-NEXT: s_mov_b32 s3, 0xf000115; SI-NEXT: s_mov_b32 s2, -1116; SI-NEXT: s_waitcnt lgkmcnt(0)117; SI-NEXT: s_ashr_i32 s4, s6, 31118; SI-NEXT: v_mov_b32_e32 v0, s6119; SI-NEXT: v_mov_b32_e32 v1, s4120; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0121; SI-NEXT: s_endpgm122;123; VI-LABEL: s_sext_i32_to_i64:124; VI: ; %bb.0:125; VI-NEXT: s_load_dword s6, s[4:5], 0x2c126; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24127; VI-NEXT: s_mov_b32 s3, 0xf000128; VI-NEXT: s_mov_b32 s2, -1129; VI-NEXT: s_waitcnt lgkmcnt(0)130; VI-NEXT: s_ashr_i32 s4, s6, 31131; VI-NEXT: v_mov_b32_e32 v0, s6132; VI-NEXT: v_mov_b32_e32 v1, s4133; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0134; VI-NEXT: s_endpgm135 %sext = sext i32 %a to i64136 store i64 %sext, ptr addrspace(1) %out, align 8137 ret void138}139 140define amdgpu_kernel void @v_sext_i32_to_i64(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind {141; SI-LABEL: v_sext_i32_to_i64:142; SI: ; %bb.0:143; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9144; SI-NEXT: s_mov_b32 s7, 0xf000145; SI-NEXT: s_mov_b32 s6, -1146; SI-NEXT: s_mov_b32 s10, s6147; SI-NEXT: s_mov_b32 s11, s7148; SI-NEXT: s_waitcnt lgkmcnt(0)149; SI-NEXT: s_mov_b32 s8, s2150; SI-NEXT: s_mov_b32 s9, s3151; SI-NEXT: buffer_load_dword v0, off, s[8:11], 0152; SI-NEXT: s_mov_b32 s4, s0153; SI-NEXT: s_mov_b32 s5, s1154; SI-NEXT: s_waitcnt vmcnt(0)155; SI-NEXT: v_ashrrev_i32_e32 v1, 31, v0156; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0157; SI-NEXT: s_endpgm158;159; VI-LABEL: v_sext_i32_to_i64:160; VI: ; %bb.0:161; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24162; VI-NEXT: s_mov_b32 s7, 0xf000163; VI-NEXT: s_mov_b32 s6, -1164; VI-NEXT: s_mov_b32 s10, s6165; VI-NEXT: s_mov_b32 s11, s7166; VI-NEXT: s_waitcnt lgkmcnt(0)167; VI-NEXT: s_mov_b32 s8, s2168; VI-NEXT: s_mov_b32 s9, s3169; VI-NEXT: buffer_load_dword v0, off, s[8:11], 0170; VI-NEXT: s_mov_b32 s4, s0171; VI-NEXT: s_mov_b32 s5, s1172; VI-NEXT: s_waitcnt vmcnt(0)173; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v0174; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0175; VI-NEXT: s_endpgm176 %val = load i32, ptr addrspace(1) %in, align 4177 %sext = sext i32 %val to i64178 store i64 %sext, ptr addrspace(1) %out, align 8179 ret void180}181 182define amdgpu_kernel void @s_sext_i16_to_i64(ptr addrspace(1) %out, i16 %a) nounwind {183; SI-LABEL: s_sext_i16_to_i64:184; SI: ; %bb.0:185; SI-NEXT: s_load_dword s6, s[4:5], 0xb186; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9187; SI-NEXT: s_mov_b32 s3, 0xf000188; SI-NEXT: s_mov_b32 s2, -1189; SI-NEXT: s_waitcnt lgkmcnt(0)190; SI-NEXT: s_bfe_i64 s[4:5], s[6:7], 0x100000191; SI-NEXT: v_mov_b32_e32 v0, s4192; SI-NEXT: v_mov_b32_e32 v1, s5193; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0194; SI-NEXT: s_endpgm195;196; VI-LABEL: s_sext_i16_to_i64:197; VI: ; %bb.0:198; VI-NEXT: s_load_dword s6, s[4:5], 0x2c199; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24200; VI-NEXT: s_mov_b32 s3, 0xf000201; VI-NEXT: s_mov_b32 s2, -1202; VI-NEXT: s_waitcnt lgkmcnt(0)203; VI-NEXT: s_bfe_i64 s[4:5], s[6:7], 0x100000204; VI-NEXT: v_mov_b32_e32 v0, s4205; VI-NEXT: v_mov_b32_e32 v1, s5206; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0207; VI-NEXT: s_endpgm208 %sext = sext i16 %a to i64209 store i64 %sext, ptr addrspace(1) %out, align 8210 ret void211}212 213define amdgpu_kernel void @s_sext_i1_to_i16(ptr addrspace(1) %out, i32 %a, i32 %b) nounwind {214; SI-LABEL: s_sext_i1_to_i16:215; SI: ; %bb.0:216; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9217; SI-NEXT: s_waitcnt lgkmcnt(0)218; SI-NEXT: s_mov_b64 s[4:5], s[2:3]219; SI-NEXT: s_cmp_eq_u32 s4, s5220; SI-NEXT: s_cselect_b64 s[4:5], -1, 0221; SI-NEXT: s_mov_b32 s3, 0xf000222; SI-NEXT: s_mov_b32 s2, -1223; SI-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[4:5]224; SI-NEXT: buffer_store_short v0, off, s[0:3], 0225; SI-NEXT: s_endpgm226;227; VI-LABEL: s_sext_i1_to_i16:228; VI: ; %bb.0:229; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24230; VI-NEXT: s_waitcnt lgkmcnt(0)231; VI-NEXT: s_mov_b64 s[4:5], s[2:3]232; VI-NEXT: s_cmp_eq_u32 s4, s5233; VI-NEXT: s_cselect_b64 s[4:5], -1, 0234; VI-NEXT: s_mov_b32 s3, 0xf000235; VI-NEXT: s_mov_b32 s2, -1236; VI-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[4:5]237; VI-NEXT: buffer_store_short v0, off, s[0:3], 0238; VI-NEXT: s_endpgm239 %cmp = icmp eq i32 %a, %b240 %sext = sext i1 %cmp to i16241 store i16 %sext, ptr addrspace(1) %out242 ret void243}244 245; This purpose of this test is to make sure the i16 = sign_extend i1 node246; makes it all the way throught the legalizer/optimizer to make sure247; we select this correctly. In the s_sext_i1_to_i16, the sign_extend node248; is optimized to a select very early.249define amdgpu_kernel void @s_sext_i1_to_i16_with_and(ptr addrspace(1) %out, i32 %a, i32 %b, i32 %c, i32 %d) nounwind {250; SI-LABEL: s_sext_i1_to_i16_with_and:251; SI: ; %bb.0:252; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xb253; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9254; SI-NEXT: s_mov_b32 s7, 0xf000255; SI-NEXT: s_mov_b32 s6, -1256; SI-NEXT: s_waitcnt lgkmcnt(0)257; SI-NEXT: s_cmp_eq_u32 s0, s1258; SI-NEXT: s_cselect_b64 s[0:1], -1, 0259; SI-NEXT: s_cmp_eq_u32 s2, s3260; SI-NEXT: s_cselect_b64 s[2:3], -1, 0261; SI-NEXT: s_and_b64 s[0:1], s[0:1], s[2:3]262; SI-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[0:1]263; SI-NEXT: buffer_store_short v0, off, s[4:7], 0264; SI-NEXT: s_endpgm265;266; VI-LABEL: s_sext_i1_to_i16_with_and:267; VI: ; %bb.0:268; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c269; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24270; VI-NEXT: s_mov_b32 s7, 0xf000271; VI-NEXT: s_mov_b32 s6, -1272; VI-NEXT: s_waitcnt lgkmcnt(0)273; VI-NEXT: s_cmp_eq_u32 s0, s1274; VI-NEXT: s_cselect_b64 s[0:1], -1, 0275; VI-NEXT: s_cmp_eq_u32 s2, s3276; VI-NEXT: s_cselect_b64 s[2:3], -1, 0277; VI-NEXT: s_and_b64 s[0:1], s[0:1], s[2:3]278; VI-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[0:1]279; VI-NEXT: buffer_store_short v0, off, s[4:7], 0280; VI-NEXT: s_endpgm281 %cmp0 = icmp eq i32 %a, %b282 %cmp1 = icmp eq i32 %c, %d283 %cmp = and i1 %cmp0, %cmp1284 %sext = sext i1 %cmp to i16285 store i16 %sext, ptr addrspace(1) %out286 ret void287}288 289define amdgpu_kernel void @v_sext_i1_to_i16_with_and(ptr addrspace(1) %out, i32 %a, i32 %b, i32 %c) nounwind {290; SI-LABEL: v_sext_i1_to_i16_with_and:291; SI: ; %bb.0:292; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xb293; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9294; SI-NEXT: s_mov_b32 s7, 0xf000295; SI-NEXT: s_mov_b32 s6, -1296; SI-NEXT: s_waitcnt lgkmcnt(0)297; SI-NEXT: s_cmp_eq_u32 s1, s2298; SI-NEXT: v_cmp_eq_u32_e32 vcc, s0, v0299; SI-NEXT: s_cselect_b64 s[0:1], -1, 0300; SI-NEXT: s_and_b64 s[0:1], vcc, s[0:1]301; SI-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[0:1]302; SI-NEXT: buffer_store_short v0, off, s[4:7], 0303; SI-NEXT: s_endpgm304;305; VI-LABEL: v_sext_i1_to_i16_with_and:306; VI: ; %bb.0:307; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c308; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24309; VI-NEXT: s_mov_b32 s7, 0xf000310; VI-NEXT: s_mov_b32 s6, -1311; VI-NEXT: s_waitcnt lgkmcnt(0)312; VI-NEXT: s_cmp_eq_u32 s1, s2313; VI-NEXT: v_cmp_eq_u32_e32 vcc, s0, v0314; VI-NEXT: s_cselect_b64 s[0:1], -1, 0315; VI-NEXT: s_and_b64 s[0:1], vcc, s[0:1]316; VI-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[0:1]317; VI-NEXT: buffer_store_short v0, off, s[4:7], 0318; VI-NEXT: s_endpgm319 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #1320 %cmp0 = icmp eq i32 %a, %tid321 %cmp1 = icmp eq i32 %b, %c322 %cmp = and i1 %cmp0, %cmp1323 %sext = sext i1 %cmp to i16324 store i16 %sext, ptr addrspace(1) %out325 ret void326}327 328; FIXME: We end up with a v_bfe instruction, because the i16 srl329; gets selected to a v_lshrrev_b16 instructions, so the input to330; the bfe is a vector registers. To fix this we need to be able to331; optimize:332; t29: i16 = truncate t10333; t55: i16 = srl t29, Constant:i32<8>334; t63: i32 = any_extend t55335; t64: i32 = sign_extend_inreg t63, ValueType:ch:i8336define amdgpu_kernel void @s_sext_v4i8_to_v4i32(ptr addrspace(1) %out, i32 %a) nounwind {337; SI-LABEL: s_sext_v4i8_to_v4i32:338; SI: ; %bb.0:339; SI-NEXT: s_load_dword s6, s[4:5], 0xb340; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9341; SI-NEXT: s_mov_b32 s3, 0xf000342; SI-NEXT: s_mov_b32 s2, -1343; SI-NEXT: s_waitcnt lgkmcnt(0)344; SI-NEXT: s_ashr_i32 s4, s6, 24345; SI-NEXT: s_bfe_i32 s5, s6, 0x80010346; SI-NEXT: s_bfe_i32 s7, s6, 0x80008347; SI-NEXT: s_sext_i32_i8 s6, s6348; SI-NEXT: v_mov_b32_e32 v0, s6349; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0350; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)351; SI-NEXT: v_mov_b32_e32 v0, s7352; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0353; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)354; SI-NEXT: v_mov_b32_e32 v0, s5355; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0356; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)357; SI-NEXT: v_mov_b32_e32 v0, s4358; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0359; SI-NEXT: s_waitcnt vmcnt(0)360; SI-NEXT: s_endpgm361;362; VI-LABEL: s_sext_v4i8_to_v4i32:363; VI: ; %bb.0:364; VI-NEXT: s_load_dword s6, s[4:5], 0x2c365; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24366; VI-NEXT: s_mov_b32 s3, 0xf000367; VI-NEXT: s_mov_b32 s2, -1368; VI-NEXT: s_waitcnt lgkmcnt(0)369; VI-NEXT: s_ashr_i32 s4, s6, 24370; VI-NEXT: s_bfe_i32 s5, s6, 0x80010371; VI-NEXT: s_bfe_i32 s7, s6, 0x80008372; VI-NEXT: s_sext_i32_i8 s6, s6373; VI-NEXT: v_mov_b32_e32 v0, s6374; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0375; VI-NEXT: s_waitcnt vmcnt(0)376; VI-NEXT: v_mov_b32_e32 v0, s7377; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0378; VI-NEXT: s_waitcnt vmcnt(0)379; VI-NEXT: v_mov_b32_e32 v0, s5380; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0381; VI-NEXT: s_waitcnt vmcnt(0)382; VI-NEXT: v_mov_b32_e32 v0, s4383; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0384; VI-NEXT: s_waitcnt vmcnt(0)385; VI-NEXT: s_endpgm386 %cast = bitcast i32 %a to <4 x i8>387 %ext = sext <4 x i8> %cast to <4 x i32>388 %elt0 = extractelement <4 x i32> %ext, i32 0389 %elt1 = extractelement <4 x i32> %ext, i32 1390 %elt2 = extractelement <4 x i32> %ext, i32 2391 %elt3 = extractelement <4 x i32> %ext, i32 3392 store volatile i32 %elt0, ptr addrspace(1) %out393 store volatile i32 %elt1, ptr addrspace(1) %out394 store volatile i32 %elt2, ptr addrspace(1) %out395 store volatile i32 %elt3, ptr addrspace(1) %out396 ret void397}398 399; FIXME: need to optimize same sequence as above test to avoid400; this shift.401define amdgpu_kernel void @v_sext_v4i8_to_v4i32(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind {402; SI-LABEL: v_sext_v4i8_to_v4i32:403; SI: ; %bb.0:404; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9405; SI-NEXT: s_mov_b32 s7, 0xf000406; SI-NEXT: s_mov_b32 s6, -1407; SI-NEXT: s_mov_b32 s10, s6408; SI-NEXT: s_mov_b32 s11, s7409; SI-NEXT: s_waitcnt lgkmcnt(0)410; SI-NEXT: s_mov_b32 s8, s2411; SI-NEXT: s_mov_b32 s9, s3412; SI-NEXT: buffer_load_dword v0, off, s[8:11], 0413; SI-NEXT: s_mov_b32 s4, s0414; SI-NEXT: s_mov_b32 s5, s1415; SI-NEXT: s_waitcnt vmcnt(0)416; SI-NEXT: v_ashrrev_i32_e32 v1, 24, v0417; SI-NEXT: v_bfe_i32 v2, v0, 16, 8418; SI-NEXT: v_bfe_i32 v3, v0, 8, 8419; SI-NEXT: v_bfe_i32 v0, v0, 0, 8420; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0421; SI-NEXT: s_waitcnt vmcnt(0)422; SI-NEXT: buffer_store_dword v3, off, s[4:7], 0423; SI-NEXT: s_waitcnt vmcnt(0)424; SI-NEXT: buffer_store_dword v2, off, s[4:7], 0425; SI-NEXT: s_waitcnt vmcnt(0)426; SI-NEXT: buffer_store_dword v1, off, s[4:7], 0427; SI-NEXT: s_waitcnt vmcnt(0)428; SI-NEXT: s_endpgm429;430; VI-LABEL: v_sext_v4i8_to_v4i32:431; VI: ; %bb.0:432; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24433; VI-NEXT: s_mov_b32 s7, 0xf000434; VI-NEXT: s_mov_b32 s6, -1435; VI-NEXT: s_mov_b32 s10, s6436; VI-NEXT: s_mov_b32 s11, s7437; VI-NEXT: s_waitcnt lgkmcnt(0)438; VI-NEXT: s_mov_b32 s8, s2439; VI-NEXT: s_mov_b32 s9, s3440; VI-NEXT: buffer_load_dword v0, off, s[8:11], 0441; VI-NEXT: s_mov_b32 s4, s0442; VI-NEXT: s_mov_b32 s5, s1443; VI-NEXT: s_waitcnt vmcnt(0)444; VI-NEXT: v_ashrrev_i32_e32 v1, 24, v0445; VI-NEXT: v_bfe_i32 v2, v0, 16, 8446; VI-NEXT: v_bfe_i32 v3, v0, 8, 8447; VI-NEXT: v_bfe_i32 v0, v0, 0, 8448; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0449; VI-NEXT: s_waitcnt vmcnt(0)450; VI-NEXT: buffer_store_dword v3, off, s[4:7], 0451; VI-NEXT: s_waitcnt vmcnt(0)452; VI-NEXT: buffer_store_dword v2, off, s[4:7], 0453; VI-NEXT: s_waitcnt vmcnt(0)454; VI-NEXT: buffer_store_dword v1, off, s[4:7], 0455; VI-NEXT: s_waitcnt vmcnt(0)456; VI-NEXT: s_endpgm457 %a = load i32, ptr addrspace(1) %in458 %cast = bitcast i32 %a to <4 x i8>459 %ext = sext <4 x i8> %cast to <4 x i32>460 %elt0 = extractelement <4 x i32> %ext, i32 0461 %elt1 = extractelement <4 x i32> %ext, i32 1462 %elt2 = extractelement <4 x i32> %ext, i32 2463 %elt3 = extractelement <4 x i32> %ext, i32 3464 store volatile i32 %elt0, ptr addrspace(1) %out465 store volatile i32 %elt1, ptr addrspace(1) %out466 store volatile i32 %elt2, ptr addrspace(1) %out467 store volatile i32 %elt3, ptr addrspace(1) %out468 ret void469}470 471; FIXME: s_bfe_i64, same on SI and VI472define amdgpu_kernel void @s_sext_v4i16_to_v4i32(ptr addrspace(1) %out, i64 %a) nounwind {473; SI-LABEL: s_sext_v4i16_to_v4i32:474; SI: ; %bb.0:475; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9476; SI-NEXT: s_mov_b32 s7, 0xf000477; SI-NEXT: s_mov_b32 s6, -1478; SI-NEXT: s_waitcnt lgkmcnt(0)479; SI-NEXT: s_mov_b32 s5, s1480; SI-NEXT: s_ashr_i32 s1, s2, 16481; SI-NEXT: s_sext_i32_i16 s2, s2482; SI-NEXT: s_mov_b32 s4, s0483; SI-NEXT: v_mov_b32_e32 v0, s2484; SI-NEXT: s_ashr_i32 s0, s3, 16485; SI-NEXT: s_sext_i32_i16 s3, s3486; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0487; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)488; SI-NEXT: v_mov_b32_e32 v0, s1489; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0490; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)491; SI-NEXT: v_mov_b32_e32 v0, s3492; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0493; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)494; SI-NEXT: v_mov_b32_e32 v0, s0495; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0496; SI-NEXT: s_waitcnt vmcnt(0)497; SI-NEXT: s_endpgm498;499; VI-LABEL: s_sext_v4i16_to_v4i32:500; VI: ; %bb.0:501; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24502; VI-NEXT: s_mov_b32 s7, 0xf000503; VI-NEXT: s_mov_b32 s6, -1504; VI-NEXT: s_waitcnt lgkmcnt(0)505; VI-NEXT: s_mov_b32 s5, s1506; VI-NEXT: s_ashr_i32 s1, s2, 16507; VI-NEXT: s_sext_i32_i16 s2, s2508; VI-NEXT: s_mov_b32 s4, s0509; VI-NEXT: v_mov_b32_e32 v0, s2510; VI-NEXT: s_ashr_i32 s0, s3, 16511; VI-NEXT: s_sext_i32_i16 s3, s3512; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0513; VI-NEXT: s_waitcnt vmcnt(0)514; VI-NEXT: v_mov_b32_e32 v0, s1515; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0516; VI-NEXT: s_waitcnt vmcnt(0)517; VI-NEXT: v_mov_b32_e32 v0, s3518; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0519; VI-NEXT: s_waitcnt vmcnt(0)520; VI-NEXT: v_mov_b32_e32 v0, s0521; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0522; VI-NEXT: s_waitcnt vmcnt(0)523; VI-NEXT: s_endpgm524 %cast = bitcast i64 %a to <4 x i16>525 %ext = sext <4 x i16> %cast to <4 x i32>526 %elt0 = extractelement <4 x i32> %ext, i32 0527 %elt1 = extractelement <4 x i32> %ext, i32 1528 %elt2 = extractelement <4 x i32> %ext, i32 2529 %elt3 = extractelement <4 x i32> %ext, i32 3530 store volatile i32 %elt0, ptr addrspace(1) %out531 store volatile i32 %elt1, ptr addrspace(1) %out532 store volatile i32 %elt2, ptr addrspace(1) %out533 store volatile i32 %elt3, ptr addrspace(1) %out534 ret void535}536 537define amdgpu_kernel void @v_sext_v4i16_to_v4i32(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind {538; SI-LABEL: v_sext_v4i16_to_v4i32:539; SI: ; %bb.0:540; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9541; SI-NEXT: s_mov_b32 s7, 0xf000542; SI-NEXT: s_mov_b32 s6, -1543; SI-NEXT: s_mov_b32 s10, s6544; SI-NEXT: s_mov_b32 s11, s7545; SI-NEXT: s_waitcnt lgkmcnt(0)546; SI-NEXT: s_mov_b32 s8, s2547; SI-NEXT: s_mov_b32 s9, s3548; SI-NEXT: buffer_load_dwordx2 v[0:1], off, s[8:11], 0549; SI-NEXT: s_mov_b32 s4, s0550; SI-NEXT: s_mov_b32 s5, s1551; SI-NEXT: s_waitcnt vmcnt(0)552; SI-NEXT: v_ashrrev_i32_e32 v3, 16, v0553; SI-NEXT: v_bfe_i32 v0, v0, 0, 16554; SI-NEXT: v_ashrrev_i32_e32 v2, 16, v1555; SI-NEXT: v_bfe_i32 v1, v1, 0, 16556; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0557; SI-NEXT: s_waitcnt vmcnt(0)558; SI-NEXT: buffer_store_dword v3, off, s[4:7], 0559; SI-NEXT: s_waitcnt vmcnt(0)560; SI-NEXT: buffer_store_dword v1, off, s[4:7], 0561; SI-NEXT: s_waitcnt vmcnt(0)562; SI-NEXT: buffer_store_dword v2, off, s[4:7], 0563; SI-NEXT: s_waitcnt vmcnt(0)564; SI-NEXT: s_endpgm565;566; VI-LABEL: v_sext_v4i16_to_v4i32:567; VI: ; %bb.0:568; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24569; VI-NEXT: s_mov_b32 s7, 0xf000570; VI-NEXT: s_mov_b32 s6, -1571; VI-NEXT: s_mov_b32 s10, s6572; VI-NEXT: s_mov_b32 s11, s7573; VI-NEXT: s_waitcnt lgkmcnt(0)574; VI-NEXT: s_mov_b32 s8, s2575; VI-NEXT: s_mov_b32 s9, s3576; VI-NEXT: buffer_load_dwordx2 v[0:1], off, s[8:11], 0577; VI-NEXT: s_mov_b32 s4, s0578; VI-NEXT: s_mov_b32 s5, s1579; VI-NEXT: s_waitcnt vmcnt(0)580; VI-NEXT: v_ashrrev_i32_e32 v3, 16, v0581; VI-NEXT: v_bfe_i32 v0, v0, 0, 16582; VI-NEXT: v_ashrrev_i32_e32 v2, 16, v1583; VI-NEXT: v_bfe_i32 v1, v1, 0, 16584; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0585; VI-NEXT: s_waitcnt vmcnt(0)586; VI-NEXT: buffer_store_dword v3, off, s[4:7], 0587; VI-NEXT: s_waitcnt vmcnt(0)588; VI-NEXT: buffer_store_dword v1, off, s[4:7], 0589; VI-NEXT: s_waitcnt vmcnt(0)590; VI-NEXT: buffer_store_dword v2, off, s[4:7], 0591; VI-NEXT: s_waitcnt vmcnt(0)592; VI-NEXT: s_endpgm593 %a = load i64, ptr addrspace(1) %in594 %cast = bitcast i64 %a to <4 x i16>595 %ext = sext <4 x i16> %cast to <4 x i32>596 %elt0 = extractelement <4 x i32> %ext, i32 0597 %elt1 = extractelement <4 x i32> %ext, i32 1598 %elt2 = extractelement <4 x i32> %ext, i32 2599 %elt3 = extractelement <4 x i32> %ext, i32 3600 store volatile i32 %elt0, ptr addrspace(1) %out601 store volatile i32 %elt1, ptr addrspace(1) %out602 store volatile i32 %elt2, ptr addrspace(1) %out603 store volatile i32 %elt3, ptr addrspace(1) %out604 ret void605}606 607declare i32 @llvm.amdgcn.workitem.id.x() #1608 609attributes #1 = { nounwind readnone }610