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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 62; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx950 < %s | FileCheck %s3 4define amdgpu_kernel void @memoryIntrinstic(ptr addrspace(3) %inptr, i1 %cond, ptr addrspace(3) %outptr) {5; CHECK-LABEL: memoryIntrinstic:6; CHECK: ; %bb.0:7; CHECK-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x08; CHECK-NEXT: s_waitcnt lgkmcnt(0)9; CHECK-NEXT: s_bitcmp0_b32 s1, 010; CHECK-NEXT: s_cbranch_scc0 .LBB0_211; CHECK-NEXT: ; %bb.1: ; %else12; CHECK-NEXT: v_mov_b32_e32 v0, s013; CHECK-NEXT: ds_read_b64_tr_b16 v[2:3], v0 offset:819214; CHECK-NEXT: s_mov_b32 s1, 0x706030215; CHECK-NEXT: s_mov_b32 s3, 0x504010016; CHECK-NEXT: s_waitcnt lgkmcnt(0)17; CHECK-NEXT: v_perm_b32 v0, v3, v2, s118; CHECK-NEXT: v_perm_b32 v1, v3, v2, s319; CHECK-NEXT: s_cbranch_execz .LBB0_320; CHECK-NEXT: s_branch .LBB0_421; CHECK-NEXT: .LBB0_2:22; CHECK-NEXT: ; implicit-def: $vgpr123; CHECK-NEXT: .LBB0_3: ; %then24; CHECK-NEXT: v_mov_b32_e32 v0, s025; CHECK-NEXT: ds_read_b64_tr_b16 v[2:3], v0 offset:819226; CHECK-NEXT: s_mov_b32 s0, 0x504010027; CHECK-NEXT: s_mov_b32 s1, 0x706030228; CHECK-NEXT: s_waitcnt lgkmcnt(0)29; CHECK-NEXT: v_perm_b32 v0, v3, v2, s030; CHECK-NEXT: v_perm_b32 v1, v3, v2, s131; CHECK-NEXT: .LBB0_4: ; %end32; CHECK-NEXT: v_mov_b32_e32 v2, s233; CHECK-NEXT: ds_write_b64 v2, v[0:1]34; CHECK-NEXT: s_endpgm35 %gep0 = getelementptr ptr addrspace(3), ptr addrspace(3) %inptr, i32 204836 br i1 %cond, label %then, label %else37 38then:39 %load0 = tail call <4 x half> @llvm.amdgcn.ds.read.tr16.b64.v4f16(ptr addrspace(3) %gep0)40 %shuf0 = shufflevector <4 x half> %load0, <4 x half> %load0, <4 x i32> <i32 0, i32 2, i32 1, i32 3>41 br label %end42 43else:44 %load1 = tail call <4 x half> @llvm.amdgcn.ds.read.tr16.b64.v4f16(ptr addrspace(3) %gep0)45 %shuf1 = shufflevector <4 x half> %load1, <4 x half> %load1, <4 x i32> <i32 1, i32 3, i32 0, i32 2>46 br label %end47 48end:49 %res = phi <4 x half> [ %shuf0, %then ], [ %shuf1, %else ]50 store <4 x half> %res, ptr addrspace(3) %outptr51 ret void52}53 54define amdgpu_kernel void @badIntrinsicUse(ptr addrspace(3) %inptr, i1 %cond, ptr addrspace(3) %outptr, <4 x i32> %rsrc) {55; CHECK-LABEL: badIntrinsicUse:56; CHECK: ; %bb.0:57; CHECK-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x058; CHECK-NEXT: s_waitcnt lgkmcnt(0)59; CHECK-NEXT: s_and_b32 s1, s1, 160; CHECK-NEXT: s_add_i32 s3, s0, 0x200061; CHECK-NEXT: s_cmp_eq_u32 s1, 062; CHECK-NEXT: s_cbranch_scc0 .LBB1_263; CHECK-NEXT: ; %bb.1: ; %else64; CHECK-NEXT: v_mov_b32_e32 v0, s365; CHECK-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x1066; CHECK-NEXT: ds_read_b64_tr_b16 v[2:3], v067; CHECK-NEXT: s_mov_b32 s0, 0x706030268; CHECK-NEXT: s_waitcnt lgkmcnt(0)69; CHECK-NEXT: buffer_store_dword v0, off, s[4:7], 070; CHECK-NEXT: v_perm_b32 v0, v3, v2, s071; CHECK-NEXT: s_mov_b32 s0, 0x504010072; CHECK-NEXT: v_perm_b32 v1, v3, v2, s073; CHECK-NEXT: s_cbranch_execz .LBB1_374; CHECK-NEXT: s_branch .LBB1_475; CHECK-NEXT: .LBB1_2:76; CHECK-NEXT: ; implicit-def: $vgpr177; CHECK-NEXT: .LBB1_3: ; %then78; CHECK-NEXT: v_mov_b32_e32 v0, s379; CHECK-NEXT: ds_read_b64_tr_b16 v[2:3], v080; CHECK-NEXT: s_mov_b32 s0, 0x504010081; CHECK-NEXT: s_mov_b32 s1, 0x706030282; CHECK-NEXT: s_waitcnt lgkmcnt(0)83; CHECK-NEXT: v_perm_b32 v0, v3, v2, s084; CHECK-NEXT: v_perm_b32 v1, v3, v2, s185; CHECK-NEXT: .LBB1_4: ; %end86; CHECK-NEXT: v_mov_b32_e32 v2, s287; CHECK-NEXT: ds_write_b64 v2, v[0:1]88; CHECK-NEXT: s_endpgm89 %gep0 = getelementptr ptr addrspace(3), ptr addrspace(3) %inptr, i32 204890 br i1 %cond, label %then, label %else91 92then:93 %load0 = tail call <4 x half> @llvm.amdgcn.ds.read.tr16.b64.v4f16(ptr addrspace(3) %gep0)94 %shuf0 = shufflevector <4 x half> %load0, <4 x half> %load0, <4 x i32> <i32 0, i32 2, i32 1, i32 3>95 br label %end96 97else:98 %load1 = tail call <4 x half> @llvm.amdgcn.ds.read.tr16.b64.v4f16(ptr addrspace(3) %gep0)99 call void @llvm.amdgcn.raw.buffer.store(ptr addrspace(3) %gep0, <4 x i32> %rsrc, i32 0, i32 0, i32 0)100 %shuf1 = shufflevector <4 x half> %load1, <4 x half> %load1, <4 x i32> <i32 1, i32 3, i32 0, i32 2>101 br label %end102 103end:104 %res = phi <4 x half> [ %shuf0, %then ], [ %shuf1, %else ]105 store <4 x half> %res, ptr addrspace(3) %outptr106 ret void107}108 109define amdgpu_kernel void @badIntrinsicUse2(ptr addrspace(3) %inptr, i1 %cond, ptr addrspace(3) %outptr, ptr addrspace(3) %outptr1) {110; CHECK-LABEL: badIntrinsicUse2:111; CHECK: ; %bb.0:112; CHECK-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0113; CHECK-NEXT: s_waitcnt lgkmcnt(0)114; CHECK-NEXT: s_and_b32 s1, s1, 1115; CHECK-NEXT: s_add_i32 s4, s0, 0x2000116; CHECK-NEXT: s_cmp_eq_u32 s1, 0117; CHECK-NEXT: s_cbranch_scc0 .LBB2_2118; CHECK-NEXT: ; %bb.1: ; %else119; CHECK-NEXT: v_mov_b32_e32 v0, s4120; CHECK-NEXT: ds_read_b64_tr_b16 v[2:3], v0121; CHECK-NEXT: v_mov_b32_e32 v0, s3122; CHECK-NEXT: v_mov_b32_e32 v1, s4123; CHECK-NEXT: s_mov_b32 s0, 0x7060302124; CHECK-NEXT: ds_write_b32 v0, v1125; CHECK-NEXT: s_waitcnt lgkmcnt(1)126; CHECK-NEXT: v_perm_b32 v0, v3, v2, s0127; CHECK-NEXT: s_mov_b32 s0, 0x5040100128; CHECK-NEXT: v_perm_b32 v1, v3, v2, s0129; CHECK-NEXT: s_cbranch_execz .LBB2_3130; CHECK-NEXT: s_branch .LBB2_4131; CHECK-NEXT: .LBB2_2:132; CHECK-NEXT: ; implicit-def: $vgpr1133; CHECK-NEXT: .LBB2_3: ; %then134; CHECK-NEXT: v_mov_b32_e32 v0, s4135; CHECK-NEXT: ds_read_b64_tr_b16 v[2:3], v0136; CHECK-NEXT: s_mov_b32 s0, 0x5040100137; CHECK-NEXT: s_mov_b32 s1, 0x7060302138; CHECK-NEXT: s_waitcnt lgkmcnt(0)139; CHECK-NEXT: v_perm_b32 v0, v3, v2, s0140; CHECK-NEXT: v_perm_b32 v1, v3, v2, s1141; CHECK-NEXT: .LBB2_4: ; %end142; CHECK-NEXT: v_mov_b32_e32 v2, s2143; CHECK-NEXT: ds_write_b64 v2, v[0:1]144; CHECK-NEXT: s_endpgm145 %gep0 = getelementptr ptr addrspace(3), ptr addrspace(3) %inptr, i32 2048146 br i1 %cond, label %then, label %else147 148then:149 %load0 = tail call <4 x half> @llvm.amdgcn.ds.read.tr16.b64.v4f16(ptr addrspace(3) %gep0)150 %shuf0 = shufflevector <4 x half> %load0, <4 x half> %load0, <4 x i32> <i32 0, i32 2, i32 1, i32 3>151 br label %end152 153else:154 %load1 = tail call <4 x half> @llvm.amdgcn.ds.read.tr16.b64.v4f16(ptr addrspace(3) %gep0)155 %gep1 = call ptr addrspace(3) @llvm.amdgcn.readfirstlane(ptr addrspace(3) %gep0)156 store ptr addrspace(3) %gep1, ptr addrspace(3) %outptr1157 %shuf1 = shufflevector <4 x half> %load1, <4 x half> %load1, <4 x i32> <i32 1, i32 3, i32 0, i32 2>158 br label %end159 160end:161 %res = phi <4 x half> [ %shuf0, %then ], [ %shuf1, %else ]162 store <4 x half> %res, ptr addrspace(3) %outptr163 ret void164}165