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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs -run-pass=machine-sink -o - %s | FileCheck -check-prefixes=GFX10 %s3 4# Test that MachineSink pass respects block prologues when sinking instructions.5# Specifically an instruction must not be sunk before exec mask manipulation.6 7---8name: _amdgpu_hs_main9alignment: 110tracksRegLiveness: true11machineFunctionInfo:12 isEntryFunction: true13body: |14 ; GFX10-LABEL: name: _amdgpu_hs_main15 ; GFX10: bb.0:16 ; GFX10-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)17 ; GFX10-NEXT: {{ $}}18 ; GFX10-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF19 ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 820 ; GFX10-NEXT: [[V_BFE_U32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_U32_e64 [[DEF]], 8, 5, implicit $exec21 ; GFX10-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 522 ; GFX10-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 [[V_BFE_U32_e64_]], killed [[S_MOV_B32_1]], implicit $exec23 ; GFX10-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[V_CMP_NE_U32_e64_]], -1, implicit-def $scc24 ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[S_XOR_B32_]], $exec_lo, implicit-def $scc25 ; GFX10-NEXT: [[S_XOR_B32_1:%[0-9]+]]:sreg_32 = S_XOR_B32 $exec_lo, [[S_AND_B32_]], implicit-def $scc26 ; GFX10-NEXT: $exec_lo = S_MOV_B32_term [[S_AND_B32_]]27 ; GFX10-NEXT: S_CBRANCH_EXECZ %bb.2, implicit $exec28 ; GFX10-NEXT: S_BRANCH %bb.129 ; GFX10-NEXT: {{ $}}30 ; GFX10-NEXT: bb.1:31 ; GFX10-NEXT: successors: %bb.2(0x80000000)32 ; GFX10-NEXT: {{ $}}33 ; GFX10-NEXT: [[DEF1:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF34 ; GFX10-NEXT: S_BRANCH %bb.235 ; GFX10-NEXT: {{ $}}36 ; GFX10-NEXT: bb.2:37 ; GFX10-NEXT: successors: %bb.3(0x40000000), %bb.4(0x40000000)38 ; GFX10-NEXT: {{ $}}39 ; GFX10-NEXT: $exec_lo = S_OR_B32 $exec_lo, [[S_XOR_B32_1]], implicit-def $scc40 ; GFX10-NEXT: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[S_MOV_B32_]], [[DEF]], implicit $exec41 ; GFX10-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 3142 ; GFX10-NEXT: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 [[V_BFE_U32_e64_]], killed [[S_MOV_B32_2]], implicit $exec43 ; GFX10-NEXT: [[S_XOR_B32_2:%[0-9]+]]:sreg_32 = S_XOR_B32 [[V_CMP_NE_U32_e64_1]], -1, implicit-def $scc44 ; GFX10-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32 = S_AND_B32 [[S_XOR_B32_2]], $exec_lo, implicit-def $scc45 ; GFX10-NEXT: [[S_XOR_B32_3:%[0-9]+]]:sreg_32 = S_XOR_B32 $exec_lo, [[S_AND_B32_1]], implicit-def $scc46 ; GFX10-NEXT: $exec_lo = S_MOV_B32_term [[S_AND_B32_1]]47 ; GFX10-NEXT: S_CBRANCH_EXECZ %bb.4, implicit $exec48 ; GFX10-NEXT: S_BRANCH %bb.349 ; GFX10-NEXT: {{ $}}50 ; GFX10-NEXT: bb.3:51 ; GFX10-NEXT: successors: %bb.4(0x80000000)52 ; GFX10-NEXT: {{ $}}53 ; GFX10-NEXT: S_BRANCH %bb.454 ; GFX10-NEXT: {{ $}}55 ; GFX10-NEXT: bb.4:56 ; GFX10-NEXT: successors: %bb.5(0x80000000)57 ; GFX10-NEXT: {{ $}}58 ; GFX10-NEXT: $exec_lo = S_OR_B32 $exec_lo, [[S_XOR_B32_3]], implicit-def $scc59 ; GFX10-NEXT: [[DEF2:%[0-9]+]]:sreg_32 = IMPLICIT_DEF60 ; GFX10-NEXT: [[S_MOV_B32_3:%[0-9]+]]:sreg_32 = S_MOV_B32 1661 ; GFX10-NEXT: [[S_MOV_B32_4:%[0-9]+]]:sreg_32 = S_MOV_B32 462 ; GFX10-NEXT: [[V_LSHL_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = nuw nsw V_LSHL_ADD_U32_e64 [[V_LSHRREV_B32_e64_]], [[S_MOV_B32_4]], killed [[S_MOV_B32_3]], implicit $exec63 ; GFX10-NEXT: S_BRANCH %bb.564 ; GFX10-NEXT: {{ $}}65 ; GFX10-NEXT: bb.5:66 ; GFX10-NEXT: $exec_lo = S_OR_B32 $exec_lo, [[DEF2]], implicit-def $scc67 ; GFX10-NEXT: S_ENDPGM 068 bb.0:69 successors: %bb.4(0x40000000), %bb.5(0x40000000)70 71 %0:sgpr_32 = IMPLICIT_DEF72 %14:sreg_32 = IMPLICIT_DEF73 %15:vgpr_32 = IMPLICIT_DEF74 %16:sreg_32 = S_MOV_B32 875 %17:vgpr_32 = V_LSHRREV_B32_e64 %16, %15, implicit $exec76 %18:vgpr_32 = V_BFE_U32_e64 %15, 8, 5, implicit $exec77 %19:sreg_32 = S_MOV_B32 578 %20:sreg_32 = V_CMP_NE_U32_e64 %18, killed %19, implicit $exec79 %21:sreg_32 = S_XOR_B32 %20, -1, implicit-def $scc80 %22:sreg_32 = S_AND_B32 %21, $exec_lo, implicit-def $scc81 %23:sreg_32 = S_XOR_B32 $exec_lo, %22, implicit-def $scc82 $exec_lo = S_MOV_B32_term %2283 S_CBRANCH_EXECZ %bb.5, implicit $exec84 S_BRANCH %bb.485 86 bb.4:87 successors: %bb.5(0x80000000)88 89 S_BRANCH %bb.590 91 bb.5:92 successors: %bb.6(0x40000000), %bb.7(0x40000000)93 94 $exec_lo = S_OR_B32 $exec_lo, %23, implicit-def $scc95 %24:sreg_32 = S_MOV_B32 3196 %25:sreg_32 = V_CMP_NE_U32_e64 %18, killed %24, implicit $exec97 %26:sreg_32 = S_XOR_B32 %25, -1, implicit-def $scc98 %27:sreg_32 = S_AND_B32 %26, $exec_lo, implicit-def $scc99 %28:sreg_32 = S_XOR_B32 $exec_lo, %27, implicit-def $scc100 $exec_lo = S_MOV_B32_term %27101 S_CBRANCH_EXECZ %bb.7, implicit $exec102 S_BRANCH %bb.6103 104 bb.6:105 successors: %bb.7(0x80000000)106 107 S_BRANCH %bb.7108 109 bb.7:110 successors: %bb.8(0x80000000)111 112 $exec_lo = S_OR_B32 $exec_lo, %28, implicit-def $scc113 %29:sreg_32 = S_MOV_B32 16114 %30:sreg_32 = S_MOV_B32 4115 %31:vgpr_32 = nuw nsw V_LSHL_ADD_U32_e64 %17, %30, killed %29, implicit $exec116 S_BRANCH %bb.8117 118 bb.8:119 $exec_lo = S_OR_B32 $exec_lo, %14, implicit-def $scc120 S_ENDPGM 0121 122...123