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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI %s3; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s4; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 < %s | FileCheck -enable-var-scope -check-prefixes=GFX942 %s5 6declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone7 8define amdgpu_kernel void @sint_to_fp_i32_to_f64(ptr addrspace(1) %out, i32 %in) {9; CI-LABEL: sint_to_fp_i32_to_f64:10; CI: ; %bb.0:11; CI-NEXT: s_load_dword s2, s[8:9], 0x212; CI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x013; CI-NEXT: s_add_i32 s12, s12, s1714; CI-NEXT: s_mov_b32 flat_scratch_lo, s1315; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 816; CI-NEXT: s_waitcnt lgkmcnt(0)17; CI-NEXT: v_cvt_f64_i32_e32 v[0:1], s218; CI-NEXT: v_mov_b32_e32 v3, s119; CI-NEXT: v_mov_b32_e32 v2, s020; CI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]21; CI-NEXT: s_endpgm22;23; VI-LABEL: sint_to_fp_i32_to_f64:24; VI: ; %bb.0:25; VI-NEXT: s_load_dword s2, s[8:9], 0x826; VI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x027; VI-NEXT: s_add_i32 s12, s12, s1728; VI-NEXT: s_mov_b32 flat_scratch_lo, s1329; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 830; VI-NEXT: s_waitcnt lgkmcnt(0)31; VI-NEXT: v_cvt_f64_i32_e32 v[0:1], s232; VI-NEXT: v_mov_b32_e32 v3, s133; VI-NEXT: v_mov_b32_e32 v2, s034; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]35; VI-NEXT: s_endpgm36;37; GFX942-LABEL: sint_to_fp_i32_to_f64:38; GFX942: ; %bb.0:39; GFX942-NEXT: s_load_dword s2, s[4:5], 0x840; GFX942-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x041; GFX942-NEXT: v_mov_b32_e32 v2, 042; GFX942-NEXT: s_waitcnt lgkmcnt(0)43; GFX942-NEXT: v_cvt_f64_i32_e32 v[0:1], s244; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]45; GFX942-NEXT: s_endpgm46 %result = sitofp i32 %in to double47 store double %result, ptr addrspace(1) %out48 ret void49}50 51; We can't fold the SGPRs into v_cndmask_b32_e64, because it already52; uses an SGPR (implicit vcc).53define amdgpu_kernel void @sint_to_fp_i1_f64(ptr addrspace(1) %out, i32 %in) {54; CI-LABEL: sint_to_fp_i1_f64:55; CI: ; %bb.0:56; CI-NEXT: s_load_dword s2, s[8:9], 0x257; CI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x058; CI-NEXT: s_add_i32 s12, s12, s1759; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 860; CI-NEXT: s_mov_b32 flat_scratch_lo, s1361; CI-NEXT: s_waitcnt lgkmcnt(0)62; CI-NEXT: s_cmp_eq_u32 s2, 063; CI-NEXT: s_cselect_b32 s2, 0xbff00000, 064; CI-NEXT: v_mov_b32_e32 v3, s165; CI-NEXT: v_mov_b32_e32 v0, 066; CI-NEXT: v_mov_b32_e32 v1, s267; CI-NEXT: v_mov_b32_e32 v2, s068; CI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]69; CI-NEXT: s_endpgm70;71; VI-LABEL: sint_to_fp_i1_f64:72; VI: ; %bb.0:73; VI-NEXT: s_load_dword s2, s[8:9], 0x874; VI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x075; VI-NEXT: s_add_i32 s12, s12, s1776; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 877; VI-NEXT: s_mov_b32 flat_scratch_lo, s1378; VI-NEXT: s_waitcnt lgkmcnt(0)79; VI-NEXT: s_cmp_eq_u32 s2, 080; VI-NEXT: s_cselect_b32 s2, 0xbff00000, 081; VI-NEXT: v_mov_b32_e32 v3, s182; VI-NEXT: v_mov_b32_e32 v0, 083; VI-NEXT: v_mov_b32_e32 v1, s284; VI-NEXT: v_mov_b32_e32 v2, s085; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]86; VI-NEXT: s_endpgm87;88; GFX942-LABEL: sint_to_fp_i1_f64:89; GFX942: ; %bb.0:90; GFX942-NEXT: s_load_dword s2, s[4:5], 0x891; GFX942-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x092; GFX942-NEXT: v_mov_b32_e32 v0, 093; GFX942-NEXT: s_waitcnt lgkmcnt(0)94; GFX942-NEXT: s_cmp_eq_u32 s2, 095; GFX942-NEXT: s_cselect_b32 s2, 0xbff00000, 096; GFX942-NEXT: v_mov_b32_e32 v1, s297; GFX942-NEXT: global_store_dwordx2 v0, v[0:1], s[0:1]98; GFX942-NEXT: s_endpgm99 %cmp = icmp eq i32 %in, 0100 %fp = sitofp i1 %cmp to double101 store double %fp, ptr addrspace(1) %out, align 4102 ret void103}104 105define amdgpu_kernel void @sint_to_fp_i1_f64_load(ptr addrspace(1) %out, i1 %in) {106; CI-LABEL: sint_to_fp_i1_f64_load:107; CI: ; %bb.0:108; CI-NEXT: s_load_dword s2, s[8:9], 0x2109; CI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0110; CI-NEXT: s_add_i32 s12, s12, s17111; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8112; CI-NEXT: s_mov_b32 flat_scratch_lo, s13113; CI-NEXT: s_waitcnt lgkmcnt(0)114; CI-NEXT: s_bitcmp1_b32 s2, 0115; CI-NEXT: s_cselect_b64 s[2:3], -1, 0116; CI-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[2:3]117; CI-NEXT: v_cvt_f64_i32_e32 v[0:1], v0118; CI-NEXT: v_mov_b32_e32 v3, s1119; CI-NEXT: v_mov_b32_e32 v2, s0120; CI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]121; CI-NEXT: s_endpgm122;123; VI-LABEL: sint_to_fp_i1_f64_load:124; VI: ; %bb.0:125; VI-NEXT: s_load_dword s2, s[8:9], 0x8126; VI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0127; VI-NEXT: s_add_i32 s12, s12, s17128; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8129; VI-NEXT: s_mov_b32 flat_scratch_lo, s13130; VI-NEXT: s_waitcnt lgkmcnt(0)131; VI-NEXT: s_bitcmp1_b32 s2, 0132; VI-NEXT: s_cselect_b64 s[2:3], -1, 0133; VI-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[2:3]134; VI-NEXT: v_cvt_f64_i32_e32 v[0:1], v0135; VI-NEXT: v_mov_b32_e32 v3, s1136; VI-NEXT: v_mov_b32_e32 v2, s0137; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]138; VI-NEXT: s_endpgm139;140; GFX942-LABEL: sint_to_fp_i1_f64_load:141; GFX942: ; %bb.0:142; GFX942-NEXT: s_load_dword s2, s[4:5], 0x8143; GFX942-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0144; GFX942-NEXT: v_mov_b32_e32 v2, 0145; GFX942-NEXT: s_waitcnt lgkmcnt(0)146; GFX942-NEXT: s_bitcmp1_b32 s2, 0147; GFX942-NEXT: s_cselect_b64 s[2:3], -1, 0148; GFX942-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[2:3]149; GFX942-NEXT: v_cvt_f64_i32_e32 v[0:1], v0150; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]151; GFX942-NEXT: s_endpgm152 %fp = sitofp i1 %in to double153 store double %fp, ptr addrspace(1) %out, align 8154 ret void155}156 157define amdgpu_kernel void @s_sint_to_fp_i64_to_f64(ptr addrspace(1) %out, i64 %in) {158; CI-LABEL: s_sint_to_fp_i64_to_f64:159; CI: ; %bb.0:160; CI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0161; CI-NEXT: s_add_i32 s12, s12, s17162; CI-NEXT: s_mov_b32 flat_scratch_lo, s13163; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8164; CI-NEXT: s_waitcnt lgkmcnt(0)165; CI-NEXT: v_cvt_f64_i32_e32 v[0:1], s3166; CI-NEXT: v_cvt_f64_u32_e32 v[2:3], s2167; CI-NEXT: v_mov_b32_e32 v4, s0168; CI-NEXT: v_mov_b32_e32 v5, s1169; CI-NEXT: v_ldexp_f64 v[0:1], v[0:1], 32170; CI-NEXT: v_add_f64 v[0:1], v[0:1], v[2:3]171; CI-NEXT: flat_store_dwordx2 v[4:5], v[0:1]172; CI-NEXT: s_endpgm173;174; VI-LABEL: s_sint_to_fp_i64_to_f64:175; VI: ; %bb.0:176; VI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0177; VI-NEXT: s_add_i32 s12, s12, s17178; VI-NEXT: s_mov_b32 flat_scratch_lo, s13179; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8180; VI-NEXT: s_waitcnt lgkmcnt(0)181; VI-NEXT: v_cvt_f64_i32_e32 v[0:1], s3182; VI-NEXT: v_cvt_f64_u32_e32 v[2:3], s2183; VI-NEXT: v_ldexp_f64 v[0:1], v[0:1], 32184; VI-NEXT: v_add_f64 v[0:1], v[0:1], v[2:3]185; VI-NEXT: v_mov_b32_e32 v2, s0186; VI-NEXT: v_mov_b32_e32 v3, s1187; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]188; VI-NEXT: s_endpgm189;190; GFX942-LABEL: s_sint_to_fp_i64_to_f64:191; GFX942: ; %bb.0:192; GFX942-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0193; GFX942-NEXT: v_mov_b32_e32 v4, 0194; GFX942-NEXT: s_waitcnt lgkmcnt(0)195; GFX942-NEXT: v_cvt_f64_i32_e32 v[0:1], s3196; GFX942-NEXT: v_ldexp_f64 v[0:1], v[0:1], 32197; GFX942-NEXT: v_cvt_f64_u32_e32 v[2:3], s2198; GFX942-NEXT: v_add_f64 v[0:1], v[0:1], v[2:3]199; GFX942-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]200; GFX942-NEXT: s_endpgm201 %result = sitofp i64 %in to double202 store double %result, ptr addrspace(1) %out203 ret void204}205 206define amdgpu_kernel void @v_sint_to_fp_i64_to_f64(ptr addrspace(1) %out, ptr addrspace(1) %in) {207; CI-LABEL: v_sint_to_fp_i64_to_f64:208; CI: ; %bb.0:209; CI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0210; CI-NEXT: v_lshlrev_b32_e32 v0, 3, v0211; CI-NEXT: s_add_i32 s12, s12, s17212; CI-NEXT: s_mov_b32 flat_scratch_lo, s13213; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8214; CI-NEXT: s_waitcnt lgkmcnt(0)215; CI-NEXT: v_mov_b32_e32 v1, s3216; CI-NEXT: v_add_i32_e32 v0, vcc, s2, v0217; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc218; CI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]219; CI-NEXT: s_waitcnt vmcnt(0)220; CI-NEXT: v_cvt_f64_i32_e32 v[1:2], v1221; CI-NEXT: v_cvt_f64_u32_e32 v[3:4], v0222; CI-NEXT: v_ldexp_f64 v[0:1], v[1:2], 32223; CI-NEXT: v_mov_b32_e32 v2, s0224; CI-NEXT: v_add_f64 v[0:1], v[0:1], v[3:4]225; CI-NEXT: v_mov_b32_e32 v3, s1226; CI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]227; CI-NEXT: s_endpgm228;229; VI-LABEL: v_sint_to_fp_i64_to_f64:230; VI: ; %bb.0:231; VI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0232; VI-NEXT: v_lshlrev_b32_e32 v0, 3, v0233; VI-NEXT: s_add_i32 s12, s12, s17234; VI-NEXT: s_mov_b32 flat_scratch_lo, s13235; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8236; VI-NEXT: s_waitcnt lgkmcnt(0)237; VI-NEXT: v_mov_b32_e32 v1, s3238; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0239; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc240; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]241; VI-NEXT: s_waitcnt vmcnt(0)242; VI-NEXT: v_cvt_f64_i32_e32 v[1:2], v1243; VI-NEXT: v_cvt_f64_u32_e32 v[3:4], v0244; VI-NEXT: v_ldexp_f64 v[1:2], v[1:2], 32245; VI-NEXT: v_add_f64 v[0:1], v[1:2], v[3:4]246; VI-NEXT: v_mov_b32_e32 v2, s0247; VI-NEXT: v_mov_b32_e32 v3, s1248; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]249; VI-NEXT: s_endpgm250;251; GFX942-LABEL: v_sint_to_fp_i64_to_f64:252; GFX942: ; %bb.0:253; GFX942-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0254; GFX942-NEXT: v_and_b32_e32 v0, 0x3ff, v0255; GFX942-NEXT: v_lshlrev_b32_e32 v0, 3, v0256; GFX942-NEXT: v_mov_b32_e32 v4, 0257; GFX942-NEXT: s_waitcnt lgkmcnt(0)258; GFX942-NEXT: global_load_dwordx2 v[0:1], v0, s[2:3]259; GFX942-NEXT: s_waitcnt vmcnt(0)260; GFX942-NEXT: v_cvt_f64_i32_e32 v[2:3], v1261; GFX942-NEXT: v_ldexp_f64 v[2:3], v[2:3], 32262; GFX942-NEXT: v_cvt_f64_u32_e32 v[0:1], v0263; GFX942-NEXT: v_add_f64 v[0:1], v[2:3], v[0:1]264; GFX942-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]265; GFX942-NEXT: s_endpgm266 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone267 %gep = getelementptr i64, ptr addrspace(1) %in, i32 %tid268 %val = load i64, ptr addrspace(1) %gep, align 8269 %result = sitofp i64 %val to double270 store double %result, ptr addrspace(1) %out271 ret void272}273 274; FIXME: bfe and sext on VI+275define amdgpu_kernel void @s_sint_to_fp_i8_to_f64(ptr addrspace(1) %out, i8 %in) {276; CI-LABEL: s_sint_to_fp_i8_to_f64:277; CI: ; %bb.0:278; CI-NEXT: s_load_dword s2, s[8:9], 0x2279; CI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0280; CI-NEXT: s_add_i32 s12, s12, s17281; CI-NEXT: s_mov_b32 flat_scratch_lo, s13282; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8283; CI-NEXT: s_waitcnt lgkmcnt(0)284; CI-NEXT: s_sext_i32_i8 s2, s2285; CI-NEXT: v_cvt_f64_i32_e32 v[0:1], s2286; CI-NEXT: v_mov_b32_e32 v3, s1287; CI-NEXT: v_mov_b32_e32 v2, s0288; CI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]289; CI-NEXT: s_endpgm290;291; VI-LABEL: s_sint_to_fp_i8_to_f64:292; VI: ; %bb.0:293; VI-NEXT: s_load_dword s2, s[8:9], 0x8294; VI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0295; VI-NEXT: s_add_i32 s12, s12, s17296; VI-NEXT: s_mov_b32 flat_scratch_lo, s13297; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8298; VI-NEXT: s_waitcnt lgkmcnt(0)299; VI-NEXT: s_sext_i32_i8 s2, s2300; VI-NEXT: v_cvt_f64_i32_e32 v[0:1], s2301; VI-NEXT: v_mov_b32_e32 v3, s1302; VI-NEXT: v_mov_b32_e32 v2, s0303; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]304; VI-NEXT: s_endpgm305;306; GFX942-LABEL: s_sint_to_fp_i8_to_f64:307; GFX942: ; %bb.0:308; GFX942-NEXT: s_load_dword s2, s[4:5], 0x8309; GFX942-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0310; GFX942-NEXT: v_mov_b32_e32 v2, 0311; GFX942-NEXT: s_waitcnt lgkmcnt(0)312; GFX942-NEXT: s_sext_i32_i8 s2, s2313; GFX942-NEXT: v_cvt_f64_i32_e32 v[0:1], s2314; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]315; GFX942-NEXT: s_endpgm316 %fp = sitofp i8 %in to double317 store double %fp, ptr addrspace(1) %out318 ret void319}320 321define double @v_sint_to_fp_i8_to_f64(i8 %in) {322; CI-LABEL: v_sint_to_fp_i8_to_f64:323; CI: ; %bb.0:324; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)325; CI-NEXT: v_bfe_i32 v0, v0, 0, 8326; CI-NEXT: v_cvt_f64_i32_e32 v[0:1], v0327; CI-NEXT: s_setpc_b64 s[30:31]328;329; VI-LABEL: v_sint_to_fp_i8_to_f64:330; VI: ; %bb.0:331; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)332; VI-NEXT: v_bfe_i32 v0, v0, 0, 8333; VI-NEXT: v_bfe_i32 v0, v0, 0, 16334; VI-NEXT: v_cvt_f64_i32_e32 v[0:1], v0335; VI-NEXT: s_setpc_b64 s[30:31]336;337; GFX942-LABEL: v_sint_to_fp_i8_to_f64:338; GFX942: ; %bb.0:339; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)340; GFX942-NEXT: v_bfe_i32 v0, v0, 0, 8341; GFX942-NEXT: v_bfe_i32 v0, v0, 0, 16342; GFX942-NEXT: v_cvt_f64_i32_e32 v[0:1], v0343; GFX942-NEXT: s_setpc_b64 s[30:31]344 %fp = sitofp i8 %in to double345 ret double %fp346 }347 348define amdgpu_kernel void @s_select_sint_to_fp_i1_vals_f64(ptr addrspace(1) %out, i32 %in) {349; CI-LABEL: s_select_sint_to_fp_i1_vals_f64:350; CI: ; %bb.0:351; CI-NEXT: s_load_dword s2, s[8:9], 0x2352; CI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0353; CI-NEXT: s_add_i32 s12, s12, s17354; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8355; CI-NEXT: s_mov_b32 flat_scratch_lo, s13356; CI-NEXT: s_waitcnt lgkmcnt(0)357; CI-NEXT: s_cmp_eq_u32 s2, 0358; CI-NEXT: s_cselect_b32 s2, 0xbff00000, 0359; CI-NEXT: v_mov_b32_e32 v3, s1360; CI-NEXT: v_mov_b32_e32 v0, 0361; CI-NEXT: v_mov_b32_e32 v1, s2362; CI-NEXT: v_mov_b32_e32 v2, s0363; CI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]364; CI-NEXT: s_endpgm365;366; VI-LABEL: s_select_sint_to_fp_i1_vals_f64:367; VI: ; %bb.0:368; VI-NEXT: s_load_dword s2, s[8:9], 0x8369; VI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0370; VI-NEXT: s_add_i32 s12, s12, s17371; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8372; VI-NEXT: s_mov_b32 flat_scratch_lo, s13373; VI-NEXT: s_waitcnt lgkmcnt(0)374; VI-NEXT: s_cmp_eq_u32 s2, 0375; VI-NEXT: s_cselect_b32 s2, 0xbff00000, 0376; VI-NEXT: v_mov_b32_e32 v3, s1377; VI-NEXT: v_mov_b32_e32 v0, 0378; VI-NEXT: v_mov_b32_e32 v1, s2379; VI-NEXT: v_mov_b32_e32 v2, s0380; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]381; VI-NEXT: s_endpgm382;383; GFX942-LABEL: s_select_sint_to_fp_i1_vals_f64:384; GFX942: ; %bb.0:385; GFX942-NEXT: s_load_dword s2, s[4:5], 0x8386; GFX942-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0387; GFX942-NEXT: v_mov_b32_e32 v0, 0388; GFX942-NEXT: s_waitcnt lgkmcnt(0)389; GFX942-NEXT: s_cmp_eq_u32 s2, 0390; GFX942-NEXT: s_cselect_b32 s2, 0xbff00000, 0391; GFX942-NEXT: v_mov_b32_e32 v1, s2392; GFX942-NEXT: global_store_dwordx2 v0, v[0:1], s[0:1]393; GFX942-NEXT: s_endpgm394 %cmp = icmp eq i32 %in, 0395 %select = select i1 %cmp, double -1.0, double 0.0396 store double %select, ptr addrspace(1) %out, align 8397 ret void398}399 400define void @v_select_sint_to_fp_i1_vals_f64(ptr addrspace(1) %out, i32 %in) {401; GCN-LABEL: v_select_sint_to_fp_i1_vals_f64:402; GCN: ; %bb.0:403; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)404; GCN-NEXT: v_mov_b32_e32 v4, 0xbff00000405; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2406; GCN-NEXT: v_mov_b32_e32 v3, 0407; GCN-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc408; GCN-NEXT: flat_store_dwordx2 v[0:1], v[3:4]409; GCN-NEXT: s_waitcnt vmcnt(0)410; GCN-NEXT: s_setpc_b64 s[30:31]411;412; GFX942-LABEL: v_select_sint_to_fp_i1_vals_f64:413; GFX942: ; %bb.0:414; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)415; GFX942-NEXT: v_mov_b32_e32 v3, 0xbff00000416; GFX942-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2417; GFX942-NEXT: v_mov_b32_e32 v4, 0418; GFX942-NEXT: s_nop 0419; GFX942-NEXT: v_cndmask_b32_e32 v5, 0, v3, vcc420; GFX942-NEXT: global_store_dwordx2 v[0:1], v[4:5], off421; GFX942-NEXT: s_waitcnt vmcnt(0)422; GFX942-NEXT: s_setpc_b64 s[30:31]423 %cmp = icmp eq i32 %in, 0424 %select = select i1 %cmp, double -1.0, double 0.0425 store double %select, ptr addrspace(1) %out, align 8426 ret void427}428 429define amdgpu_kernel void @s_select_sint_to_fp_i1_vals_i64(ptr addrspace(1) %out, i32 %in) {430; CI-LABEL: s_select_sint_to_fp_i1_vals_i64:431; CI: ; %bb.0:432; CI-NEXT: s_load_dword s2, s[8:9], 0x2433; CI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0434; CI-NEXT: s_add_i32 s12, s12, s17435; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8436; CI-NEXT: s_mov_b32 flat_scratch_lo, s13437; CI-NEXT: s_waitcnt lgkmcnt(0)438; CI-NEXT: s_cmp_eq_u32 s2, 0439; CI-NEXT: s_cselect_b32 s2, 0xbff00000, 0440; CI-NEXT: v_mov_b32_e32 v3, s1441; CI-NEXT: v_mov_b32_e32 v0, 0442; CI-NEXT: v_mov_b32_e32 v1, s2443; CI-NEXT: v_mov_b32_e32 v2, s0444; CI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]445; CI-NEXT: s_endpgm446;447; VI-LABEL: s_select_sint_to_fp_i1_vals_i64:448; VI: ; %bb.0:449; VI-NEXT: s_load_dword s2, s[8:9], 0x8450; VI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0451; VI-NEXT: s_add_i32 s12, s12, s17452; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8453; VI-NEXT: s_mov_b32 flat_scratch_lo, s13454; VI-NEXT: s_waitcnt lgkmcnt(0)455; VI-NEXT: s_cmp_eq_u32 s2, 0456; VI-NEXT: s_cselect_b32 s2, 0xbff00000, 0457; VI-NEXT: v_mov_b32_e32 v3, s1458; VI-NEXT: v_mov_b32_e32 v0, 0459; VI-NEXT: v_mov_b32_e32 v1, s2460; VI-NEXT: v_mov_b32_e32 v2, s0461; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]462; VI-NEXT: s_endpgm463;464; GFX942-LABEL: s_select_sint_to_fp_i1_vals_i64:465; GFX942: ; %bb.0:466; GFX942-NEXT: s_load_dword s2, s[4:5], 0x8467; GFX942-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0468; GFX942-NEXT: v_mov_b32_e32 v0, 0469; GFX942-NEXT: s_waitcnt lgkmcnt(0)470; GFX942-NEXT: s_cmp_eq_u32 s2, 0471; GFX942-NEXT: s_cselect_b32 s2, 0xbff00000, 0472; GFX942-NEXT: v_mov_b32_e32 v1, s2473; GFX942-NEXT: global_store_dwordx2 v0, v[0:1], s[0:1]474; GFX942-NEXT: s_endpgm475 %cmp = icmp eq i32 %in, 0476 %select = select i1 %cmp, i64 u0xbff0000000000000, i64 0477 store i64 %select, ptr addrspace(1) %out, align 8478 ret void479}480 481define void @v_select_sint_to_fp_i1_vals_i64(ptr addrspace(1) %out, i32 %in) {482; GCN-LABEL: v_select_sint_to_fp_i1_vals_i64:483; GCN: ; %bb.0:484; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)485; GCN-NEXT: v_mov_b32_e32 v4, 0xbff00000486; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2487; GCN-NEXT: v_mov_b32_e32 v3, 0488; GCN-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc489; GCN-NEXT: flat_store_dwordx2 v[0:1], v[3:4]490; GCN-NEXT: s_waitcnt vmcnt(0)491; GCN-NEXT: s_setpc_b64 s[30:31]492;493; GFX942-LABEL: v_select_sint_to_fp_i1_vals_i64:494; GFX942: ; %bb.0:495; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)496; GFX942-NEXT: v_mov_b32_e32 v3, 0xbff00000497; GFX942-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2498; GFX942-NEXT: v_mov_b32_e32 v4, 0499; GFX942-NEXT: s_nop 0500; GFX942-NEXT: v_cndmask_b32_e32 v5, 0, v3, vcc501; GFX942-NEXT: global_store_dwordx2 v[0:1], v[4:5], off502; GFX942-NEXT: s_waitcnt vmcnt(0)503; GFX942-NEXT: s_setpc_b64 s[30:31]504 %cmp = icmp eq i32 %in, 0505 %select = select i1 %cmp, i64 u0xbff0000000000000, i64 0506 store i64 %select, ptr addrspace(1) %out, align 8507 ret void508}509 510; TODO: This should swap the selected order / invert the compare and do it.511define void @v_swap_select_sint_to_fp_i1_vals_f64(ptr addrspace(1) %out, i32 %in) {512; GCN-LABEL: v_swap_select_sint_to_fp_i1_vals_f64:513; GCN: ; %bb.0:514; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)515; GCN-NEXT: v_mov_b32_e32 v4, 0xbff00000516; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2517; GCN-NEXT: v_mov_b32_e32 v3, 0518; GCN-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc519; GCN-NEXT: flat_store_dwordx2 v[0:1], v[3:4]520; GCN-NEXT: s_waitcnt vmcnt(0)521; GCN-NEXT: s_setpc_b64 s[30:31]522;523; GFX942-LABEL: v_swap_select_sint_to_fp_i1_vals_f64:524; GFX942: ; %bb.0:525; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)526; GFX942-NEXT: v_mov_b32_e32 v3, 0xbff00000527; GFX942-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2528; GFX942-NEXT: v_mov_b32_e32 v4, 0529; GFX942-NEXT: s_nop 0530; GFX942-NEXT: v_cndmask_b32_e64 v5, v3, 0, vcc531; GFX942-NEXT: global_store_dwordx2 v[0:1], v[4:5], off532; GFX942-NEXT: s_waitcnt vmcnt(0)533; GFX942-NEXT: s_setpc_b64 s[30:31]534 %cmp = icmp eq i32 %in, 0535 %select = select i1 %cmp, double 0.0, double -1.0536 store double %select, ptr addrspace(1) %out, align 8537 ret void538}539 540; TODO: This should swap the selected order / invert the compare and do it.541define amdgpu_kernel void @s_swap_select_sint_to_fp_i1_vals_f64(ptr addrspace(1) %out, i32 %in) {542; CI-LABEL: s_swap_select_sint_to_fp_i1_vals_f64:543; CI: ; %bb.0:544; CI-NEXT: s_load_dword s2, s[8:9], 0x2545; CI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0546; CI-NEXT: s_add_i32 s12, s12, s17547; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8548; CI-NEXT: s_mov_b32 flat_scratch_lo, s13549; CI-NEXT: s_waitcnt lgkmcnt(0)550; CI-NEXT: s_cmp_eq_u32 s2, 0551; CI-NEXT: s_cselect_b32 s2, 0, 0xbff00000552; CI-NEXT: v_mov_b32_e32 v3, s1553; CI-NEXT: v_mov_b32_e32 v0, 0554; CI-NEXT: v_mov_b32_e32 v1, s2555; CI-NEXT: v_mov_b32_e32 v2, s0556; CI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]557; CI-NEXT: s_endpgm558;559; VI-LABEL: s_swap_select_sint_to_fp_i1_vals_f64:560; VI: ; %bb.0:561; VI-NEXT: s_load_dword s2, s[8:9], 0x8562; VI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0563; VI-NEXT: s_add_i32 s12, s12, s17564; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8565; VI-NEXT: s_mov_b32 flat_scratch_lo, s13566; VI-NEXT: s_waitcnt lgkmcnt(0)567; VI-NEXT: s_cmp_eq_u32 s2, 0568; VI-NEXT: s_cselect_b32 s2, 0, 0xbff00000569; VI-NEXT: v_mov_b32_e32 v3, s1570; VI-NEXT: v_mov_b32_e32 v0, 0571; VI-NEXT: v_mov_b32_e32 v1, s2572; VI-NEXT: v_mov_b32_e32 v2, s0573; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]574; VI-NEXT: s_endpgm575;576; GFX942-LABEL: s_swap_select_sint_to_fp_i1_vals_f64:577; GFX942: ; %bb.0:578; GFX942-NEXT: s_load_dword s2, s[4:5], 0x8579; GFX942-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0580; GFX942-NEXT: v_mov_b32_e32 v0, 0581; GFX942-NEXT: s_waitcnt lgkmcnt(0)582; GFX942-NEXT: s_cmp_eq_u32 s2, 0583; GFX942-NEXT: s_cselect_b32 s2, 0, 0xbff00000584; GFX942-NEXT: v_mov_b32_e32 v1, s2585; GFX942-NEXT: global_store_dwordx2 v0, v[0:1], s[0:1]586; GFX942-NEXT: s_endpgm587 %cmp = icmp eq i32 %in, 0588 %select = select i1 %cmp, double 0.0, double -1.0589 store double %select, ptr addrspace(1) %out, align 8590 ret void591}592