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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -verify-machineinstrs -run-pass si-fold-operands -o - %s | FileCheck -check-prefix=GCN %s3# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -verify-machineinstrs -passes si-fold-operands -o - %s | FileCheck -check-prefix=GCN %s4 5# Skip folding a REG_SEQUENCE to its user when the regclasses for the user operands can't be6# fully determined from the instruction description.7---8name: regsequence_with_regsequence_use_op9tracksRegLiveness: true10body: |11 bb.0:12 liveins: $agpr0, $agpr113 14 ; GCN-LABEL: name: regsequence_with_regsequence_use_op15 ; GCN: liveins: $agpr0, $agpr116 ; GCN-NEXT: {{ $}}17 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $agpr018 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $agpr119 ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub120 ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF21 ; GCN-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_96_align2 = REG_SEQUENCE killed [[REG_SEQUENCE]], %subreg.sub0_sub1, killed [[DEF]], %subreg.sub222 ; GCN-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE1]]23 %0:vgpr_32 = COPY $agpr024 %1:vgpr_32 = COPY $agpr125 %2:vreg_64_align2 = REG_SEQUENCE %0:vgpr_32, %subreg.sub0, %1:vgpr_32, %subreg.sub126 %3:vgpr_32 = IMPLICIT_DEF27 %4:vreg_96_align2 = REG_SEQUENCE killed %2:vreg_64_align2, %subreg.sub0_sub1, killed %3:vgpr_32, %subreg.sub228 S_ENDPGM 0, implicit %429...30---31name: insert_subreg_with_regsequence_use_op32tracksRegLiveness: true33body: |34 bb.0:35 liveins: $agpr0, $agpr136 37 ; GCN-LABEL: name: insert_subreg_with_regsequence_use_op38 ; GCN: liveins: $agpr0, $agpr139 ; GCN-NEXT: {{ $}}40 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $agpr041 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $agpr142 ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub143 ; GCN-NEXT: S_NOP 0, implicit-def %344 ; GCN-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vreg_64_align2 = INSERT_SUBREG %3, [[REG_SEQUENCE]], %subreg.sub0_sub145 ; GCN-NEXT: S_ENDPGM 0, implicit [[INSERT_SUBREG]]46 %0:vgpr_32 = COPY $agpr047 %1:vgpr_32 = COPY $agpr148 %2:vreg_64_align2 = REG_SEQUENCE %0:vgpr_32, %subreg.sub0, %1:vgpr_32, %subreg.sub149 S_NOP 0, implicit-def %3:vreg_64_align250 %4:vreg_64_align2 = INSERT_SUBREG %3, %2, %subreg.sub0_sub151 S_ENDPGM 0, implicit %452...53