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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn -mcpu=tahiti -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefixes=GCN,WAVE64,SI %s3; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize64 -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefixes=GCN,WAVE64,GFX10-WAVE64 %s4; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefixes=GCN,GFX10-WAVE32 %s5; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefixes=GCN,GFX11 %s6 7define amdgpu_ps void @test_kill_depth_0_imm_pos() #0 {8; GCN-LABEL: test_kill_depth_0_imm_pos:9; GCN: ; %bb.0:10; GCN-NEXT: s_endpgm11 call void @llvm.amdgcn.kill(i1 true)12 ret void13}14 15define amdgpu_ps void @test_kill_depth_0_imm_neg() #0 {16; WAVE64-LABEL: test_kill_depth_0_imm_neg:17; WAVE64: ; %bb.0:18; WAVE64-NEXT: s_andn2_b64 exec, exec, exec19; WAVE64-NEXT: s_cbranch_scc0 .LBB1_120; WAVE64-NEXT: s_endpgm21; WAVE64-NEXT: .LBB1_1:22; WAVE64-NEXT: s_mov_b64 exec, 023; WAVE64-NEXT: exp null off, off, off, off done vm24; WAVE64-NEXT: s_endpgm25;26; GFX10-WAVE32-LABEL: test_kill_depth_0_imm_neg:27; GFX10-WAVE32: ; %bb.0:28; GFX10-WAVE32-NEXT: s_andn2_b32 exec_lo, exec_lo, exec_lo29; GFX10-WAVE32-NEXT: s_cbranch_scc0 .LBB1_130; GFX10-WAVE32-NEXT: s_endpgm31; GFX10-WAVE32-NEXT: .LBB1_1:32; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 033; GFX10-WAVE32-NEXT: exp null off, off, off, off done vm34; GFX10-WAVE32-NEXT: s_endpgm35;36; GFX11-LABEL: test_kill_depth_0_imm_neg:37; GFX11: ; %bb.0:38; GFX11-NEXT: s_and_not1_b64 exec, exec, exec39; GFX11-NEXT: s_cbranch_scc0 .LBB1_140; GFX11-NEXT: s_endpgm41; GFX11-NEXT: .LBB1_1:42; GFX11-NEXT: s_mov_b64 exec, 043; GFX11-NEXT: exp mrt0 off, off, off, off done44; GFX11-NEXT: s_endpgm45 call void @llvm.amdgcn.kill(i1 false)46 ret void47}48 49; FIXME: Ideally only one early-exit would be emitted50define amdgpu_ps void @test_kill_depth_0_imm_neg_x2() #0 {51; WAVE64-LABEL: test_kill_depth_0_imm_neg_x2:52; WAVE64: ; %bb.0:53; WAVE64-NEXT: s_mov_b64 s[0:1], exec54; WAVE64-NEXT: s_andn2_b64 s[0:1], s[0:1], exec55; WAVE64-NEXT: s_cbranch_scc0 .LBB2_256; WAVE64-NEXT: ; %bb.1:57; WAVE64-NEXT: s_mov_b64 exec, 058; WAVE64-NEXT: s_andn2_b64 s[0:1], s[0:1], exec59; WAVE64-NEXT: s_cbranch_scc0 .LBB2_260; WAVE64-NEXT: s_endpgm61; WAVE64-NEXT: .LBB2_2:62; WAVE64-NEXT: s_mov_b64 exec, 063; WAVE64-NEXT: exp null off, off, off, off done vm64; WAVE64-NEXT: s_endpgm65;66; GFX10-WAVE32-LABEL: test_kill_depth_0_imm_neg_x2:67; GFX10-WAVE32: ; %bb.0:68; GFX10-WAVE32-NEXT: s_mov_b32 s0, exec_lo69; GFX10-WAVE32-NEXT: s_andn2_b32 s0, s0, exec_lo70; GFX10-WAVE32-NEXT: s_cbranch_scc0 .LBB2_271; GFX10-WAVE32-NEXT: ; %bb.1:72; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 073; GFX10-WAVE32-NEXT: s_andn2_b32 s0, s0, exec_lo74; GFX10-WAVE32-NEXT: s_cbranch_scc0 .LBB2_275; GFX10-WAVE32-NEXT: s_endpgm76; GFX10-WAVE32-NEXT: .LBB2_2:77; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 078; GFX10-WAVE32-NEXT: exp null off, off, off, off done vm79; GFX10-WAVE32-NEXT: s_endpgm80;81; GFX11-LABEL: test_kill_depth_0_imm_neg_x2:82; GFX11: ; %bb.0:83; GFX11-NEXT: s_mov_b64 s[0:1], exec84; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)85; GFX11-NEXT: s_and_not1_b64 s[0:1], s[0:1], exec86; GFX11-NEXT: s_cbranch_scc0 .LBB2_287; GFX11-NEXT: ; %bb.1:88; GFX11-NEXT: s_mov_b64 exec, 089; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)90; GFX11-NEXT: s_and_not1_b64 s[0:1], s[0:1], exec91; GFX11-NEXT: s_cbranch_scc0 .LBB2_292; GFX11-NEXT: s_endpgm93; GFX11-NEXT: .LBB2_2:94; GFX11-NEXT: s_mov_b64 exec, 095; GFX11-NEXT: exp mrt0 off, off, off, off done96; GFX11-NEXT: s_endpgm97 call void @llvm.amdgcn.kill(i1 false)98 call void @llvm.amdgcn.kill(i1 false)99 ret void100}101 102define amdgpu_ps void @test_kill_depth_var(float %x) #0 {103; WAVE64-LABEL: test_kill_depth_var:104; WAVE64: ; %bb.0:105; WAVE64-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v0106; WAVE64-NEXT: s_andn2_b64 exec, exec, vcc107; WAVE64-NEXT: s_cbranch_scc0 .LBB3_1108; WAVE64-NEXT: s_endpgm109; WAVE64-NEXT: .LBB3_1:110; WAVE64-NEXT: s_mov_b64 exec, 0111; WAVE64-NEXT: exp null off, off, off, off done vm112; WAVE64-NEXT: s_endpgm113;114; GFX10-WAVE32-LABEL: test_kill_depth_var:115; GFX10-WAVE32: ; %bb.0:116; GFX10-WAVE32-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0, v0117; GFX10-WAVE32-NEXT: s_andn2_b32 exec_lo, exec_lo, vcc_lo118; GFX10-WAVE32-NEXT: s_cbranch_scc0 .LBB3_1119; GFX10-WAVE32-NEXT: s_endpgm120; GFX10-WAVE32-NEXT: .LBB3_1:121; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 0122; GFX10-WAVE32-NEXT: exp null off, off, off, off done vm123; GFX10-WAVE32-NEXT: s_endpgm124;125; GFX11-LABEL: test_kill_depth_var:126; GFX11: ; %bb.0:127; GFX11-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v0128; GFX11-NEXT: s_and_not1_b64 exec, exec, vcc129; GFX11-NEXT: s_cbranch_scc0 .LBB3_1130; GFX11-NEXT: s_endpgm131; GFX11-NEXT: .LBB3_1:132; GFX11-NEXT: s_mov_b64 exec, 0133; GFX11-NEXT: exp mrt0 off, off, off, off done134; GFX11-NEXT: s_endpgm135 %cmp = fcmp olt float %x, 0.0136 call void @llvm.amdgcn.kill(i1 %cmp)137 ret void138}139 140; FIXME: Ideally only one early-exit would be emitted141define amdgpu_ps void @test_kill_depth_var_x2_same(float %x) #0 {142; SI-LABEL: test_kill_depth_var_x2_same:143; SI: ; %bb.0:144; SI-NEXT: s_mov_b64 s[0:1], exec145; SI-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v0146; SI-NEXT: s_andn2_b64 s[0:1], s[0:1], vcc147; SI-NEXT: s_cbranch_scc0 .LBB4_2148; SI-NEXT: ; %bb.1:149; SI-NEXT: s_andn2_b64 exec, exec, vcc150; SI-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v0151; SI-NEXT: s_andn2_b64 s[0:1], s[0:1], vcc152; SI-NEXT: s_cbranch_scc0 .LBB4_2153; SI-NEXT: s_endpgm154; SI-NEXT: .LBB4_2:155; SI-NEXT: s_mov_b64 exec, 0156; SI-NEXT: exp null off, off, off, off done vm157; SI-NEXT: s_endpgm158;159; GFX10-WAVE64-LABEL: test_kill_depth_var_x2_same:160; GFX10-WAVE64: ; %bb.0:161; GFX10-WAVE64-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v0162; GFX10-WAVE64-NEXT: s_mov_b64 s[0:1], exec163; GFX10-WAVE64-NEXT: s_andn2_b64 s[0:1], s[0:1], vcc164; GFX10-WAVE64-NEXT: s_cbranch_scc0 .LBB4_2165; GFX10-WAVE64-NEXT: ; %bb.1:166; GFX10-WAVE64-NEXT: s_andn2_b64 exec, exec, vcc167; GFX10-WAVE64-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v0168; GFX10-WAVE64-NEXT: s_andn2_b64 s[0:1], s[0:1], vcc169; GFX10-WAVE64-NEXT: s_cbranch_scc0 .LBB4_2170; GFX10-WAVE64-NEXT: s_endpgm171; GFX10-WAVE64-NEXT: .LBB4_2:172; GFX10-WAVE64-NEXT: s_mov_b64 exec, 0173; GFX10-WAVE64-NEXT: exp null off, off, off, off done vm174; GFX10-WAVE64-NEXT: s_endpgm175;176; GFX10-WAVE32-LABEL: test_kill_depth_var_x2_same:177; GFX10-WAVE32: ; %bb.0:178; GFX10-WAVE32-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0, v0179; GFX10-WAVE32-NEXT: s_mov_b32 s0, exec_lo180; GFX10-WAVE32-NEXT: s_andn2_b32 s0, s0, vcc_lo181; GFX10-WAVE32-NEXT: s_cbranch_scc0 .LBB4_2182; GFX10-WAVE32-NEXT: ; %bb.1:183; GFX10-WAVE32-NEXT: s_andn2_b32 exec_lo, exec_lo, vcc_lo184; GFX10-WAVE32-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0, v0185; GFX10-WAVE32-NEXT: s_andn2_b32 s0, s0, vcc_lo186; GFX10-WAVE32-NEXT: s_cbranch_scc0 .LBB4_2187; GFX10-WAVE32-NEXT: s_endpgm188; GFX10-WAVE32-NEXT: .LBB4_2:189; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 0190; GFX10-WAVE32-NEXT: exp null off, off, off, off done vm191; GFX10-WAVE32-NEXT: s_endpgm192;193; GFX11-LABEL: test_kill_depth_var_x2_same:194; GFX11: ; %bb.0:195; GFX11-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v0196; GFX11-NEXT: s_mov_b64 s[0:1], exec197; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)198; GFX11-NEXT: s_and_not1_b64 s[0:1], s[0:1], vcc199; GFX11-NEXT: s_cbranch_scc0 .LBB4_2200; GFX11-NEXT: ; %bb.1:201; GFX11-NEXT: s_and_not1_b64 exec, exec, vcc202; GFX11-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v0203; GFX11-NEXT: s_and_not1_b64 s[0:1], s[0:1], vcc204; GFX11-NEXT: s_cbranch_scc0 .LBB4_2205; GFX11-NEXT: s_endpgm206; GFX11-NEXT: .LBB4_2:207; GFX11-NEXT: s_mov_b64 exec, 0208; GFX11-NEXT: exp mrt0 off, off, off, off done209; GFX11-NEXT: s_endpgm210 %cmp = fcmp olt float %x, 0.0211 call void @llvm.amdgcn.kill(i1 %cmp)212 call void @llvm.amdgcn.kill(i1 %cmp)213 ret void214}215 216; FIXME: Ideally only one early-exit would be emitted217define amdgpu_ps void @test_kill_depth_var_x2(float %x, float %y) #0 {218; SI-LABEL: test_kill_depth_var_x2:219; SI: ; %bb.0:220; SI-NEXT: s_mov_b64 s[0:1], exec221; SI-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v0222; SI-NEXT: s_andn2_b64 s[0:1], s[0:1], vcc223; SI-NEXT: s_cbranch_scc0 .LBB5_2224; SI-NEXT: ; %bb.1:225; SI-NEXT: s_andn2_b64 exec, exec, vcc226; SI-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v1227; SI-NEXT: s_andn2_b64 s[0:1], s[0:1], vcc228; SI-NEXT: s_cbranch_scc0 .LBB5_2229; SI-NEXT: s_endpgm230; SI-NEXT: .LBB5_2:231; SI-NEXT: s_mov_b64 exec, 0232; SI-NEXT: exp null off, off, off, off done vm233; SI-NEXT: s_endpgm234;235; GFX10-WAVE64-LABEL: test_kill_depth_var_x2:236; GFX10-WAVE64: ; %bb.0:237; GFX10-WAVE64-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v0238; GFX10-WAVE64-NEXT: s_mov_b64 s[0:1], exec239; GFX10-WAVE64-NEXT: s_andn2_b64 s[0:1], s[0:1], vcc240; GFX10-WAVE64-NEXT: s_cbranch_scc0 .LBB5_2241; GFX10-WAVE64-NEXT: ; %bb.1:242; GFX10-WAVE64-NEXT: s_andn2_b64 exec, exec, vcc243; GFX10-WAVE64-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v1244; GFX10-WAVE64-NEXT: s_andn2_b64 s[0:1], s[0:1], vcc245; GFX10-WAVE64-NEXT: s_cbranch_scc0 .LBB5_2246; GFX10-WAVE64-NEXT: s_endpgm247; GFX10-WAVE64-NEXT: .LBB5_2:248; GFX10-WAVE64-NEXT: s_mov_b64 exec, 0249; GFX10-WAVE64-NEXT: exp null off, off, off, off done vm250; GFX10-WAVE64-NEXT: s_endpgm251;252; GFX10-WAVE32-LABEL: test_kill_depth_var_x2:253; GFX10-WAVE32: ; %bb.0:254; GFX10-WAVE32-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0, v0255; GFX10-WAVE32-NEXT: s_mov_b32 s0, exec_lo256; GFX10-WAVE32-NEXT: s_andn2_b32 s0, s0, vcc_lo257; GFX10-WAVE32-NEXT: s_cbranch_scc0 .LBB5_2258; GFX10-WAVE32-NEXT: ; %bb.1:259; GFX10-WAVE32-NEXT: s_andn2_b32 exec_lo, exec_lo, vcc_lo260; GFX10-WAVE32-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0, v1261; GFX10-WAVE32-NEXT: s_andn2_b32 s0, s0, vcc_lo262; GFX10-WAVE32-NEXT: s_cbranch_scc0 .LBB5_2263; GFX10-WAVE32-NEXT: s_endpgm264; GFX10-WAVE32-NEXT: .LBB5_2:265; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 0266; GFX10-WAVE32-NEXT: exp null off, off, off, off done vm267; GFX10-WAVE32-NEXT: s_endpgm268;269; GFX11-LABEL: test_kill_depth_var_x2:270; GFX11: ; %bb.0:271; GFX11-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v0272; GFX11-NEXT: s_mov_b64 s[0:1], exec273; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)274; GFX11-NEXT: s_and_not1_b64 s[0:1], s[0:1], vcc275; GFX11-NEXT: s_cbranch_scc0 .LBB5_2276; GFX11-NEXT: ; %bb.1:277; GFX11-NEXT: s_and_not1_b64 exec, exec, vcc278; GFX11-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v1279; GFX11-NEXT: s_and_not1_b64 s[0:1], s[0:1], vcc280; GFX11-NEXT: s_cbranch_scc0 .LBB5_2281; GFX11-NEXT: s_endpgm282; GFX11-NEXT: .LBB5_2:283; GFX11-NEXT: s_mov_b64 exec, 0284; GFX11-NEXT: exp mrt0 off, off, off, off done285; GFX11-NEXT: s_endpgm286 %cmp.x = fcmp olt float %x, 0.0287 call void @llvm.amdgcn.kill(i1 %cmp.x)288 %cmp.y = fcmp olt float %y, 0.0289 call void @llvm.amdgcn.kill(i1 %cmp.y)290 ret void291}292 293define amdgpu_ps void @test_kill_depth_var_x2_instructions(float %x) #0 {294; SI-LABEL: test_kill_depth_var_x2_instructions:295; SI: ; %bb.0:296; SI-NEXT: s_mov_b64 s[0:1], exec297; SI-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v0298; SI-NEXT: s_andn2_b64 s[0:1], s[0:1], vcc299; SI-NEXT: s_cbranch_scc0 .LBB6_2300; SI-NEXT: ; %bb.1:301; SI-NEXT: s_andn2_b64 exec, exec, vcc302; SI-NEXT: ;;#ASMSTART303; SI-NEXT: v_mov_b32_e64 v7, -1304; SI-NEXT: ;;#ASMEND305; SI-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v7306; SI-NEXT: s_andn2_b64 s[0:1], s[0:1], vcc307; SI-NEXT: s_cbranch_scc0 .LBB6_2308; SI-NEXT: s_endpgm309; SI-NEXT: .LBB6_2:310; SI-NEXT: s_mov_b64 exec, 0311; SI-NEXT: exp null off, off, off, off done vm312; SI-NEXT: s_endpgm313;314; GFX10-WAVE64-LABEL: test_kill_depth_var_x2_instructions:315; GFX10-WAVE64: ; %bb.0:316; GFX10-WAVE64-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v0317; GFX10-WAVE64-NEXT: s_mov_b64 s[0:1], exec318; GFX10-WAVE64-NEXT: s_andn2_b64 s[0:1], s[0:1], vcc319; GFX10-WAVE64-NEXT: s_cbranch_scc0 .LBB6_2320; GFX10-WAVE64-NEXT: ; %bb.1:321; GFX10-WAVE64-NEXT: s_andn2_b64 exec, exec, vcc322; GFX10-WAVE64-NEXT: ;;#ASMSTART323; GFX10-WAVE64-NEXT: v_mov_b32_e64 v7, -1324; GFX10-WAVE64-NEXT: ;;#ASMEND325; GFX10-WAVE64-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v7326; GFX10-WAVE64-NEXT: s_andn2_b64 s[0:1], s[0:1], vcc327; GFX10-WAVE64-NEXT: s_cbranch_scc0 .LBB6_2328; GFX10-WAVE64-NEXT: s_endpgm329; GFX10-WAVE64-NEXT: .LBB6_2:330; GFX10-WAVE64-NEXT: s_mov_b64 exec, 0331; GFX10-WAVE64-NEXT: exp null off, off, off, off done vm332; GFX10-WAVE64-NEXT: s_endpgm333;334; GFX10-WAVE32-LABEL: test_kill_depth_var_x2_instructions:335; GFX10-WAVE32: ; %bb.0:336; GFX10-WAVE32-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0, v0337; GFX10-WAVE32-NEXT: s_mov_b32 s0, exec_lo338; GFX10-WAVE32-NEXT: s_andn2_b32 s0, s0, vcc_lo339; GFX10-WAVE32-NEXT: s_cbranch_scc0 .LBB6_2340; GFX10-WAVE32-NEXT: ; %bb.1:341; GFX10-WAVE32-NEXT: s_andn2_b32 exec_lo, exec_lo, vcc_lo342; GFX10-WAVE32-NEXT: ;;#ASMSTART343; GFX10-WAVE32-NEXT: v_mov_b32_e64 v7, -1344; GFX10-WAVE32-NEXT: ;;#ASMEND345; GFX10-WAVE32-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0, v7346; GFX10-WAVE32-NEXT: s_andn2_b32 s0, s0, vcc_lo347; GFX10-WAVE32-NEXT: s_cbranch_scc0 .LBB6_2348; GFX10-WAVE32-NEXT: s_endpgm349; GFX10-WAVE32-NEXT: .LBB6_2:350; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 0351; GFX10-WAVE32-NEXT: exp null off, off, off, off done vm352; GFX10-WAVE32-NEXT: s_endpgm353;354; GFX11-LABEL: test_kill_depth_var_x2_instructions:355; GFX11: ; %bb.0:356; GFX11-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v0357; GFX11-NEXT: s_mov_b64 s[0:1], exec358; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)359; GFX11-NEXT: s_and_not1_b64 s[0:1], s[0:1], vcc360; GFX11-NEXT: s_cbranch_scc0 .LBB6_2361; GFX11-NEXT: ; %bb.1:362; GFX11-NEXT: s_and_not1_b64 exec, exec, vcc363; GFX11-NEXT: ;;#ASMSTART364; GFX11-NEXT: v_mov_b32_e64 v7, -1365; GFX11-NEXT: ;;#ASMEND366; GFX11-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v7367; GFX11-NEXT: s_and_not1_b64 s[0:1], s[0:1], vcc368; GFX11-NEXT: s_cbranch_scc0 .LBB6_2369; GFX11-NEXT: s_endpgm370; GFX11-NEXT: .LBB6_2:371; GFX11-NEXT: s_mov_b64 exec, 0372; GFX11-NEXT: exp mrt0 off, off, off, off done373; GFX11-NEXT: s_endpgm374 %cmp.x = fcmp olt float %x, 0.0375 call void @llvm.amdgcn.kill(i1 %cmp.x)376 %y = call float asm sideeffect "v_mov_b32_e64 v7, -1", "={v7}"()377 %cmp.y = fcmp olt float %y, 0.0378 call void @llvm.amdgcn.kill(i1 %cmp.y)379 ret void380}381 382; FIXME: why does the skip depend on the asm length in the same block?383define amdgpu_ps float @test_kill_control_flow(i32 inreg %arg) #0 {384; SI-LABEL: test_kill_control_flow:385; SI: ; %bb.0: ; %entry386; SI-NEXT: s_cmp_lg_u32 s0, 0387; SI-NEXT: s_cbranch_scc0 .LBB7_2388; SI-NEXT: ; %bb.1: ; %exit389; SI-NEXT: v_mov_b32_e32 v0, 1.0390; SI-NEXT: s_branch .LBB7_5391; SI-NEXT: .LBB7_2: ; %bb392; SI-NEXT: s_mov_b64 s[2:3], exec393; SI-NEXT: ;;#ASMSTART394; SI-NEXT: v_mov_b32_e64 v7, -1395; SI-NEXT: v_nop_e64396; SI-NEXT: v_nop_e64397; SI-NEXT: v_nop_e64398; SI-NEXT: v_nop_e64399; SI-NEXT: v_nop_e64400; SI-NEXT: v_nop_e64401; SI-NEXT: v_nop_e64402; SI-NEXT: v_nop_e64403; SI-NEXT: v_nop_e64404; SI-NEXT: v_nop_e64405; SI-NEXT: ;;#ASMEND406; SI-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v7407; SI-NEXT: s_andn2_b64 s[2:3], s[2:3], vcc408; SI-NEXT: s_cbranch_scc0 .LBB7_4409; SI-NEXT: ; %bb.3: ; %bb410; SI-NEXT: s_andn2_b64 exec, exec, vcc411; SI-NEXT: v_mov_b32_e32 v0, 1.0412; SI-NEXT: s_branch .LBB7_5413; SI-NEXT: .LBB7_4:414; SI-NEXT: s_mov_b64 exec, 0415; SI-NEXT: exp null off, off, off, off done vm416; SI-NEXT: s_endpgm417; SI-NEXT: .LBB7_5:418;419; GFX10-WAVE64-LABEL: test_kill_control_flow:420; GFX10-WAVE64: ; %bb.0: ; %entry421; GFX10-WAVE64-NEXT: s_cmp_lg_u32 s0, 0422; GFX10-WAVE64-NEXT: s_cbranch_scc0 .LBB7_2423; GFX10-WAVE64-NEXT: ; %bb.1: ; %exit424; GFX10-WAVE64-NEXT: v_mov_b32_e32 v0, 1.0425; GFX10-WAVE64-NEXT: s_branch .LBB7_5426; GFX10-WAVE64-NEXT: .LBB7_2: ; %bb427; GFX10-WAVE64-NEXT: ;;#ASMSTART428; GFX10-WAVE64-NEXT: v_mov_b32_e64 v7, -1429; GFX10-WAVE64-NEXT: v_nop_e64430; GFX10-WAVE64-NEXT: v_nop_e64431; GFX10-WAVE64-NEXT: v_nop_e64432; GFX10-WAVE64-NEXT: v_nop_e64433; GFX10-WAVE64-NEXT: v_nop_e64434; GFX10-WAVE64-NEXT: v_nop_e64435; GFX10-WAVE64-NEXT: v_nop_e64436; GFX10-WAVE64-NEXT: v_nop_e64437; GFX10-WAVE64-NEXT: v_nop_e64438; GFX10-WAVE64-NEXT: v_nop_e64439; GFX10-WAVE64-NEXT: ;;#ASMEND440; GFX10-WAVE64-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v7441; GFX10-WAVE64-NEXT: s_mov_b64 s[2:3], exec442; GFX10-WAVE64-NEXT: s_andn2_b64 s[2:3], s[2:3], vcc443; GFX10-WAVE64-NEXT: s_cbranch_scc0 .LBB7_4444; GFX10-WAVE64-NEXT: ; %bb.3: ; %bb445; GFX10-WAVE64-NEXT: s_andn2_b64 exec, exec, vcc446; GFX10-WAVE64-NEXT: v_mov_b32_e32 v0, 1.0447; GFX10-WAVE64-NEXT: s_branch .LBB7_5448; GFX10-WAVE64-NEXT: .LBB7_4:449; GFX10-WAVE64-NEXT: s_mov_b64 exec, 0450; GFX10-WAVE64-NEXT: exp null off, off, off, off done vm451; GFX10-WAVE64-NEXT: s_endpgm452; GFX10-WAVE64-NEXT: .LBB7_5:453;454; GFX10-WAVE32-LABEL: test_kill_control_flow:455; GFX10-WAVE32: ; %bb.0: ; %entry456; GFX10-WAVE32-NEXT: s_cmp_lg_u32 s0, 0457; GFX10-WAVE32-NEXT: s_cbranch_scc0 .LBB7_2458; GFX10-WAVE32-NEXT: ; %bb.1: ; %exit459; GFX10-WAVE32-NEXT: v_mov_b32_e32 v0, 1.0460; GFX10-WAVE32-NEXT: s_branch .LBB7_5461; GFX10-WAVE32-NEXT: .LBB7_2: ; %bb462; GFX10-WAVE32-NEXT: ;;#ASMSTART463; GFX10-WAVE32-NEXT: v_mov_b32_e64 v7, -1464; GFX10-WAVE32-NEXT: v_nop_e64465; GFX10-WAVE32-NEXT: v_nop_e64466; GFX10-WAVE32-NEXT: v_nop_e64467; GFX10-WAVE32-NEXT: v_nop_e64468; GFX10-WAVE32-NEXT: v_nop_e64469; GFX10-WAVE32-NEXT: v_nop_e64470; GFX10-WAVE32-NEXT: v_nop_e64471; GFX10-WAVE32-NEXT: v_nop_e64472; GFX10-WAVE32-NEXT: v_nop_e64473; GFX10-WAVE32-NEXT: v_nop_e64474; GFX10-WAVE32-NEXT: ;;#ASMEND475; GFX10-WAVE32-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0, v7476; GFX10-WAVE32-NEXT: s_mov_b32 s1, exec_lo477; GFX10-WAVE32-NEXT: s_andn2_b32 s1, s1, vcc_lo478; GFX10-WAVE32-NEXT: s_cbranch_scc0 .LBB7_4479; GFX10-WAVE32-NEXT: ; %bb.3: ; %bb480; GFX10-WAVE32-NEXT: s_andn2_b32 exec_lo, exec_lo, vcc_lo481; GFX10-WAVE32-NEXT: v_mov_b32_e32 v0, 1.0482; GFX10-WAVE32-NEXT: s_branch .LBB7_5483; GFX10-WAVE32-NEXT: .LBB7_4:484; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 0485; GFX10-WAVE32-NEXT: exp null off, off, off, off done vm486; GFX10-WAVE32-NEXT: s_endpgm487; GFX10-WAVE32-NEXT: .LBB7_5:488;489; GFX11-LABEL: test_kill_control_flow:490; GFX11: ; %bb.0: ; %entry491; GFX11-NEXT: s_cmp_lg_u32 s0, 0492; GFX11-NEXT: s_cbranch_scc0 .LBB7_2493; GFX11-NEXT: ; %bb.1: ; %exit494; GFX11-NEXT: v_mov_b32_e32 v0, 1.0495; GFX11-NEXT: s_branch .LBB7_5496; GFX11-NEXT: .LBB7_2: ; %bb497; GFX11-NEXT: ;;#ASMSTART498; GFX11-NEXT: v_mov_b32_e64 v7, -1499; GFX11-NEXT: v_nop_e64500; GFX11-NEXT: v_nop_e64501; GFX11-NEXT: v_nop_e64502; GFX11-NEXT: v_nop_e64503; GFX11-NEXT: v_nop_e64504; GFX11-NEXT: v_nop_e64505; GFX11-NEXT: v_nop_e64506; GFX11-NEXT: v_nop_e64507; GFX11-NEXT: v_nop_e64508; GFX11-NEXT: v_nop_e64509; GFX11-NEXT: ;;#ASMEND510; GFX11-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v7511; GFX11-NEXT: s_mov_b64 s[2:3], exec512; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)513; GFX11-NEXT: s_and_not1_b64 s[2:3], s[2:3], vcc514; GFX11-NEXT: s_cbranch_scc0 .LBB7_4515; GFX11-NEXT: ; %bb.3: ; %bb516; GFX11-NEXT: s_and_not1_b64 exec, exec, vcc517; GFX11-NEXT: v_mov_b32_e32 v0, 1.0518; GFX11-NEXT: s_branch .LBB7_5519; GFX11-NEXT: .LBB7_4:520; GFX11-NEXT: s_mov_b64 exec, 0521; GFX11-NEXT: exp mrt0 off, off, off, off done522; GFX11-NEXT: s_endpgm523; GFX11-NEXT: .LBB7_5:524entry:525 %cmp = icmp eq i32 %arg, 0526 br i1 %cmp, label %bb, label %exit527 528bb:529 %var = call float asm sideeffect "v_mov_b32_e64 v7, -1530 v_nop_e64531 v_nop_e64532 v_nop_e64533 v_nop_e64534 v_nop_e64535 v_nop_e64536 v_nop_e64537 v_nop_e64538 v_nop_e64539 v_nop_e64", "={v7}"()540 %cmp.var = fcmp olt float %var, 0.0541 ; TODO: We could do an early-exit here (the branch above is uniform!)542 call void @llvm.amdgcn.kill(i1 %cmp.var)543 br label %exit544 545exit:546 ret float 1.0547}548 549define amdgpu_ps void @test_kill_control_flow_remainder(i32 inreg %arg) #0 {550; SI-LABEL: test_kill_control_flow_remainder:551; SI: ; %bb.0: ; %entry552; SI-NEXT: s_cmp_lg_u32 s0, 0553; SI-NEXT: v_mov_b32_e32 v9, 0554; SI-NEXT: s_cbranch_scc1 .LBB8_3555; SI-NEXT: ; %bb.1: ; %bb556; SI-NEXT: s_mov_b64 s[2:3], exec557; SI-NEXT: ;;#ASMSTART558; SI-NEXT: v_mov_b32_e64 v7, -1559; SI-NEXT: v_nop_e64560; SI-NEXT: v_nop_e64561; SI-NEXT: v_nop_e64562; SI-NEXT: v_nop_e64563; SI-NEXT: v_nop_e64564; SI-NEXT: v_nop_e64565; SI-NEXT: v_nop_e64566; SI-NEXT: v_nop_e64567; SI-NEXT: v_nop_e64568; SI-NEXT: v_nop_e64569; SI-NEXT: v_nop_e64570; SI-NEXT: ;;#ASMEND571; SI-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v7572; SI-NEXT: s_andn2_b64 s[2:3], s[2:3], vcc573; SI-NEXT: ;;#ASMSTART574; SI-NEXT: v_mov_b32_e64 v8, -1575; SI-NEXT: ;;#ASMEND576; SI-NEXT: s_cbranch_scc0 .LBB8_4577; SI-NEXT: ; %bb.2: ; %bb578; SI-NEXT: s_andn2_b64 exec, exec, vcc579; SI-NEXT: s_mov_b32 s3, 0xf000580; SI-NEXT: s_mov_b32 s2, -1581; SI-NEXT: buffer_store_dword v8, off, s[0:3], 0582; SI-NEXT: s_waitcnt vmcnt(0)583; SI-NEXT: ;;#ASMSTART584; SI-NEXT: v_mov_b32_e64 v9, -2585; SI-NEXT: ;;#ASMEND586; SI-NEXT: .LBB8_3: ; %exit587; SI-NEXT: s_mov_b32 s3, 0xf000588; SI-NEXT: s_mov_b32 s2, -1589; SI-NEXT: buffer_store_dword v9, off, s[0:3], 0590; SI-NEXT: s_endpgm591; SI-NEXT: .LBB8_4:592; SI-NEXT: s_mov_b64 exec, 0593; SI-NEXT: exp null off, off, off, off done vm594; SI-NEXT: s_endpgm595;596; GFX10-WAVE64-LABEL: test_kill_control_flow_remainder:597; GFX10-WAVE64: ; %bb.0: ; %entry598; GFX10-WAVE64-NEXT: v_mov_b32_e32 v9, 0599; GFX10-WAVE64-NEXT: s_cmp_lg_u32 s0, 0600; GFX10-WAVE64-NEXT: s_cbranch_scc0 .LBB8_2601; GFX10-WAVE64-NEXT: ; %bb.1: ; %exit602; GFX10-WAVE64-NEXT: global_store_dword v[0:1], v9, off603; GFX10-WAVE64-NEXT: s_endpgm604; GFX10-WAVE64-NEXT: .LBB8_2: ; %bb605; GFX10-WAVE64-NEXT: ;;#ASMSTART606; GFX10-WAVE64-NEXT: v_mov_b32_e64 v7, -1607; GFX10-WAVE64-NEXT: v_nop_e64608; GFX10-WAVE64-NEXT: v_nop_e64609; GFX10-WAVE64-NEXT: v_nop_e64610; GFX10-WAVE64-NEXT: v_nop_e64611; GFX10-WAVE64-NEXT: v_nop_e64612; GFX10-WAVE64-NEXT: v_nop_e64613; GFX10-WAVE64-NEXT: v_nop_e64614; GFX10-WAVE64-NEXT: v_nop_e64615; GFX10-WAVE64-NEXT: v_nop_e64616; GFX10-WAVE64-NEXT: v_nop_e64617; GFX10-WAVE64-NEXT: v_nop_e64618; GFX10-WAVE64-NEXT: ;;#ASMEND619; GFX10-WAVE64-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v7620; GFX10-WAVE64-NEXT: s_mov_b64 s[2:3], exec621; GFX10-WAVE64-NEXT: ;;#ASMSTART622; GFX10-WAVE64-NEXT: v_mov_b32_e64 v8, -1623; GFX10-WAVE64-NEXT: ;;#ASMEND624; GFX10-WAVE64-NEXT: s_andn2_b64 s[2:3], s[2:3], vcc625; GFX10-WAVE64-NEXT: s_cbranch_scc0 .LBB8_4626; GFX10-WAVE64-NEXT: ; %bb.3: ; %bb627; GFX10-WAVE64-NEXT: s_andn2_b64 exec, exec, vcc628; GFX10-WAVE64-NEXT: global_store_dword v[0:1], v8, off629; GFX10-WAVE64-NEXT: s_waitcnt_vscnt null, 0x0630; GFX10-WAVE64-NEXT: ;;#ASMSTART631; GFX10-WAVE64-NEXT: v_mov_b32_e64 v9, -2632; GFX10-WAVE64-NEXT: ;;#ASMEND633; GFX10-WAVE64-NEXT: global_store_dword v[0:1], v9, off634; GFX10-WAVE64-NEXT: s_endpgm635; GFX10-WAVE64-NEXT: .LBB8_4:636; GFX10-WAVE64-NEXT: s_mov_b64 exec, 0637; GFX10-WAVE64-NEXT: exp null off, off, off, off done vm638; GFX10-WAVE64-NEXT: s_endpgm639;640; GFX10-WAVE32-LABEL: test_kill_control_flow_remainder:641; GFX10-WAVE32: ; %bb.0: ; %entry642; GFX10-WAVE32-NEXT: v_mov_b32_e32 v9, 0643; GFX10-WAVE32-NEXT: s_cmp_lg_u32 s0, 0644; GFX10-WAVE32-NEXT: s_cbranch_scc0 .LBB8_2645; GFX10-WAVE32-NEXT: ; %bb.1: ; %exit646; GFX10-WAVE32-NEXT: global_store_dword v[0:1], v9, off647; GFX10-WAVE32-NEXT: s_endpgm648; GFX10-WAVE32-NEXT: .LBB8_2: ; %bb649; GFX10-WAVE32-NEXT: ;;#ASMSTART650; GFX10-WAVE32-NEXT: v_mov_b32_e64 v7, -1651; GFX10-WAVE32-NEXT: v_nop_e64652; GFX10-WAVE32-NEXT: v_nop_e64653; GFX10-WAVE32-NEXT: v_nop_e64654; GFX10-WAVE32-NEXT: v_nop_e64655; GFX10-WAVE32-NEXT: v_nop_e64656; GFX10-WAVE32-NEXT: v_nop_e64657; GFX10-WAVE32-NEXT: v_nop_e64658; GFX10-WAVE32-NEXT: v_nop_e64659; GFX10-WAVE32-NEXT: v_nop_e64660; GFX10-WAVE32-NEXT: v_nop_e64661; GFX10-WAVE32-NEXT: v_nop_e64662; GFX10-WAVE32-NEXT: ;;#ASMEND663; GFX10-WAVE32-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0, v7664; GFX10-WAVE32-NEXT: s_mov_b32 s1, exec_lo665; GFX10-WAVE32-NEXT: ;;#ASMSTART666; GFX10-WAVE32-NEXT: v_mov_b32_e64 v8, -1667; GFX10-WAVE32-NEXT: ;;#ASMEND668; GFX10-WAVE32-NEXT: s_andn2_b32 s1, s1, vcc_lo669; GFX10-WAVE32-NEXT: s_cbranch_scc0 .LBB8_4670; GFX10-WAVE32-NEXT: ; %bb.3: ; %bb671; GFX10-WAVE32-NEXT: s_andn2_b32 exec_lo, exec_lo, vcc_lo672; GFX10-WAVE32-NEXT: global_store_dword v[0:1], v8, off673; GFX10-WAVE32-NEXT: s_waitcnt_vscnt null, 0x0674; GFX10-WAVE32-NEXT: ;;#ASMSTART675; GFX10-WAVE32-NEXT: v_mov_b32_e64 v9, -2676; GFX10-WAVE32-NEXT: ;;#ASMEND677; GFX10-WAVE32-NEXT: global_store_dword v[0:1], v9, off678; GFX10-WAVE32-NEXT: s_endpgm679; GFX10-WAVE32-NEXT: .LBB8_4:680; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 0681; GFX10-WAVE32-NEXT: exp null off, off, off, off done vm682; GFX10-WAVE32-NEXT: s_endpgm683;684; GFX11-LABEL: test_kill_control_flow_remainder:685; GFX11: ; %bb.0: ; %entry686; GFX11-NEXT: v_mov_b32_e32 v9, 0687; GFX11-NEXT: s_cmp_lg_u32 s0, 0688; GFX11-NEXT: s_cbranch_scc0 .LBB8_2689; GFX11-NEXT: ; %bb.1: ; %exit690; GFX11-NEXT: global_store_b32 v[0:1], v9, off691; GFX11-NEXT: s_endpgm692; GFX11-NEXT: .LBB8_2: ; %bb693; GFX11-NEXT: ;;#ASMSTART694; GFX11-NEXT: v_mov_b32_e64 v7, -1695; GFX11-NEXT: v_nop_e64696; GFX11-NEXT: v_nop_e64697; GFX11-NEXT: v_nop_e64698; GFX11-NEXT: v_nop_e64699; GFX11-NEXT: v_nop_e64700; GFX11-NEXT: v_nop_e64701; GFX11-NEXT: v_nop_e64702; GFX11-NEXT: v_nop_e64703; GFX11-NEXT: v_nop_e64704; GFX11-NEXT: v_nop_e64705; GFX11-NEXT: v_nop_e64706; GFX11-NEXT: ;;#ASMEND707; GFX11-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v7708; GFX11-NEXT: s_mov_b64 s[2:3], exec709; GFX11-NEXT: ;;#ASMSTART710; GFX11-NEXT: v_mov_b32_e64 v8, -1711; GFX11-NEXT: ;;#ASMEND712; GFX11-NEXT: s_and_not1_b64 s[2:3], s[2:3], vcc713; GFX11-NEXT: s_cbranch_scc0 .LBB8_4714; GFX11-NEXT: ; %bb.3: ; %bb715; GFX11-NEXT: s_and_not1_b64 exec, exec, vcc716; GFX11-NEXT: global_store_b32 v[0:1], v8, off dlc717; GFX11-NEXT: s_waitcnt_vscnt null, 0x0718; GFX11-NEXT: ;;#ASMSTART719; GFX11-NEXT: v_mov_b32_e64 v9, -2720; GFX11-NEXT: ;;#ASMEND721; GFX11-NEXT: global_store_b32 v[0:1], v9, off722; GFX11-NEXT: s_endpgm723; GFX11-NEXT: .LBB8_4:724; GFX11-NEXT: s_mov_b64 exec, 0725; GFX11-NEXT: exp mrt0 off, off, off, off done726; GFX11-NEXT: s_endpgm727entry:728 %cmp = icmp eq i32 %arg, 0729 br i1 %cmp, label %bb, label %exit730 731bb:732 %var = call float asm sideeffect "v_mov_b32_e64 v7, -1733 v_nop_e64734 v_nop_e64735 v_nop_e64736 v_nop_e64737 v_nop_e64738 v_nop_e64739 v_nop_e64740 v_nop_e64741 v_nop_e64742 v_nop_e64743 v_nop_e64", "={v7}"()744 %live.across = call float asm sideeffect "v_mov_b32_e64 v8, -1", "={v8}"()745 %cmp.var = fcmp olt float %var, 0.0746 ; TODO: We could do an early-exit here (the branch above is uniform!)747 call void @llvm.amdgcn.kill(i1 %cmp.var)748 store volatile float %live.across, ptr addrspace(1) poison749 %live.out = call float asm sideeffect "v_mov_b32_e64 v9, -2", "={v9}"()750 br label %exit751 752exit:753 %phi = phi float [ 0.0, %entry ], [ %live.out, %bb ]754 store float %phi, ptr addrspace(1) poison755 ret void756}757 758define amdgpu_ps float @test_kill_control_flow_return(i32 inreg %arg) #0 {759; SI-LABEL: test_kill_control_flow_return:760; SI: ; %bb.0: ; %entry761; SI-NEXT: s_cmp_eq_u32 s0, 1762; SI-NEXT: s_cselect_b64 s[4:5], -1, 0763; SI-NEXT: s_mov_b64 s[2:3], exec764; SI-NEXT: s_andn2_b64 s[4:5], exec, s[4:5]765; SI-NEXT: s_andn2_b64 s[2:3], s[2:3], s[4:5]766; SI-NEXT: s_cbranch_scc0 .LBB9_4767; SI-NEXT: ; %bb.1: ; %entry768; SI-NEXT: s_and_b64 exec, exec, s[2:3]769; SI-NEXT: s_cmp_lg_u32 s0, 0770; SI-NEXT: v_mov_b32_e32 v0, 0771; SI-NEXT: s_cbranch_scc0 .LBB9_3772; SI-NEXT: ; %bb.2: ; %exit773; SI-NEXT: s_branch .LBB9_5774; SI-NEXT: .LBB9_3: ; %bb775; SI-NEXT: ;;#ASMSTART776; SI-NEXT: v_mov_b32_e64 v7, -1777; SI-NEXT: v_nop_e64778; SI-NEXT: v_nop_e64779; SI-NEXT: v_nop_e64780; SI-NEXT: v_nop_e64781; SI-NEXT: v_nop_e64782; SI-NEXT: v_nop_e64783; SI-NEXT: v_nop_e64784; SI-NEXT: v_nop_e64785; SI-NEXT: v_nop_e64786; SI-NEXT: v_nop_e64787; SI-NEXT: ;;#ASMEND788; SI-NEXT: v_mov_b32_e32 v0, v7789; SI-NEXT: s_branch .LBB9_5790; SI-NEXT: .LBB9_4:791; SI-NEXT: s_mov_b64 exec, 0792; SI-NEXT: exp null off, off, off, off done vm793; SI-NEXT: s_endpgm794; SI-NEXT: .LBB9_5:795;796; GFX10-WAVE64-LABEL: test_kill_control_flow_return:797; GFX10-WAVE64: ; %bb.0: ; %entry798; GFX10-WAVE64-NEXT: s_cmp_eq_u32 s0, 1799; GFX10-WAVE64-NEXT: s_mov_b64 s[2:3], exec800; GFX10-WAVE64-NEXT: s_cselect_b64 s[4:5], -1, 0801; GFX10-WAVE64-NEXT: s_andn2_b64 s[4:5], exec, s[4:5]802; GFX10-WAVE64-NEXT: s_andn2_b64 s[2:3], s[2:3], s[4:5]803; GFX10-WAVE64-NEXT: s_cbranch_scc0 .LBB9_4804; GFX10-WAVE64-NEXT: ; %bb.1: ; %entry805; GFX10-WAVE64-NEXT: s_and_b64 exec, exec, s[2:3]806; GFX10-WAVE64-NEXT: v_mov_b32_e32 v0, 0807; GFX10-WAVE64-NEXT: s_cmp_lg_u32 s0, 0808; GFX10-WAVE64-NEXT: s_cbranch_scc0 .LBB9_3809; GFX10-WAVE64-NEXT: ; %bb.2: ; %exit810; GFX10-WAVE64-NEXT: s_branch .LBB9_5811; GFX10-WAVE64-NEXT: .LBB9_3: ; %bb812; GFX10-WAVE64-NEXT: ;;#ASMSTART813; GFX10-WAVE64-NEXT: v_mov_b32_e64 v7, -1814; GFX10-WAVE64-NEXT: v_nop_e64815; GFX10-WAVE64-NEXT: v_nop_e64816; GFX10-WAVE64-NEXT: v_nop_e64817; GFX10-WAVE64-NEXT: v_nop_e64818; GFX10-WAVE64-NEXT: v_nop_e64819; GFX10-WAVE64-NEXT: v_nop_e64820; GFX10-WAVE64-NEXT: v_nop_e64821; GFX10-WAVE64-NEXT: v_nop_e64822; GFX10-WAVE64-NEXT: v_nop_e64823; GFX10-WAVE64-NEXT: v_nop_e64824; GFX10-WAVE64-NEXT: ;;#ASMEND825; GFX10-WAVE64-NEXT: v_mov_b32_e32 v0, v7826; GFX10-WAVE64-NEXT: s_branch .LBB9_5827; GFX10-WAVE64-NEXT: .LBB9_4:828; GFX10-WAVE64-NEXT: s_mov_b64 exec, 0829; GFX10-WAVE64-NEXT: exp null off, off, off, off done vm830; GFX10-WAVE64-NEXT: s_endpgm831; GFX10-WAVE64-NEXT: .LBB9_5:832;833; GFX10-WAVE32-LABEL: test_kill_control_flow_return:834; GFX10-WAVE32: ; %bb.0: ; %entry835; GFX10-WAVE32-NEXT: s_cmp_eq_u32 s0, 1836; GFX10-WAVE32-NEXT: s_mov_b32 s1, exec_lo837; GFX10-WAVE32-NEXT: s_cselect_b32 s2, -1, 0838; GFX10-WAVE32-NEXT: s_andn2_b32 s2, exec_lo, s2839; GFX10-WAVE32-NEXT: s_andn2_b32 s1, s1, s2840; GFX10-WAVE32-NEXT: s_cbranch_scc0 .LBB9_4841; GFX10-WAVE32-NEXT: ; %bb.1: ; %entry842; GFX10-WAVE32-NEXT: s_and_b32 exec_lo, exec_lo, s1843; GFX10-WAVE32-NEXT: v_mov_b32_e32 v0, 0844; GFX10-WAVE32-NEXT: s_cmp_lg_u32 s0, 0845; GFX10-WAVE32-NEXT: s_cbranch_scc0 .LBB9_3846; GFX10-WAVE32-NEXT: ; %bb.2: ; %exit847; GFX10-WAVE32-NEXT: s_branch .LBB9_5848; GFX10-WAVE32-NEXT: .LBB9_3: ; %bb849; GFX10-WAVE32-NEXT: ;;#ASMSTART850; GFX10-WAVE32-NEXT: v_mov_b32_e64 v7, -1851; GFX10-WAVE32-NEXT: v_nop_e64852; GFX10-WAVE32-NEXT: v_nop_e64853; GFX10-WAVE32-NEXT: v_nop_e64854; GFX10-WAVE32-NEXT: v_nop_e64855; GFX10-WAVE32-NEXT: v_nop_e64856; GFX10-WAVE32-NEXT: v_nop_e64857; GFX10-WAVE32-NEXT: v_nop_e64858; GFX10-WAVE32-NEXT: v_nop_e64859; GFX10-WAVE32-NEXT: v_nop_e64860; GFX10-WAVE32-NEXT: v_nop_e64861; GFX10-WAVE32-NEXT: ;;#ASMEND862; GFX10-WAVE32-NEXT: v_mov_b32_e32 v0, v7863; GFX10-WAVE32-NEXT: s_branch .LBB9_5864; GFX10-WAVE32-NEXT: .LBB9_4:865; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 0866; GFX10-WAVE32-NEXT: exp null off, off, off, off done vm867; GFX10-WAVE32-NEXT: s_endpgm868; GFX10-WAVE32-NEXT: .LBB9_5:869;870; GFX11-LABEL: test_kill_control_flow_return:871; GFX11: ; %bb.0: ; %entry872; GFX11-NEXT: s_cmp_eq_u32 s0, 1873; GFX11-NEXT: s_mov_b64 s[2:3], exec874; GFX11-NEXT: s_cselect_b64 s[4:5], -1, 0875; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)876; GFX11-NEXT: s_and_not1_b64 s[4:5], exec, s[4:5]877; GFX11-NEXT: s_and_not1_b64 s[2:3], s[2:3], s[4:5]878; GFX11-NEXT: s_cbranch_scc0 .LBB9_4879; GFX11-NEXT: ; %bb.1: ; %entry880; GFX11-NEXT: s_and_b64 exec, exec, s[2:3]881; GFX11-NEXT: v_mov_b32_e32 v0, 0882; GFX11-NEXT: s_cmp_lg_u32 s0, 0883; GFX11-NEXT: s_cbranch_scc0 .LBB9_3884; GFX11-NEXT: ; %bb.2: ; %exit885; GFX11-NEXT: s_branch .LBB9_5886; GFX11-NEXT: .LBB9_3: ; %bb887; GFX11-NEXT: ;;#ASMSTART888; GFX11-NEXT: v_mov_b32_e64 v7, -1889; GFX11-NEXT: v_nop_e64890; GFX11-NEXT: v_nop_e64891; GFX11-NEXT: v_nop_e64892; GFX11-NEXT: v_nop_e64893; GFX11-NEXT: v_nop_e64894; GFX11-NEXT: v_nop_e64895; GFX11-NEXT: v_nop_e64896; GFX11-NEXT: v_nop_e64897; GFX11-NEXT: v_nop_e64898; GFX11-NEXT: v_nop_e64899; GFX11-NEXT: ;;#ASMEND900; GFX11-NEXT: v_mov_b32_e32 v0, v7901; GFX11-NEXT: s_branch .LBB9_5902; GFX11-NEXT: .LBB9_4:903; GFX11-NEXT: s_mov_b64 exec, 0904; GFX11-NEXT: exp mrt0 off, off, off, off done905; GFX11-NEXT: s_endpgm906; GFX11-NEXT: .LBB9_5:907entry:908 %kill = icmp eq i32 %arg, 1909 %cmp = icmp eq i32 %arg, 0910 call void @llvm.amdgcn.kill(i1 %kill)911 br i1 %cmp, label %bb, label %exit912 913bb:914 %var = call float asm sideeffect "v_mov_b32_e64 v7, -1915 v_nop_e64916 v_nop_e64917 v_nop_e64918 v_nop_e64919 v_nop_e64920 v_nop_e64921 v_nop_e64922 v_nop_e64923 v_nop_e64924 v_nop_e64", "={v7}"()925 br label %exit926 927exit:928 %ret = phi float [ %var, %bb ], [ 0.0, %entry ]929 ret float %ret930}931 932define amdgpu_ps void @test_kill_divergent_loop(i32 %arg) #0 {933; SI-LABEL: test_kill_divergent_loop:934; SI: ; %bb.0: ; %entry935; SI-NEXT: s_mov_b64 s[0:1], exec936; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0937; SI-NEXT: s_and_saveexec_b64 s[2:3], vcc938; SI-NEXT: s_xor_b64 s[4:5], exec, s[2:3]939; SI-NEXT: s_cbranch_execz .LBB10_4940; SI-NEXT: ; %bb.1: ; %bb.preheader941; SI-NEXT: s_mov_b32 s3, 0xf000942; SI-NEXT: s_mov_b32 s2, -1943; SI-NEXT: .LBB10_2: ; %bb944; SI-NEXT: ; =>This Inner Loop Header: Depth=1945; SI-NEXT: ;;#ASMSTART946; SI-NEXT: v_mov_b32_e64 v7, -1947; SI-NEXT: v_nop_e64948; SI-NEXT: v_nop_e64949; SI-NEXT: v_nop_e64950; SI-NEXT: v_nop_e64951; SI-NEXT: v_nop_e64952; SI-NEXT: v_nop_e64953; SI-NEXT: v_nop_e64954; SI-NEXT: v_nop_e64955; SI-NEXT: v_nop_e64956; SI-NEXT: v_nop_e64957; SI-NEXT: ;;#ASMEND958; SI-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v7959; SI-NEXT: s_andn2_b64 s[0:1], s[0:1], vcc960; SI-NEXT: s_cbranch_scc0 .LBB10_5961; SI-NEXT: ; %bb.3: ; %bb962; SI-NEXT: ; in Loop: Header=BB10_2 Depth=1963; SI-NEXT: s_andn2_b64 exec, exec, vcc964; SI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc965; SI-NEXT: s_waitcnt vmcnt(0)966; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0967; SI-NEXT: s_cbranch_vccnz .LBB10_2968; SI-NEXT: .LBB10_4: ; %Flow1969; SI-NEXT: s_or_b64 exec, exec, s[4:5]970; SI-NEXT: s_mov_b32 s3, 0xf000971; SI-NEXT: s_mov_b32 s2, -1972; SI-NEXT: v_mov_b32_e32 v0, 8973; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0974; SI-NEXT: s_waitcnt vmcnt(0)975; SI-NEXT: s_endpgm976; SI-NEXT: .LBB10_5:977; SI-NEXT: s_mov_b64 exec, 0978; SI-NEXT: exp null off, off, off, off done vm979; SI-NEXT: s_endpgm980;981; GFX10-WAVE64-LABEL: test_kill_divergent_loop:982; GFX10-WAVE64: ; %bb.0: ; %entry983; GFX10-WAVE64-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0984; GFX10-WAVE64-NEXT: s_mov_b64 s[0:1], exec985; GFX10-WAVE64-NEXT: s_and_saveexec_b64 s[2:3], vcc986; GFX10-WAVE64-NEXT: s_xor_b64 s[2:3], exec, s[2:3]987; GFX10-WAVE64-NEXT: s_cbranch_execz .LBB10_3988; GFX10-WAVE64-NEXT: .LBB10_1: ; %bb989; GFX10-WAVE64-NEXT: ; =>This Inner Loop Header: Depth=1990; GFX10-WAVE64-NEXT: ;;#ASMSTART991; GFX10-WAVE64-NEXT: v_mov_b32_e64 v7, -1992; GFX10-WAVE64-NEXT: v_nop_e64993; GFX10-WAVE64-NEXT: v_nop_e64994; GFX10-WAVE64-NEXT: v_nop_e64995; GFX10-WAVE64-NEXT: v_nop_e64996; GFX10-WAVE64-NEXT: v_nop_e64997; GFX10-WAVE64-NEXT: v_nop_e64998; GFX10-WAVE64-NEXT: v_nop_e64999; GFX10-WAVE64-NEXT: v_nop_e641000; GFX10-WAVE64-NEXT: v_nop_e641001; GFX10-WAVE64-NEXT: v_nop_e641002; GFX10-WAVE64-NEXT: ;;#ASMEND1003; GFX10-WAVE64-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v71004; GFX10-WAVE64-NEXT: s_andn2_b64 s[0:1], s[0:1], vcc1005; GFX10-WAVE64-NEXT: s_cbranch_scc0 .LBB10_41006; GFX10-WAVE64-NEXT: ; %bb.2: ; %bb1007; GFX10-WAVE64-NEXT: ; in Loop: Header=BB10_1 Depth=11008; GFX10-WAVE64-NEXT: s_andn2_b64 exec, exec, vcc1009; GFX10-WAVE64-NEXT: global_load_dword v0, v[0:1], off glc dlc1010; GFX10-WAVE64-NEXT: s_waitcnt vmcnt(0)1011; GFX10-WAVE64-NEXT: v_cmp_eq_u32_e32 vcc, 0, v01012; GFX10-WAVE64-NEXT: s_cbranch_vccnz .LBB10_11013; GFX10-WAVE64-NEXT: .LBB10_3: ; %Flow11014; GFX10-WAVE64-NEXT: s_or_b64 exec, exec, s[2:3]1015; GFX10-WAVE64-NEXT: v_mov_b32_e32 v0, 81016; GFX10-WAVE64-NEXT: global_store_dword v[0:1], v0, off1017; GFX10-WAVE64-NEXT: s_waitcnt_vscnt null, 0x01018; GFX10-WAVE64-NEXT: s_endpgm1019; GFX10-WAVE64-NEXT: .LBB10_4:1020; GFX10-WAVE64-NEXT: s_mov_b64 exec, 01021; GFX10-WAVE64-NEXT: exp null off, off, off, off done vm1022; GFX10-WAVE64-NEXT: s_endpgm1023;1024; GFX10-WAVE32-LABEL: test_kill_divergent_loop:1025; GFX10-WAVE32: ; %bb.0: ; %entry1026; GFX10-WAVE32-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v01027; GFX10-WAVE32-NEXT: s_mov_b32 s0, exec_lo1028; GFX10-WAVE32-NEXT: s_and_saveexec_b32 s1, vcc_lo1029; GFX10-WAVE32-NEXT: s_xor_b32 s1, exec_lo, s11030; GFX10-WAVE32-NEXT: s_cbranch_execz .LBB10_31031; GFX10-WAVE32-NEXT: .LBB10_1: ; %bb1032; GFX10-WAVE32-NEXT: ; =>This Inner Loop Header: Depth=11033; GFX10-WAVE32-NEXT: ;;#ASMSTART1034; GFX10-WAVE32-NEXT: v_mov_b32_e64 v7, -11035; GFX10-WAVE32-NEXT: v_nop_e641036; GFX10-WAVE32-NEXT: v_nop_e641037; GFX10-WAVE32-NEXT: v_nop_e641038; GFX10-WAVE32-NEXT: v_nop_e641039; GFX10-WAVE32-NEXT: v_nop_e641040; GFX10-WAVE32-NEXT: v_nop_e641041; GFX10-WAVE32-NEXT: v_nop_e641042; GFX10-WAVE32-NEXT: v_nop_e641043; GFX10-WAVE32-NEXT: v_nop_e641044; GFX10-WAVE32-NEXT: v_nop_e641045; GFX10-WAVE32-NEXT: ;;#ASMEND1046; GFX10-WAVE32-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0, v71047; GFX10-WAVE32-NEXT: s_andn2_b32 s0, s0, vcc_lo1048; GFX10-WAVE32-NEXT: s_cbranch_scc0 .LBB10_41049; GFX10-WAVE32-NEXT: ; %bb.2: ; %bb1050; GFX10-WAVE32-NEXT: ; in Loop: Header=BB10_1 Depth=11051; GFX10-WAVE32-NEXT: s_andn2_b32 exec_lo, exec_lo, vcc_lo1052; GFX10-WAVE32-NEXT: global_load_dword v0, v[0:1], off glc dlc1053; GFX10-WAVE32-NEXT: s_waitcnt vmcnt(0)1054; GFX10-WAVE32-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v01055; GFX10-WAVE32-NEXT: s_cbranch_vccnz .LBB10_11056; GFX10-WAVE32-NEXT: .LBB10_3: ; %Flow11057; GFX10-WAVE32-NEXT: s_or_b32 exec_lo, exec_lo, s11058; GFX10-WAVE32-NEXT: v_mov_b32_e32 v0, 81059; GFX10-WAVE32-NEXT: global_store_dword v[0:1], v0, off1060; GFX10-WAVE32-NEXT: s_waitcnt_vscnt null, 0x01061; GFX10-WAVE32-NEXT: s_endpgm1062; GFX10-WAVE32-NEXT: .LBB10_4:1063; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 01064; GFX10-WAVE32-NEXT: exp null off, off, off, off done vm1065; GFX10-WAVE32-NEXT: s_endpgm1066;1067; GFX11-LABEL: test_kill_divergent_loop:1068; GFX11: ; %bb.0: ; %entry1069; GFX11-NEXT: s_mov_b64 s[0:1], exec1070; GFX11-NEXT: s_mov_b64 s[2:3], exec1071; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v01072; GFX11-NEXT: s_xor_b64 s[2:3], exec, s[2:3]1073; GFX11-NEXT: s_cbranch_execz .LBB10_31074; GFX11-NEXT: .LBB10_1: ; %bb1075; GFX11-NEXT: ; =>This Inner Loop Header: Depth=11076; GFX11-NEXT: ;;#ASMSTART1077; GFX11-NEXT: v_mov_b32_e64 v7, -11078; GFX11-NEXT: v_nop_e641079; GFX11-NEXT: v_nop_e641080; GFX11-NEXT: v_nop_e641081; GFX11-NEXT: v_nop_e641082; GFX11-NEXT: v_nop_e641083; GFX11-NEXT: v_nop_e641084; GFX11-NEXT: v_nop_e641085; GFX11-NEXT: v_nop_e641086; GFX11-NEXT: v_nop_e641087; GFX11-NEXT: v_nop_e641088; GFX11-NEXT: ;;#ASMEND1089; GFX11-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v71090; GFX11-NEXT: s_and_not1_b64 s[0:1], s[0:1], vcc1091; GFX11-NEXT: s_cbranch_scc0 .LBB10_41092; GFX11-NEXT: ; %bb.2: ; %bb1093; GFX11-NEXT: ; in Loop: Header=BB10_1 Depth=11094; GFX11-NEXT: s_and_not1_b64 exec, exec, vcc1095; GFX11-NEXT: global_load_b32 v0, v[0:1], off glc dlc1096; GFX11-NEXT: s_waitcnt vmcnt(0)1097; GFX11-NEXT: v_cmp_eq_u32_e32 vcc, 0, v01098; GFX11-NEXT: s_cbranch_vccnz .LBB10_11099; GFX11-NEXT: .LBB10_3: ; %Flow11100; GFX11-NEXT: s_or_b64 exec, exec, s[2:3]1101; GFX11-NEXT: v_mov_b32_e32 v0, 81102; GFX11-NEXT: global_store_b32 v[0:1], v0, off dlc1103; GFX11-NEXT: s_waitcnt_vscnt null, 0x01104; GFX11-NEXT: s_endpgm1105; GFX11-NEXT: .LBB10_4:1106; GFX11-NEXT: s_mov_b64 exec, 01107; GFX11-NEXT: exp mrt0 off, off, off, off done1108; GFX11-NEXT: s_endpgm1109entry:1110 %cmp = icmp eq i32 %arg, 01111 br i1 %cmp, label %bb, label %exit1112 1113bb:1114 %var = call float asm sideeffect "v_mov_b32_e64 v7, -11115 v_nop_e641116 v_nop_e641117 v_nop_e641118 v_nop_e641119 v_nop_e641120 v_nop_e641121 v_nop_e641122 v_nop_e641123 v_nop_e641124 v_nop_e64", "={v7}"()1125 %cmp.var = fcmp olt float %var, 0.01126 call void @llvm.amdgcn.kill(i1 %cmp.var)1127 %vgpr = load volatile i32, ptr addrspace(1) poison1128 %loop.cond = icmp eq i32 %vgpr, 01129 br i1 %loop.cond, label %bb, label %exit1130 1131exit:1132 store volatile i32 8, ptr addrspace(1) poison1133 ret void1134}1135 1136; bug 285501137define amdgpu_ps void @phi_use_def_before_kill(float inreg %x, i32 inreg %y) #0 {1138; SI-LABEL: phi_use_def_before_kill:1139; SI: ; %bb.0: ; %bb1140; SI-NEXT: v_add_f32_e64 v1, s0, 1.01141; SI-NEXT: v_cmp_lt_f32_e32 vcc, 0, v11142; SI-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc1143; SI-NEXT: v_cmp_nlt_f32_e32 vcc, 0, v11144; SI-NEXT: s_andn2_b64 exec, exec, vcc1145; SI-NEXT: s_cbranch_scc0 .LBB11_61146; SI-NEXT: ; %bb.1: ; %bb1147; SI-NEXT: s_andn2_b64 exec, exec, vcc1148; SI-NEXT: s_cmp_lg_u32 s1, 01149; SI-NEXT: s_cbranch_scc0 .LBB11_31150; SI-NEXT: ; %bb.2: ; %bb81151; SI-NEXT: s_mov_b32 s3, 0xf0001152; SI-NEXT: s_mov_b32 s2, -11153; SI-NEXT: v_mov_b32_e32 v0, 81154; SI-NEXT: buffer_store_dword v0, off, s[0:3], 01155; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)1156; SI-NEXT: v_mov_b32_e32 v0, 4.01157; SI-NEXT: .LBB11_3: ; %phibb1158; SI-NEXT: v_cmp_eq_f32_e32 vcc, 0, v01159; SI-NEXT: s_cbranch_vccz .LBB11_51160; SI-NEXT: ; %bb.4: ; %bb101161; SI-NEXT: s_mov_b32 s3, 0xf0001162; SI-NEXT: s_mov_b32 s2, -11163; SI-NEXT: v_mov_b32_e32 v0, 91164; SI-NEXT: buffer_store_dword v0, off, s[0:3], 01165; SI-NEXT: s_waitcnt vmcnt(0)1166; SI-NEXT: .LBB11_5: ; %end1167; SI-NEXT: s_endpgm1168; SI-NEXT: .LBB11_6:1169; SI-NEXT: s_mov_b64 exec, 01170; SI-NEXT: exp null off, off, off, off done vm1171; SI-NEXT: s_endpgm1172;1173; GFX10-WAVE64-LABEL: phi_use_def_before_kill:1174; GFX10-WAVE64: ; %bb.0: ; %bb1175; GFX10-WAVE64-NEXT: v_add_f32_e64 v1, s0, 1.01176; GFX10-WAVE64-NEXT: v_cmp_lt_f32_e32 vcc, 0, v11177; GFX10-WAVE64-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc1178; GFX10-WAVE64-NEXT: v_cmp_nlt_f32_e32 vcc, 0, v11179; GFX10-WAVE64-NEXT: s_andn2_b64 exec, exec, vcc1180; GFX10-WAVE64-NEXT: s_cbranch_scc0 .LBB11_61181; GFX10-WAVE64-NEXT: ; %bb.1: ; %bb1182; GFX10-WAVE64-NEXT: s_andn2_b64 exec, exec, vcc1183; GFX10-WAVE64-NEXT: s_cmp_lg_u32 s1, 01184; GFX10-WAVE64-NEXT: s_cbranch_scc0 .LBB11_31185; GFX10-WAVE64-NEXT: ; %bb.2: ; %bb81186; GFX10-WAVE64-NEXT: v_mov_b32_e32 v1, 81187; GFX10-WAVE64-NEXT: v_mov_b32_e32 v0, 4.01188; GFX10-WAVE64-NEXT: global_store_dword v[0:1], v1, off1189; GFX10-WAVE64-NEXT: s_waitcnt_vscnt null, 0x01190; GFX10-WAVE64-NEXT: .LBB11_3: ; %phibb1191; GFX10-WAVE64-NEXT: v_cmp_eq_f32_e32 vcc, 0, v01192; GFX10-WAVE64-NEXT: s_cbranch_vccz .LBB11_51193; GFX10-WAVE64-NEXT: ; %bb.4: ; %bb101194; GFX10-WAVE64-NEXT: v_mov_b32_e32 v0, 91195; GFX10-WAVE64-NEXT: global_store_dword v[0:1], v0, off1196; GFX10-WAVE64-NEXT: s_waitcnt_vscnt null, 0x01197; GFX10-WAVE64-NEXT: .LBB11_5: ; %end1198; GFX10-WAVE64-NEXT: s_endpgm1199; GFX10-WAVE64-NEXT: .LBB11_6:1200; GFX10-WAVE64-NEXT: s_mov_b64 exec, 01201; GFX10-WAVE64-NEXT: exp null off, off, off, off done vm1202; GFX10-WAVE64-NEXT: s_endpgm1203;1204; GFX10-WAVE32-LABEL: phi_use_def_before_kill:1205; GFX10-WAVE32: ; %bb.0: ; %bb1206; GFX10-WAVE32-NEXT: v_add_f32_e64 v1, s0, 1.01207; GFX10-WAVE32-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0, v11208; GFX10-WAVE32-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc_lo1209; GFX10-WAVE32-NEXT: v_cmp_nlt_f32_e32 vcc_lo, 0, v11210; GFX10-WAVE32-NEXT: s_andn2_b32 exec_lo, exec_lo, vcc_lo1211; GFX10-WAVE32-NEXT: s_cbranch_scc0 .LBB11_61212; GFX10-WAVE32-NEXT: ; %bb.1: ; %bb1213; GFX10-WAVE32-NEXT: s_andn2_b32 exec_lo, exec_lo, vcc_lo1214; GFX10-WAVE32-NEXT: s_cmp_lg_u32 s1, 01215; GFX10-WAVE32-NEXT: s_cbranch_scc0 .LBB11_31216; GFX10-WAVE32-NEXT: ; %bb.2: ; %bb81217; GFX10-WAVE32-NEXT: v_mov_b32_e32 v1, 81218; GFX10-WAVE32-NEXT: v_mov_b32_e32 v0, 4.01219; GFX10-WAVE32-NEXT: global_store_dword v[0:1], v1, off1220; GFX10-WAVE32-NEXT: s_waitcnt_vscnt null, 0x01221; GFX10-WAVE32-NEXT: .LBB11_3: ; %phibb1222; GFX10-WAVE32-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v01223; GFX10-WAVE32-NEXT: s_cbranch_vccz .LBB11_51224; GFX10-WAVE32-NEXT: ; %bb.4: ; %bb101225; GFX10-WAVE32-NEXT: v_mov_b32_e32 v0, 91226; GFX10-WAVE32-NEXT: global_store_dword v[0:1], v0, off1227; GFX10-WAVE32-NEXT: s_waitcnt_vscnt null, 0x01228; GFX10-WAVE32-NEXT: .LBB11_5: ; %end1229; GFX10-WAVE32-NEXT: s_endpgm1230; GFX10-WAVE32-NEXT: .LBB11_6:1231; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 01232; GFX10-WAVE32-NEXT: exp null off, off, off, off done vm1233; GFX10-WAVE32-NEXT: s_endpgm1234;1235; GFX11-LABEL: phi_use_def_before_kill:1236; GFX11: ; %bb.0: ; %bb1237; GFX11-NEXT: v_add_f32_e64 v1, s0, 1.01238; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)1239; GFX11-NEXT: v_cmp_lt_f32_e32 vcc, 0, v11240; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc1241; GFX11-NEXT: v_cmp_nlt_f32_e32 vcc, 0, v11242; GFX11-NEXT: s_waitcnt_depctr depctr_va_vcc(0)1243; GFX11-NEXT: s_and_not1_b64 exec, exec, vcc1244; GFX11-NEXT: s_cbranch_scc0 .LBB11_61245; GFX11-NEXT: ; %bb.1: ; %bb1246; GFX11-NEXT: s_and_not1_b64 exec, exec, vcc1247; GFX11-NEXT: s_cmp_lg_u32 s1, 01248; GFX11-NEXT: s_cbranch_scc0 .LBB11_31249; GFX11-NEXT: ; %bb.2: ; %bb81250; GFX11-NEXT: v_mov_b32_e32 v1, 81251; GFX11-NEXT: v_mov_b32_e32 v0, 4.01252; GFX11-NEXT: global_store_b32 v[0:1], v1, off dlc1253; GFX11-NEXT: s_waitcnt_vscnt null, 0x01254; GFX11-NEXT: .LBB11_3: ; %phibb1255; GFX11-NEXT: v_cmp_eq_f32_e32 vcc, 0, v01256; GFX11-NEXT: s_cbranch_vccz .LBB11_51257; GFX11-NEXT: ; %bb.4: ; %bb101258; GFX11-NEXT: v_mov_b32_e32 v0, 91259; GFX11-NEXT: global_store_b32 v[0:1], v0, off dlc1260; GFX11-NEXT: s_waitcnt_vscnt null, 0x01261; GFX11-NEXT: .LBB11_5: ; %end1262; GFX11-NEXT: s_endpgm1263; GFX11-NEXT: .LBB11_6:1264; GFX11-NEXT: s_mov_b64 exec, 01265; GFX11-NEXT: exp mrt0 off, off, off, off done1266; GFX11-NEXT: s_endpgm1267bb:1268 %tmp = fadd float %x, 1.000000e+001269 %tmp1 = fcmp olt float 0.000000e+00, %tmp1270 %tmp2 = select i1 %tmp1, float -1.000000e+00, float 0.000000e+001271 %cmp.tmp2 = fcmp olt float %tmp2, 0.01272 call void @llvm.amdgcn.kill(i1 %cmp.tmp2)1273 %uniform.cond = icmp eq i32 %y, 01274 br i1 %uniform.cond, label %phibb, label %bb81275 1276phibb:1277 %tmp5 = phi float [ %tmp2, %bb ], [ 4.0, %bb8 ]1278 %tmp6 = fcmp oeq float %tmp5, 0.000000e+001279 br i1 %tmp6, label %bb10, label %end1280 1281bb8:1282 store volatile i32 8, ptr addrspace(1) poison1283 br label %phibb1284 1285bb10:1286 store volatile i32 9, ptr addrspace(1) poison1287 br label %end1288 1289end:1290 ret void1291}1292 1293define amdgpu_ps void @no_skip_no_successors(float inreg %arg, float inreg %arg1) #0 {1294; SI-LABEL: no_skip_no_successors:1295; SI: ; %bb.0: ; %bb1296; SI-NEXT: v_cmp_nge_f32_e64 s[4:5], s1, 01297; SI-NEXT: s_and_b64 vcc, exec, s[4:5]1298; SI-NEXT: s_cbranch_vccz .LBB12_31299; SI-NEXT: ; %bb.1: ; %bb61300; SI-NEXT: s_mov_b64 s[2:3], exec1301; SI-NEXT: s_andn2_b64 s[2:3], s[2:3], exec1302; SI-NEXT: s_cbranch_scc0 .LBB12_51303; SI-NEXT: ; %bb.2: ; %bb61304; SI-NEXT: s_mov_b64 exec, 01305; SI-NEXT: .LBB12_3: ; %bb31306; SI-NEXT: v_mov_b32_e32 v0, 0x3e7ae1481307; SI-NEXT: v_cmp_nge_f32_e32 vcc, s0, v01308; SI-NEXT: s_and_b64 vcc, exec, vcc1309; SI-NEXT: ; %bb.4: ; %bb51310; SI-NEXT: .LBB12_5:1311; SI-NEXT: s_mov_b64 exec, 01312; SI-NEXT: exp null off, off, off, off done vm1313; SI-NEXT: s_endpgm1314;1315; GFX10-WAVE64-LABEL: no_skip_no_successors:1316; GFX10-WAVE64: ; %bb.0: ; %bb1317; GFX10-WAVE64-NEXT: v_cmp_nge_f32_e64 s[4:5], s1, 01318; GFX10-WAVE64-NEXT: s_and_b64 vcc, exec, s[4:5]1319; GFX10-WAVE64-NEXT: s_cbranch_vccz .LBB12_31320; GFX10-WAVE64-NEXT: ; %bb.1: ; %bb61321; GFX10-WAVE64-NEXT: s_mov_b64 s[2:3], exec1322; GFX10-WAVE64-NEXT: s_andn2_b64 s[2:3], s[2:3], exec1323; GFX10-WAVE64-NEXT: s_cbranch_scc0 .LBB12_51324; GFX10-WAVE64-NEXT: ; %bb.2: ; %bb61325; GFX10-WAVE64-NEXT: s_mov_b64 exec, 01326; GFX10-WAVE64-NEXT: .LBB12_3: ; %bb31327; GFX10-WAVE64-NEXT: v_cmp_nle_f32_e64 s[0:1], 0x3e7ae148, s01328; GFX10-WAVE64-NEXT: s_and_b64 vcc, exec, s[0:1]1329; GFX10-WAVE64-NEXT: ; %bb.4: ; %bb51330; GFX10-WAVE64-NEXT: .LBB12_5:1331; GFX10-WAVE64-NEXT: s_mov_b64 exec, 01332; GFX10-WAVE64-NEXT: exp null off, off, off, off done vm1333; GFX10-WAVE64-NEXT: s_endpgm1334;1335; GFX10-WAVE32-LABEL: no_skip_no_successors:1336; GFX10-WAVE32: ; %bb.0: ; %bb1337; GFX10-WAVE32-NEXT: v_cmp_nge_f32_e64 s1, s1, 01338; GFX10-WAVE32-NEXT: s_and_b32 vcc_lo, exec_lo, s11339; GFX10-WAVE32-NEXT: s_cbranch_vccz .LBB12_31340; GFX10-WAVE32-NEXT: ; %bb.1: ; %bb61341; GFX10-WAVE32-NEXT: s_mov_b32 s2, exec_lo1342; GFX10-WAVE32-NEXT: s_andn2_b32 s2, s2, exec_lo1343; GFX10-WAVE32-NEXT: s_cbranch_scc0 .LBB12_51344; GFX10-WAVE32-NEXT: ; %bb.2: ; %bb61345; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 01346; GFX10-WAVE32-NEXT: .LBB12_3: ; %bb31347; GFX10-WAVE32-NEXT: v_cmp_nle_f32_e64 s0, 0x3e7ae148, s01348; GFX10-WAVE32-NEXT: s_and_b32 vcc_lo, exec_lo, s01349; GFX10-WAVE32-NEXT: ; %bb.4: ; %bb51350; GFX10-WAVE32-NEXT: .LBB12_5:1351; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 01352; GFX10-WAVE32-NEXT: exp null off, off, off, off done vm1353; GFX10-WAVE32-NEXT: s_endpgm1354;1355; GFX11-LABEL: no_skip_no_successors:1356; GFX11: ; %bb.0: ; %bb1357; GFX11-NEXT: v_cmp_nge_f32_e64 s[4:5], s1, 01358; GFX11-NEXT: s_and_b64 vcc, exec, s[4:5]1359; GFX11-NEXT: s_cbranch_vccz .LBB12_31360; GFX11-NEXT: ; %bb.1: ; %bb61361; GFX11-NEXT: s_mov_b64 s[2:3], exec1362; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)1363; GFX11-NEXT: s_and_not1_b64 s[2:3], s[2:3], exec1364; GFX11-NEXT: s_cbranch_scc0 .LBB12_51365; GFX11-NEXT: ; %bb.2: ; %bb61366; GFX11-NEXT: s_mov_b64 exec, 01367; GFX11-NEXT: .LBB12_3: ; %bb31368; GFX11-NEXT: v_cmp_nle_f32_e64 s[0:1], 0x3e7ae148, s01369; GFX11-NEXT: s_and_b64 vcc, exec, s[0:1]1370; GFX11-NEXT: ; %bb.4: ; %bb51371; GFX11-NEXT: .LBB12_5:1372; GFX11-NEXT: s_mov_b64 exec, 01373; GFX11-NEXT: exp mrt0 off, off, off, off done1374; GFX11-NEXT: s_endpgm1375bb:1376 %tmp = fcmp ult float %arg1, 0.000000e+001377 br i1 %tmp, label %bb6, label %bb31378 1379bb3: ; preds = %bb1380 %tmp2 = fcmp ult float %arg, 0x3FCF5C29000000001381 br i1 %tmp2, label %bb5, label %bb41382 1383bb4: ; preds = %bb31384 br i1 true, label %bb5, label %bb71385 1386bb5: ; preds = %bb4, %bb31387 unreachable1388 1389bb6: ; preds = %bb1390 call void @llvm.amdgcn.kill(i1 false)1391 unreachable1392 1393bb7: ; preds = %bb41394 ret void1395}1396 1397define amdgpu_ps void @if_after_kill_block(float %arg, float %arg1, float %arg2, float %arg3) #0 {1398; SI-LABEL: if_after_kill_block:1399; SI: ; %bb.0: ; %bb1400; SI-NEXT: s_mov_b64 s[0:1], exec1401; SI-NEXT: s_wqm_b64 exec, exec1402; SI-NEXT: v_cmp_nle_f32_e32 vcc, 0, v11403; SI-NEXT: s_and_saveexec_b64 s[2:3], vcc1404; SI-NEXT: s_xor_b64 s[2:3], exec, s[2:3]1405; SI-NEXT: s_cbranch_execz .LBB13_31406; SI-NEXT: ; %bb.1: ; %bb31407; SI-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v01408; SI-NEXT: s_andn2_b64 s[0:1], s[0:1], vcc1409; SI-NEXT: s_cbranch_scc0 .LBB13_61410; SI-NEXT: ; %bb.2: ; %bb31411; SI-NEXT: s_andn2_b64 exec, exec, vcc1412; SI-NEXT: .LBB13_3: ; %bb41413; SI-NEXT: s_or_b64 exec, exec, s[2:3]1414; SI-NEXT: image_sample_c v0, v[2:3], s[0:7], s[0:3] dmask:0x101415; SI-NEXT: s_waitcnt vmcnt(0)1416; SI-NEXT: v_cmp_neq_f32_e32 vcc, 0, v01417; SI-NEXT: s_and_saveexec_b64 s[0:1], vcc1418; SI-NEXT: s_cbranch_execz .LBB13_51419; SI-NEXT: ; %bb.4: ; %bb81420; SI-NEXT: s_mov_b32 s3, 0xf0001421; SI-NEXT: s_mov_b32 s2, -11422; SI-NEXT: v_mov_b32_e32 v0, 91423; SI-NEXT: buffer_store_dword v0, off, s[0:3], 01424; SI-NEXT: s_waitcnt vmcnt(0)1425; SI-NEXT: .LBB13_5: ; %UnifiedReturnBlock1426; SI-NEXT: s_endpgm1427; SI-NEXT: .LBB13_6:1428; SI-NEXT: s_mov_b64 exec, 01429; SI-NEXT: exp null off, off, off, off done vm1430; SI-NEXT: s_endpgm1431;1432; GFX10-WAVE64-LABEL: if_after_kill_block:1433; GFX10-WAVE64: ; %bb.0: ; %bb1434; GFX10-WAVE64-NEXT: s_mov_b64 s[0:1], exec1435; GFX10-WAVE64-NEXT: s_wqm_b64 exec, exec1436; GFX10-WAVE64-NEXT: v_cmp_nle_f32_e32 vcc, 0, v11437; GFX10-WAVE64-NEXT: s_and_saveexec_b64 s[2:3], vcc1438; GFX10-WAVE64-NEXT: s_xor_b64 s[2:3], exec, s[2:3]1439; GFX10-WAVE64-NEXT: s_cbranch_execz .LBB13_31440; GFX10-WAVE64-NEXT: ; %bb.1: ; %bb31441; GFX10-WAVE64-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v01442; GFX10-WAVE64-NEXT: s_andn2_b64 s[0:1], s[0:1], vcc1443; GFX10-WAVE64-NEXT: s_cbranch_scc0 .LBB13_61444; GFX10-WAVE64-NEXT: ; %bb.2: ; %bb31445; GFX10-WAVE64-NEXT: s_andn2_b64 exec, exec, vcc1446; GFX10-WAVE64-NEXT: .LBB13_3: ; %bb41447; GFX10-WAVE64-NEXT: s_or_b64 exec, exec, s[2:3]1448; GFX10-WAVE64-NEXT: image_sample_c v0, v[2:3], s[0:7], s[0:3] dmask:0x10 dim:SQ_RSRC_IMG_1D1449; GFX10-WAVE64-NEXT: s_waitcnt vmcnt(0)1450; GFX10-WAVE64-NEXT: v_cmp_neq_f32_e32 vcc, 0, v01451; GFX10-WAVE64-NEXT: s_and_saveexec_b64 s[0:1], vcc1452; GFX10-WAVE64-NEXT: s_cbranch_execz .LBB13_51453; GFX10-WAVE64-NEXT: ; %bb.4: ; %bb81454; GFX10-WAVE64-NEXT: v_mov_b32_e32 v0, 91455; GFX10-WAVE64-NEXT: global_store_dword v[0:1], v0, off1456; GFX10-WAVE64-NEXT: s_waitcnt_vscnt null, 0x01457; GFX10-WAVE64-NEXT: .LBB13_5: ; %UnifiedReturnBlock1458; GFX10-WAVE64-NEXT: s_endpgm1459; GFX10-WAVE64-NEXT: .LBB13_6:1460; GFX10-WAVE64-NEXT: s_mov_b64 exec, 01461; GFX10-WAVE64-NEXT: exp null off, off, off, off done vm1462; GFX10-WAVE64-NEXT: s_endpgm1463;1464; GFX10-WAVE32-LABEL: if_after_kill_block:1465; GFX10-WAVE32: ; %bb.0: ; %bb1466; GFX10-WAVE32-NEXT: s_mov_b32 s0, exec_lo1467; GFX10-WAVE32-NEXT: s_wqm_b32 exec_lo, exec_lo1468; GFX10-WAVE32-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0, v11469; GFX10-WAVE32-NEXT: s_and_saveexec_b32 s1, vcc_lo1470; GFX10-WAVE32-NEXT: s_xor_b32 s1, exec_lo, s11471; GFX10-WAVE32-NEXT: s_cbranch_execz .LBB13_31472; GFX10-WAVE32-NEXT: ; %bb.1: ; %bb31473; GFX10-WAVE32-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0, v01474; GFX10-WAVE32-NEXT: s_andn2_b32 s0, s0, vcc_lo1475; GFX10-WAVE32-NEXT: s_cbranch_scc0 .LBB13_61476; GFX10-WAVE32-NEXT: ; %bb.2: ; %bb31477; GFX10-WAVE32-NEXT: s_andn2_b32 exec_lo, exec_lo, vcc_lo1478; GFX10-WAVE32-NEXT: .LBB13_3: ; %bb41479; GFX10-WAVE32-NEXT: s_or_b32 exec_lo, exec_lo, s11480; GFX10-WAVE32-NEXT: image_sample_c v0, v[2:3], s[0:7], s[0:3] dmask:0x10 dim:SQ_RSRC_IMG_1D1481; GFX10-WAVE32-NEXT: s_waitcnt vmcnt(0)1482; GFX10-WAVE32-NEXT: v_cmp_neq_f32_e32 vcc_lo, 0, v01483; GFX10-WAVE32-NEXT: s_and_saveexec_b32 s0, vcc_lo1484; GFX10-WAVE32-NEXT: s_cbranch_execz .LBB13_51485; GFX10-WAVE32-NEXT: ; %bb.4: ; %bb81486; GFX10-WAVE32-NEXT: v_mov_b32_e32 v0, 91487; GFX10-WAVE32-NEXT: global_store_dword v[0:1], v0, off1488; GFX10-WAVE32-NEXT: s_waitcnt_vscnt null, 0x01489; GFX10-WAVE32-NEXT: .LBB13_5: ; %UnifiedReturnBlock1490; GFX10-WAVE32-NEXT: s_endpgm1491; GFX10-WAVE32-NEXT: .LBB13_6:1492; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 01493; GFX10-WAVE32-NEXT: exp null off, off, off, off done vm1494; GFX10-WAVE32-NEXT: s_endpgm1495;1496; GFX11-LABEL: if_after_kill_block:1497; GFX11: ; %bb.0: ; %bb1498; GFX11-NEXT: s_mov_b64 s[0:1], exec1499; GFX11-NEXT: s_wqm_b64 exec, exec1500; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)1501; GFX11-NEXT: s_mov_b64 s[2:3], exec1502; GFX11-NEXT: v_cmpx_nle_f32_e32 0, v11503; GFX11-NEXT: s_xor_b64 s[2:3], exec, s[2:3]1504; GFX11-NEXT: s_cbranch_execz .LBB13_31505; GFX11-NEXT: ; %bb.1: ; %bb31506; GFX11-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v01507; GFX11-NEXT: s_and_not1_b64 s[0:1], s[0:1], vcc1508; GFX11-NEXT: s_cbranch_scc0 .LBB13_61509; GFX11-NEXT: ; %bb.2: ; %bb31510; GFX11-NEXT: s_and_not1_b64 exec, exec, vcc1511; GFX11-NEXT: .LBB13_3: ; %bb41512; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)1513; GFX11-NEXT: s_or_b64 exec, exec, s[2:3]1514; GFX11-NEXT: image_sample_c v0, v[2:3], s[0:7], s[0:3] dmask:0x10 dim:SQ_RSRC_IMG_1D1515; GFX11-NEXT: s_mov_b64 s[0:1], exec1516; GFX11-NEXT: s_waitcnt vmcnt(0)1517; GFX11-NEXT: v_cmpx_neq_f32_e32 0, v01518; GFX11-NEXT: s_cbranch_execz .LBB13_51519; GFX11-NEXT: ; %bb.4: ; %bb81520; GFX11-NEXT: v_mov_b32_e32 v0, 91521; GFX11-NEXT: global_store_b32 v[0:1], v0, off dlc1522; GFX11-NEXT: s_waitcnt_vscnt null, 0x01523; GFX11-NEXT: .LBB13_5: ; %UnifiedReturnBlock1524; GFX11-NEXT: s_endpgm1525; GFX11-NEXT: .LBB13_6:1526; GFX11-NEXT: s_mov_b64 exec, 01527; GFX11-NEXT: exp mrt0 off, off, off, off done1528; GFX11-NEXT: s_endpgm1529bb:1530 %tmp = fcmp ult float %arg1, 0.000000e+001531 br i1 %tmp, label %bb3, label %bb41532 1533bb3: ; preds = %bb1534 %cmp.arg = fcmp olt float %arg, 0.01535 call void @llvm.amdgcn.kill(i1 %cmp.arg)1536 br label %bb41537 1538bb4: ; preds = %bb3, %bb1539 %tmp5 = call <4 x float> @llvm.amdgcn.image.sample.c.1d.v4f32.f32(i32 16, float %arg2, float %arg3, <8 x i32> poison, <4 x i32> poison, i1 0, i32 0, i32 0)1540 %tmp6 = extractelement <4 x float> %tmp5, i32 01541 %tmp7 = fcmp une float %tmp6, 0.000000e+001542 br i1 %tmp7, label %bb8, label %bb91543 1544bb8: ; preds = %bb9, %bb41545 store volatile i32 9, ptr addrspace(1) poison1546 ret void1547 1548bb9: ; preds = %bb41549 ret void1550}1551 1552define amdgpu_ps void @cbranch_kill(i32 inreg %0, float %val0, float %val1) {1553; SI-LABEL: cbranch_kill:1554; SI: ; %bb.0: ; %.entry1555; SI-NEXT: s_mov_b64 s[0:1], exec1556; SI-NEXT: v_mov_b32_e32 v4, 01557; SI-NEXT: v_mov_b32_e32 v2, v11558; SI-NEXT: v_mov_b32_e32 v3, v11559; SI-NEXT: image_sample_l v1, v[1:4], s[0:7], s[0:3] dmask:0x1 da1560; SI-NEXT: s_waitcnt vmcnt(0)1561; SI-NEXT: v_cmp_ge_f32_e32 vcc, 0, v11562; SI-NEXT: s_and_saveexec_b64 s[2:3], vcc1563; SI-NEXT: s_xor_b64 s[2:3], exec, s[2:3]1564; SI-NEXT: s_cbranch_execz .LBB14_31565; SI-NEXT: ; %bb.1: ; %kill1566; SI-NEXT: s_andn2_b64 s[0:1], s[0:1], exec1567; SI-NEXT: ; implicit-def: $vgpr01568; SI-NEXT: ; implicit-def: $vgpr11569; SI-NEXT: s_cbranch_scc0 .LBB14_61570; SI-NEXT: ; %bb.2: ; %kill1571; SI-NEXT: s_mov_b64 exec, 01572; SI-NEXT: .LBB14_3: ; %Flow1573; SI-NEXT: s_or_saveexec_b64 s[0:1], s[2:3]1574; SI-NEXT: ; implicit-def: $vgpr21575; SI-NEXT: s_xor_b64 exec, exec, s[0:1]1576; SI-NEXT: ; %bb.4: ; %live1577; SI-NEXT: v_mul_f32_e32 v2, v0, v11578; SI-NEXT: ; %bb.5: ; %export1579; SI-NEXT: s_or_b64 exec, exec, s[0:1]1580; SI-NEXT: exp mrt0 v2, v2, v2, v2 done vm1581; SI-NEXT: s_endpgm1582; SI-NEXT: .LBB14_6:1583; SI-NEXT: s_mov_b64 exec, 01584; SI-NEXT: exp null off, off, off, off done vm1585; SI-NEXT: s_endpgm1586;1587; GFX10-WAVE64-LABEL: cbranch_kill:1588; GFX10-WAVE64: ; %bb.0: ; %.entry1589; GFX10-WAVE64-NEXT: v_mov_b32_e32 v2, 01590; GFX10-WAVE64-NEXT: s_mov_b64 s[0:1], exec1591; GFX10-WAVE64-NEXT: image_sample_l v1, [v1, v1, v1, v2], s[0:7], s[0:3] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY1592; GFX10-WAVE64-NEXT: s_waitcnt vmcnt(0)1593; GFX10-WAVE64-NEXT: v_cmp_ge_f32_e32 vcc, 0, v11594; GFX10-WAVE64-NEXT: s_and_saveexec_b64 s[2:3], vcc1595; GFX10-WAVE64-NEXT: s_xor_b64 s[2:3], exec, s[2:3]1596; GFX10-WAVE64-NEXT: s_cbranch_execz .LBB14_31597; GFX10-WAVE64-NEXT: ; %bb.1: ; %kill1598; GFX10-WAVE64-NEXT: s_andn2_b64 s[0:1], s[0:1], exec1599; GFX10-WAVE64-NEXT: ; implicit-def: $vgpr01600; GFX10-WAVE64-NEXT: ; implicit-def: $vgpr11601; GFX10-WAVE64-NEXT: s_cbranch_scc0 .LBB14_61602; GFX10-WAVE64-NEXT: ; %bb.2: ; %kill1603; GFX10-WAVE64-NEXT: s_mov_b64 exec, 01604; GFX10-WAVE64-NEXT: .LBB14_3: ; %Flow1605; GFX10-WAVE64-NEXT: s_or_saveexec_b64 s[0:1], s[2:3]1606; GFX10-WAVE64-NEXT: ; implicit-def: $vgpr21607; GFX10-WAVE64-NEXT: s_xor_b64 exec, exec, s[0:1]1608; GFX10-WAVE64-NEXT: ; %bb.4: ; %live1609; GFX10-WAVE64-NEXT: v_mul_f32_e32 v2, v0, v11610; GFX10-WAVE64-NEXT: ; %bb.5: ; %export1611; GFX10-WAVE64-NEXT: s_or_b64 exec, exec, s[0:1]1612; GFX10-WAVE64-NEXT: exp mrt0 v2, v2, v2, v2 done vm1613; GFX10-WAVE64-NEXT: s_endpgm1614; GFX10-WAVE64-NEXT: .LBB14_6:1615; GFX10-WAVE64-NEXT: s_mov_b64 exec, 01616; GFX10-WAVE64-NEXT: exp null off, off, off, off done vm1617; GFX10-WAVE64-NEXT: s_endpgm1618;1619; GFX10-WAVE32-LABEL: cbranch_kill:1620; GFX10-WAVE32: ; %bb.0: ; %.entry1621; GFX10-WAVE32-NEXT: v_mov_b32_e32 v2, 01622; GFX10-WAVE32-NEXT: s_mov_b32 s0, exec_lo1623; GFX10-WAVE32-NEXT: image_sample_l v1, [v1, v1, v1, v2], s[0:7], s[0:3] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY1624; GFX10-WAVE32-NEXT: s_waitcnt vmcnt(0)1625; GFX10-WAVE32-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v11626; GFX10-WAVE32-NEXT: s_and_saveexec_b32 s1, vcc_lo1627; GFX10-WAVE32-NEXT: s_xor_b32 s1, exec_lo, s11628; GFX10-WAVE32-NEXT: s_cbranch_execz .LBB14_31629; GFX10-WAVE32-NEXT: ; %bb.1: ; %kill1630; GFX10-WAVE32-NEXT: s_andn2_b32 s0, s0, exec_lo1631; GFX10-WAVE32-NEXT: ; implicit-def: $vgpr01632; GFX10-WAVE32-NEXT: ; implicit-def: $vgpr11633; GFX10-WAVE32-NEXT: s_cbranch_scc0 .LBB14_61634; GFX10-WAVE32-NEXT: ; %bb.2: ; %kill1635; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 01636; GFX10-WAVE32-NEXT: .LBB14_3: ; %Flow1637; GFX10-WAVE32-NEXT: s_or_saveexec_b32 s0, s11638; GFX10-WAVE32-NEXT: ; implicit-def: $vgpr21639; GFX10-WAVE32-NEXT: s_xor_b32 exec_lo, exec_lo, s01640; GFX10-WAVE32-NEXT: ; %bb.4: ; %live1641; GFX10-WAVE32-NEXT: v_mul_f32_e32 v2, v0, v11642; GFX10-WAVE32-NEXT: ; %bb.5: ; %export1643; GFX10-WAVE32-NEXT: s_or_b32 exec_lo, exec_lo, s01644; GFX10-WAVE32-NEXT: exp mrt0 v2, v2, v2, v2 done vm1645; GFX10-WAVE32-NEXT: s_endpgm1646; GFX10-WAVE32-NEXT: .LBB14_6:1647; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 01648; GFX10-WAVE32-NEXT: exp null off, off, off, off done vm1649; GFX10-WAVE32-NEXT: s_endpgm1650;1651; GFX11-LABEL: cbranch_kill:1652; GFX11: ; %bb.0: ; %.entry1653; GFX11-NEXT: v_mov_b32_e32 v2, 01654; GFX11-NEXT: s_mov_b64 s[0:1], exec1655; GFX11-NEXT: image_sample_l v1, [v1, v1, v1, v2], s[0:7], s[0:3] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY1656; GFX11-NEXT: s_mov_b64 s[2:3], exec1657; GFX11-NEXT: s_waitcnt vmcnt(0)1658; GFX11-NEXT: v_cmpx_ge_f32_e32 0, v11659; GFX11-NEXT: s_xor_b64 s[2:3], exec, s[2:3]1660; GFX11-NEXT: s_cbranch_execz .LBB14_31661; GFX11-NEXT: ; %bb.1: ; %kill1662; GFX11-NEXT: s_and_not1_b64 s[0:1], s[0:1], exec1663; GFX11-NEXT: ; implicit-def: $vgpr01664; GFX11-NEXT: ; implicit-def: $vgpr11665; GFX11-NEXT: s_cbranch_scc0 .LBB14_61666; GFX11-NEXT: ; %bb.2: ; %kill1667; GFX11-NEXT: s_mov_b64 exec, 01668; GFX11-NEXT: .LBB14_3: ; %Flow1669; GFX11-NEXT: s_or_saveexec_b64 s[0:1], s[2:3]1670; GFX11-NEXT: ; implicit-def: $vgpr21671; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)1672; GFX11-NEXT: s_xor_b64 exec, exec, s[0:1]1673; GFX11-NEXT: ; %bb.4: ; %live1674; GFX11-NEXT: v_mul_f32_e32 v2, v0, v11675; GFX11-NEXT: ; %bb.5: ; %export1676; GFX11-NEXT: s_or_b64 exec, exec, s[0:1]1677; GFX11-NEXT: exp mrt0 v2, v2, v2, v2 done1678; GFX11-NEXT: s_endpgm1679; GFX11-NEXT: .LBB14_6:1680; GFX11-NEXT: s_mov_b64 exec, 01681; GFX11-NEXT: exp mrt0 off, off, off, off done1682; GFX11-NEXT: s_endpgm1683.entry:1684 %sample = call float @llvm.amdgcn.image.sample.l.2darray.f32.f32(i32 1, float %val1, float %val1, float %val1, float 0.000000e+00, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0)1685 %cond0 = fcmp ugt float %sample, 0.000000e+001686 br i1 %cond0, label %live, label %kill1687 1688kill:1689 call void @llvm.amdgcn.kill(i1 false)1690 br label %export1691 1692live:1693 %scale = fmul reassoc nnan nsz arcp contract float %val0, %sample1694 br label %export1695 1696export:1697 %proxy = phi float [ poison, %kill ], [ %scale, %live ]1698 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %proxy, float %proxy, float %proxy, float %proxy, i1 true, i1 true) #31699 ret void1700}1701 1702 1703define amdgpu_ps void @complex_loop(i32 inreg %cmpa, i32 %cmpb, i32 %cmpc) {1704; SI-LABEL: complex_loop:1705; SI: ; %bb.0: ; %.entry1706; SI-NEXT: s_cmp_lt_i32 s0, 11707; SI-NEXT: s_cbranch_scc1 .LBB15_71708; SI-NEXT: ; %bb.1: ; %.lr.ph1709; SI-NEXT: s_mov_b64 s[2:3], exec1710; SI-NEXT: s_mov_b32 s6, 01711; SI-NEXT: s_mov_b64 s[0:1], 01712; SI-NEXT: s_branch .LBB15_31713; SI-NEXT: .LBB15_2: ; %latch1714; SI-NEXT: ; in Loop: Header=BB15_3 Depth=11715; SI-NEXT: s_or_b64 exec, exec, s[4:5]1716; SI-NEXT: s_add_i32 s6, s6, 11717; SI-NEXT: v_cmp_ge_i32_e32 vcc, s6, v11718; SI-NEXT: s_or_b64 s[0:1], vcc, s[0:1]1719; SI-NEXT: v_mov_b32_e32 v2, s61720; SI-NEXT: s_andn2_b64 exec, exec, s[0:1]1721; SI-NEXT: s_cbranch_execz .LBB15_61722; SI-NEXT: .LBB15_3: ; %hdr1723; SI-NEXT: ; =>This Inner Loop Header: Depth=11724; SI-NEXT: v_cmp_gt_u32_e32 vcc, s6, v01725; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc1726; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]1727; SI-NEXT: s_cbranch_execz .LBB15_21728; SI-NEXT: ; %bb.4: ; %kill1729; SI-NEXT: ; in Loop: Header=BB15_3 Depth=11730; SI-NEXT: s_andn2_b64 s[2:3], s[2:3], exec1731; SI-NEXT: s_cbranch_scc0 .LBB15_81732; SI-NEXT: ; %bb.5: ; %kill1733; SI-NEXT: ; in Loop: Header=BB15_3 Depth=11734; SI-NEXT: s_mov_b64 exec, 01735; SI-NEXT: s_branch .LBB15_21736; SI-NEXT: .LBB15_6: ; %Flow1737; SI-NEXT: s_or_b64 exec, exec, s[0:1]1738; SI-NEXT: exp mrt0 v2, v2, v0, v0 done vm1739; SI-NEXT: s_endpgm1740; SI-NEXT: .LBB15_7:1741; SI-NEXT: v_mov_b32_e32 v2, -11742; SI-NEXT: exp mrt0 v2, v2, v0, v0 done vm1743; SI-NEXT: s_endpgm1744; SI-NEXT: .LBB15_8:1745; SI-NEXT: s_mov_b64 exec, 01746; SI-NEXT: exp null off, off, off, off done vm1747; SI-NEXT: s_endpgm1748;1749; GFX10-WAVE64-LABEL: complex_loop:1750; GFX10-WAVE64: ; %bb.0: ; %.entry1751; GFX10-WAVE64-NEXT: s_cmp_lt_i32 s0, 11752; GFX10-WAVE64-NEXT: s_cbranch_scc1 .LBB15_71753; GFX10-WAVE64-NEXT: ; %bb.1: ; %.lr.ph1754; GFX10-WAVE64-NEXT: s_mov_b64 s[2:3], exec1755; GFX10-WAVE64-NEXT: s_mov_b32 s6, 01756; GFX10-WAVE64-NEXT: s_mov_b64 s[0:1], 01757; GFX10-WAVE64-NEXT: s_branch .LBB15_31758; GFX10-WAVE64-NEXT: .LBB15_2: ; %latch1759; GFX10-WAVE64-NEXT: ; in Loop: Header=BB15_3 Depth=11760; GFX10-WAVE64-NEXT: s_or_b64 exec, exec, s[4:5]1761; GFX10-WAVE64-NEXT: s_add_i32 s6, s6, 11762; GFX10-WAVE64-NEXT: v_cmp_ge_i32_e32 vcc, s6, v11763; GFX10-WAVE64-NEXT: v_mov_b32_e32 v2, s61764; GFX10-WAVE64-NEXT: s_or_b64 s[0:1], vcc, s[0:1]1765; GFX10-WAVE64-NEXT: s_andn2_b64 exec, exec, s[0:1]1766; GFX10-WAVE64-NEXT: s_cbranch_execz .LBB15_61767; GFX10-WAVE64-NEXT: .LBB15_3: ; %hdr1768; GFX10-WAVE64-NEXT: ; =>This Inner Loop Header: Depth=11769; GFX10-WAVE64-NEXT: v_cmp_gt_u32_e32 vcc, s6, v01770; GFX10-WAVE64-NEXT: s_and_saveexec_b64 s[4:5], vcc1771; GFX10-WAVE64-NEXT: s_xor_b64 s[4:5], exec, s[4:5]1772; GFX10-WAVE64-NEXT: s_cbranch_execz .LBB15_21773; GFX10-WAVE64-NEXT: ; %bb.4: ; %kill1774; GFX10-WAVE64-NEXT: ; in Loop: Header=BB15_3 Depth=11775; GFX10-WAVE64-NEXT: s_andn2_b64 s[2:3], s[2:3], exec1776; GFX10-WAVE64-NEXT: s_cbranch_scc0 .LBB15_81777; GFX10-WAVE64-NEXT: ; %bb.5: ; %kill1778; GFX10-WAVE64-NEXT: ; in Loop: Header=BB15_3 Depth=11779; GFX10-WAVE64-NEXT: s_mov_b64 exec, 01780; GFX10-WAVE64-NEXT: s_branch .LBB15_21781; GFX10-WAVE64-NEXT: .LBB15_6: ; %Flow1782; GFX10-WAVE64-NEXT: s_or_b64 exec, exec, s[0:1]1783; GFX10-WAVE64-NEXT: exp mrt0 v2, v2, v0, v0 done vm1784; GFX10-WAVE64-NEXT: s_endpgm1785; GFX10-WAVE64-NEXT: .LBB15_7:1786; GFX10-WAVE64-NEXT: v_mov_b32_e32 v2, -11787; GFX10-WAVE64-NEXT: exp mrt0 v2, v2, v0, v0 done vm1788; GFX10-WAVE64-NEXT: s_endpgm1789; GFX10-WAVE64-NEXT: .LBB15_8:1790; GFX10-WAVE64-NEXT: s_mov_b64 exec, 01791; GFX10-WAVE64-NEXT: exp null off, off, off, off done vm1792; GFX10-WAVE64-NEXT: s_endpgm1793;1794; GFX10-WAVE32-LABEL: complex_loop:1795; GFX10-WAVE32: ; %bb.0: ; %.entry1796; GFX10-WAVE32-NEXT: s_cmp_lt_i32 s0, 11797; GFX10-WAVE32-NEXT: s_cbranch_scc1 .LBB15_71798; GFX10-WAVE32-NEXT: ; %bb.1: ; %.lr.ph1799; GFX10-WAVE32-NEXT: s_mov_b32 s1, exec_lo1800; GFX10-WAVE32-NEXT: s_mov_b32 s2, 01801; GFX10-WAVE32-NEXT: s_mov_b32 s0, 01802; GFX10-WAVE32-NEXT: s_branch .LBB15_31803; GFX10-WAVE32-NEXT: .LBB15_2: ; %latch1804; GFX10-WAVE32-NEXT: ; in Loop: Header=BB15_3 Depth=11805; GFX10-WAVE32-NEXT: s_or_b32 exec_lo, exec_lo, s31806; GFX10-WAVE32-NEXT: s_add_i32 s2, s2, 11807; GFX10-WAVE32-NEXT: v_cmp_ge_i32_e32 vcc_lo, s2, v11808; GFX10-WAVE32-NEXT: v_mov_b32_e32 v2, s21809; GFX10-WAVE32-NEXT: s_or_b32 s0, vcc_lo, s01810; GFX10-WAVE32-NEXT: s_andn2_b32 exec_lo, exec_lo, s01811; GFX10-WAVE32-NEXT: s_cbranch_execz .LBB15_61812; GFX10-WAVE32-NEXT: .LBB15_3: ; %hdr1813; GFX10-WAVE32-NEXT: ; =>This Inner Loop Header: Depth=11814; GFX10-WAVE32-NEXT: v_cmp_gt_u32_e32 vcc_lo, s2, v01815; GFX10-WAVE32-NEXT: s_and_saveexec_b32 s3, vcc_lo1816; GFX10-WAVE32-NEXT: s_xor_b32 s3, exec_lo, s31817; GFX10-WAVE32-NEXT: s_cbranch_execz .LBB15_21818; GFX10-WAVE32-NEXT: ; %bb.4: ; %kill1819; GFX10-WAVE32-NEXT: ; in Loop: Header=BB15_3 Depth=11820; GFX10-WAVE32-NEXT: s_andn2_b32 s1, s1, exec_lo1821; GFX10-WAVE32-NEXT: s_cbranch_scc0 .LBB15_81822; GFX10-WAVE32-NEXT: ; %bb.5: ; %kill1823; GFX10-WAVE32-NEXT: ; in Loop: Header=BB15_3 Depth=11824; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 01825; GFX10-WAVE32-NEXT: s_branch .LBB15_21826; GFX10-WAVE32-NEXT: .LBB15_6: ; %Flow1827; GFX10-WAVE32-NEXT: s_or_b32 exec_lo, exec_lo, s01828; GFX10-WAVE32-NEXT: exp mrt0 v2, v2, v0, v0 done vm1829; GFX10-WAVE32-NEXT: s_endpgm1830; GFX10-WAVE32-NEXT: .LBB15_7:1831; GFX10-WAVE32-NEXT: v_mov_b32_e32 v2, -11832; GFX10-WAVE32-NEXT: exp mrt0 v2, v2, v0, v0 done vm1833; GFX10-WAVE32-NEXT: s_endpgm1834; GFX10-WAVE32-NEXT: .LBB15_8:1835; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 01836; GFX10-WAVE32-NEXT: exp null off, off, off, off done vm1837; GFX10-WAVE32-NEXT: s_endpgm1838;1839; GFX11-LABEL: complex_loop:1840; GFX11: ; %bb.0: ; %.entry1841; GFX11-NEXT: s_cmp_lt_i32 s0, 11842; GFX11-NEXT: s_cbranch_scc1 .LBB15_71843; GFX11-NEXT: ; %bb.1: ; %.lr.ph1844; GFX11-NEXT: s_mov_b64 s[2:3], exec1845; GFX11-NEXT: s_mov_b32 s6, 01846; GFX11-NEXT: s_mov_b64 s[0:1], 01847; GFX11-NEXT: s_branch .LBB15_31848; GFX11-NEXT: .LBB15_2: ; %latch1849; GFX11-NEXT: ; in Loop: Header=BB15_3 Depth=11850; GFX11-NEXT: s_or_b64 exec, exec, s[4:5]1851; GFX11-NEXT: s_add_i32 s6, s6, 11852; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)1853; GFX11-NEXT: v_cmp_ge_i32_e32 vcc, s6, v11854; GFX11-NEXT: v_mov_b32_e32 v2, s61855; GFX11-NEXT: s_or_b64 s[0:1], vcc, s[0:1]1856; GFX11-NEXT: s_and_not1_b64 exec, exec, s[0:1]1857; GFX11-NEXT: s_cbranch_execz .LBB15_61858; GFX11-NEXT: .LBB15_3: ; %hdr1859; GFX11-NEXT: ; =>This Inner Loop Header: Depth=11860; GFX11-NEXT: s_mov_b64 s[4:5], exec1861; GFX11-NEXT: v_cmpx_gt_u32_e64 s6, v01862; GFX11-NEXT: s_xor_b64 s[4:5], exec, s[4:5]1863; GFX11-NEXT: s_cbranch_execz .LBB15_21864; GFX11-NEXT: ; %bb.4: ; %kill1865; GFX11-NEXT: ; in Loop: Header=BB15_3 Depth=11866; GFX11-NEXT: s_and_not1_b64 s[2:3], s[2:3], exec1867; GFX11-NEXT: s_cbranch_scc0 .LBB15_81868; GFX11-NEXT: ; %bb.5: ; %kill1869; GFX11-NEXT: ; in Loop: Header=BB15_3 Depth=11870; GFX11-NEXT: s_mov_b64 exec, 01871; GFX11-NEXT: s_branch .LBB15_21872; GFX11-NEXT: .LBB15_6: ; %Flow1873; GFX11-NEXT: s_or_b64 exec, exec, s[0:1]1874; GFX11-NEXT: exp mrt0 v2, v2, v0, v0 done1875; GFX11-NEXT: s_endpgm1876; GFX11-NEXT: .LBB15_7:1877; GFX11-NEXT: v_mov_b32_e32 v2, -11878; GFX11-NEXT: exp mrt0 v2, v2, v0, v0 done1879; GFX11-NEXT: s_endpgm1880; GFX11-NEXT: .LBB15_8:1881; GFX11-NEXT: s_mov_b64 exec, 01882; GFX11-NEXT: exp mrt0 off, off, off, off done1883; GFX11-NEXT: s_endpgm1884.entry:1885 %flaga = icmp sgt i32 %cmpa, 01886 br i1 %flaga, label %.lr.ph, label %._crit_edge1887 1888.lr.ph:1889 br label %hdr1890 1891hdr:1892 %ctr = phi i32 [ 0, %.lr.ph ], [ %ctr.next, %latch ]1893 %flagb = icmp ugt i32 %ctr, %cmpb1894 br i1 %flagb, label %kill, label %latch1895 1896kill:1897 call void @llvm.amdgcn.kill(i1 false)1898 br label %latch1899 1900latch:1901 %ctr.next = add nuw nsw i32 %ctr, 11902 %flagc = icmp slt i32 %ctr.next, %cmpc1903 br i1 %flagc, label %hdr, label %._crit_edge1904 1905._crit_edge:1906 %tmp = phi i32 [ -1, %.entry ], [ %ctr.next, %latch ]1907 %out = bitcast i32 %tmp to float1908 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %out, float %out, float poison, float poison, i1 true, i1 true)1909 ret void1910}1911 1912define void @skip_mode_switch(i32 %arg) {1913; WAVE64-LABEL: skip_mode_switch:1914; WAVE64: ; %bb.0: ; %entry1915; WAVE64-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1916; WAVE64-NEXT: v_cmp_eq_u32_e32 vcc, 0, v01917; WAVE64-NEXT: s_and_saveexec_b64 s[4:5], vcc1918; WAVE64-NEXT: s_cbranch_execz .LBB16_21919; WAVE64-NEXT: ; %bb.1: ; %bb.01920; WAVE64-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 2), 31921; WAVE64-NEXT: .LBB16_2: ; %bb.11922; WAVE64-NEXT: s_or_b64 exec, exec, s[4:5]1923; WAVE64-NEXT: s_setpc_b64 s[30:31]1924;1925; GFX10-WAVE32-LABEL: skip_mode_switch:1926; GFX10-WAVE32: ; %bb.0: ; %entry1927; GFX10-WAVE32-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1928; GFX10-WAVE32-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v01929; GFX10-WAVE32-NEXT: s_and_saveexec_b32 s4, vcc_lo1930; GFX10-WAVE32-NEXT: s_cbranch_execz .LBB16_21931; GFX10-WAVE32-NEXT: ; %bb.1: ; %bb.01932; GFX10-WAVE32-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 2), 31933; GFX10-WAVE32-NEXT: .LBB16_2: ; %bb.11934; GFX10-WAVE32-NEXT: s_or_b32 exec_lo, exec_lo, s41935; GFX10-WAVE32-NEXT: s_setpc_b64 s[30:31]1936;1937; GFX11-LABEL: skip_mode_switch:1938; GFX11: ; %bb.0: ; %entry1939; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1940; GFX11-NEXT: s_mov_b64 s[0:1], exec1941; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v01942; GFX11-NEXT: s_cbranch_execz .LBB16_21943; GFX11-NEXT: ; %bb.1: ; %bb.01944; GFX11-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 2), 31945; GFX11-NEXT: .LBB16_2: ; %bb.11946; GFX11-NEXT: s_or_b64 exec, exec, s[0:1]1947; GFX11-NEXT: s_setpc_b64 s[30:31]1948entry:1949 %cmp = icmp eq i32 %arg, 01950 br i1 %cmp, label %bb.0, label %bb.11951 1952bb.0:1953 call void @llvm.amdgcn.s.setreg(i32 2049, i32 3)1954 br label %bb.11955 1956bb.1:1957 ret void1958}1959 1960define amdgpu_ps void @scc_use_after_kill_inst(float inreg %x, i32 inreg %y) #0 {1961; SI-LABEL: scc_use_after_kill_inst:1962; SI: ; %bb.0: ; %bb1963; SI-NEXT: v_add_f32_e64 v1, s0, 1.01964; SI-NEXT: v_cmp_lt_f32_e32 vcc, 0, v11965; SI-NEXT: s_mov_b64 s[2:3], exec1966; SI-NEXT: s_cmp_lg_u32 s1, 01967; SI-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc1968; SI-NEXT: v_cmp_nlt_f32_e32 vcc, 0, v11969; SI-NEXT: s_andn2_b64 s[2:3], s[2:3], vcc1970; SI-NEXT: s_cbranch_scc0 .LBB17_61971; SI-NEXT: ; %bb.1: ; %bb1972; SI-NEXT: s_andn2_b64 exec, exec, vcc1973; SI-NEXT: s_cbranch_scc0 .LBB17_31974; SI-NEXT: ; %bb.2: ; %bb81975; SI-NEXT: s_mov_b32 s3, 0xf0001976; SI-NEXT: s_mov_b32 s2, -11977; SI-NEXT: v_mov_b32_e32 v0, 81978; SI-NEXT: buffer_store_dword v0, off, s[0:3], 01979; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)1980; SI-NEXT: v_mov_b32_e32 v0, 4.01981; SI-NEXT: .LBB17_3: ; %phibb1982; SI-NEXT: v_cmp_eq_f32_e32 vcc, 0, v01983; SI-NEXT: s_cbranch_vccz .LBB17_51984; SI-NEXT: ; %bb.4: ; %bb101985; SI-NEXT: s_mov_b32 s3, 0xf0001986; SI-NEXT: s_mov_b32 s2, -11987; SI-NEXT: v_mov_b32_e32 v0, 91988; SI-NEXT: buffer_store_dword v0, off, s[0:3], 01989; SI-NEXT: s_waitcnt vmcnt(0)1990; SI-NEXT: .LBB17_5: ; %end1991; SI-NEXT: s_endpgm1992; SI-NEXT: .LBB17_6:1993; SI-NEXT: s_mov_b64 exec, 01994; SI-NEXT: exp null off, off, off, off done vm1995; SI-NEXT: s_endpgm1996;1997; GFX10-WAVE64-LABEL: scc_use_after_kill_inst:1998; GFX10-WAVE64: ; %bb.0: ; %bb1999; GFX10-WAVE64-NEXT: v_add_f32_e64 v1, s0, 1.02000; GFX10-WAVE64-NEXT: s_mov_b64 s[2:3], exec2001; GFX10-WAVE64-NEXT: s_cmp_lg_u32 s1, 02002; GFX10-WAVE64-NEXT: v_cmp_lt_f32_e32 vcc, 0, v12003; GFX10-WAVE64-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc2004; GFX10-WAVE64-NEXT: v_cmp_nlt_f32_e32 vcc, 0, v12005; GFX10-WAVE64-NEXT: s_andn2_b64 s[2:3], s[2:3], vcc2006; GFX10-WAVE64-NEXT: s_cbranch_scc0 .LBB17_62007; GFX10-WAVE64-NEXT: ; %bb.1: ; %bb2008; GFX10-WAVE64-NEXT: s_andn2_b64 exec, exec, vcc2009; GFX10-WAVE64-NEXT: s_cbranch_scc0 .LBB17_32010; GFX10-WAVE64-NEXT: ; %bb.2: ; %bb82011; GFX10-WAVE64-NEXT: v_mov_b32_e32 v1, 82012; GFX10-WAVE64-NEXT: v_mov_b32_e32 v0, 4.02013; GFX10-WAVE64-NEXT: global_store_dword v[0:1], v1, off2014; GFX10-WAVE64-NEXT: s_waitcnt_vscnt null, 0x02015; GFX10-WAVE64-NEXT: .LBB17_3: ; %phibb2016; GFX10-WAVE64-NEXT: v_cmp_eq_f32_e32 vcc, 0, v02017; GFX10-WAVE64-NEXT: s_cbranch_vccz .LBB17_52018; GFX10-WAVE64-NEXT: ; %bb.4: ; %bb102019; GFX10-WAVE64-NEXT: v_mov_b32_e32 v0, 92020; GFX10-WAVE64-NEXT: global_store_dword v[0:1], v0, off2021; GFX10-WAVE64-NEXT: s_waitcnt_vscnt null, 0x02022; GFX10-WAVE64-NEXT: .LBB17_5: ; %end2023; GFX10-WAVE64-NEXT: s_endpgm2024; GFX10-WAVE64-NEXT: .LBB17_6:2025; GFX10-WAVE64-NEXT: s_mov_b64 exec, 02026; GFX10-WAVE64-NEXT: exp null off, off, off, off done vm2027; GFX10-WAVE64-NEXT: s_endpgm2028;2029; GFX10-WAVE32-LABEL: scc_use_after_kill_inst:2030; GFX10-WAVE32: ; %bb.0: ; %bb2031; GFX10-WAVE32-NEXT: v_add_f32_e64 v1, s0, 1.02032; GFX10-WAVE32-NEXT: s_mov_b32 s2, exec_lo2033; GFX10-WAVE32-NEXT: s_cmp_lg_u32 s1, 02034; GFX10-WAVE32-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0, v12035; GFX10-WAVE32-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc_lo2036; GFX10-WAVE32-NEXT: v_cmp_nlt_f32_e32 vcc_lo, 0, v12037; GFX10-WAVE32-NEXT: s_andn2_b32 s2, s2, vcc_lo2038; GFX10-WAVE32-NEXT: s_cbranch_scc0 .LBB17_62039; GFX10-WAVE32-NEXT: ; %bb.1: ; %bb2040; GFX10-WAVE32-NEXT: s_andn2_b32 exec_lo, exec_lo, vcc_lo2041; GFX10-WAVE32-NEXT: s_cbranch_scc0 .LBB17_32042; GFX10-WAVE32-NEXT: ; %bb.2: ; %bb82043; GFX10-WAVE32-NEXT: v_mov_b32_e32 v1, 82044; GFX10-WAVE32-NEXT: v_mov_b32_e32 v0, 4.02045; GFX10-WAVE32-NEXT: global_store_dword v[0:1], v1, off2046; GFX10-WAVE32-NEXT: s_waitcnt_vscnt null, 0x02047; GFX10-WAVE32-NEXT: .LBB17_3: ; %phibb2048; GFX10-WAVE32-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v02049; GFX10-WAVE32-NEXT: s_cbranch_vccz .LBB17_52050; GFX10-WAVE32-NEXT: ; %bb.4: ; %bb102051; GFX10-WAVE32-NEXT: v_mov_b32_e32 v0, 92052; GFX10-WAVE32-NEXT: global_store_dword v[0:1], v0, off2053; GFX10-WAVE32-NEXT: s_waitcnt_vscnt null, 0x02054; GFX10-WAVE32-NEXT: .LBB17_5: ; %end2055; GFX10-WAVE32-NEXT: s_endpgm2056; GFX10-WAVE32-NEXT: .LBB17_6:2057; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 02058; GFX10-WAVE32-NEXT: exp null off, off, off, off done vm2059; GFX10-WAVE32-NEXT: s_endpgm2060;2061; GFX11-LABEL: scc_use_after_kill_inst:2062; GFX11: ; %bb.0: ; %bb2063; GFX11-NEXT: v_add_f32_e64 v1, s0, 1.02064; GFX11-NEXT: s_mov_b64 s[2:3], exec2065; GFX11-NEXT: s_cmp_lg_u32 s1, 02066; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)2067; GFX11-NEXT: v_cmp_lt_f32_e32 vcc, 0, v12068; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc2069; GFX11-NEXT: v_cmp_nlt_f32_e32 vcc, 0, v12070; GFX11-NEXT: s_waitcnt_depctr depctr_va_vcc(0)2071; GFX11-NEXT: s_and_not1_b64 s[2:3], s[2:3], vcc2072; GFX11-NEXT: s_cbranch_scc0 .LBB17_62073; GFX11-NEXT: ; %bb.1: ; %bb2074; GFX11-NEXT: s_and_not1_b64 exec, exec, vcc2075; GFX11-NEXT: s_cbranch_scc0 .LBB17_32076; GFX11-NEXT: ; %bb.2: ; %bb82077; GFX11-NEXT: v_mov_b32_e32 v1, 82078; GFX11-NEXT: v_mov_b32_e32 v0, 4.02079; GFX11-NEXT: global_store_b32 v[0:1], v1, off dlc2080; GFX11-NEXT: s_waitcnt_vscnt null, 0x02081; GFX11-NEXT: .LBB17_3: ; %phibb2082; GFX11-NEXT: v_cmp_eq_f32_e32 vcc, 0, v02083; GFX11-NEXT: s_cbranch_vccz .LBB17_52084; GFX11-NEXT: ; %bb.4: ; %bb102085; GFX11-NEXT: v_mov_b32_e32 v0, 92086; GFX11-NEXT: global_store_b32 v[0:1], v0, off dlc2087; GFX11-NEXT: s_waitcnt_vscnt null, 0x02088; GFX11-NEXT: .LBB17_5: ; %end2089; GFX11-NEXT: s_endpgm2090; GFX11-NEXT: .LBB17_6:2091; GFX11-NEXT: s_mov_b64 exec, 02092; GFX11-NEXT: exp mrt0 off, off, off, off done2093; GFX11-NEXT: s_endpgm2094bb:2095 %tmp = fadd float %x, 1.000000e+002096 %tmp1 = fcmp olt float 0.000000e+00, %tmp2097 %tmp2 = select i1 %tmp1, float -1.000000e+00, float 0.000000e+002098 %cmp.tmp2 = fcmp olt float %tmp2, 0.000000e+002099 %uniform.cond = icmp eq i32 %y, 02100 call void @llvm.amdgcn.kill(i1 %cmp.tmp2)2101 br i1 %uniform.cond, label %phibb, label %bb82102 2103phibb: ; preds = %bb8, %bb2104 %tmp5 = phi float [ %tmp2, %bb ], [ 4.000000e+00, %bb8 ]2105 %tmp6 = fcmp oeq float %tmp5, 0.000000e+002106 br i1 %tmp6, label %bb10, label %end2107 2108bb8: ; preds = %bb2109 store volatile i32 8, ptr addrspace(1) poison, align 42110 br label %phibb2111 2112bb10: ; preds = %phibb2113 store volatile i32 9, ptr addrspace(1) poison, align 42114 br label %end2115 2116end: ; preds = %bb10, %phibb2117 ret void2118}2119 2120declare void @llvm.amdgcn.exp.f32(i32 immarg, i32 immarg, float, float, float, float, i1 immarg, i1 immarg) #32121declare float @llvm.amdgcn.image.sample.l.2darray.f32.f32(i32 immarg, float, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #12122declare <4 x float> @llvm.amdgcn.image.sample.c.1d.v4f32.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #12123declare void @llvm.amdgcn.kill(i1) #02124 2125declare void @llvm.amdgcn.s.setreg(i32 immarg, i32)2126 2127attributes #0 = { nounwind }2128attributes #1 = { nounwind readonly }2129attributes #2 = { nounwind readnone speculatable }2130attributes #3 = { inaccessiblememonly nounwind writeonly }2131