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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 < %s | FileCheck -enable-var-scope -check-prefixes=GFX942 %s3 4 5define protected amdgpu_kernel void @test(ptr addrspace(1) %in, ptr addrspace(1) %out) #0 {6; GFX942-LABEL: test:7; GFX942: ; %bb.0: ; %entry8; GFX942-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x09; GFX942-NEXT: v_mov_b32_e32 v0, 010; GFX942-NEXT: v_mov_b32_e32 v2, v011; GFX942-NEXT: v_mov_b32_e32 v3, v012; GFX942-NEXT: v_mov_b32_e32 v1, v013; GFX942-NEXT: s_waitcnt lgkmcnt(0)14; GFX942-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x015; GFX942-NEXT: v_mov_b64_e32 v[12:13], v[2:3]16; GFX942-NEXT: v_mov_b64_e32 v[10:11], v[0:1]17; GFX942-NEXT: s_waitcnt lgkmcnt(0)18; GFX942-NEXT: v_mov_b32_e32 v8, s419; GFX942-NEXT: v_mov_b32_e32 v9, s520; GFX942-NEXT: v_mov_b32_e32 v4, s621; GFX942-NEXT: v_mov_b32_e32 v5, s722; GFX942-NEXT: v_mov_b32_e32 v6, s723; GFX942-NEXT: v_mov_b32_e32 v7, s724; GFX942-NEXT: s_nop 125; GFX942-NEXT: v_smfmac_i32_16x16x64_i8 v[10:13], v[8:9], v[4:7], v926; GFX942-NEXT: s_nop 627; GFX942-NEXT: global_store_dword v0, v13, s[2:3] offset:1228; GFX942-NEXT: s_endpgm29entry:30 %arrayidx = getelementptr inbounds i32, ptr addrspace(1) %in, i64 031 %arrayidx1 = getelementptr inbounds i32, ptr addrspace(1) %in, i64 132 %arrayidx2 = getelementptr inbounds i32, ptr addrspace(1) %in, i64 233 %arrayidx3 = getelementptr inbounds i32, ptr addrspace(1) %in, i64 334 %0 = load i32, ptr addrspace(1) %arrayidx35 %1 = load i32, ptr addrspace(1) %arrayidx136 %2 = load i32, ptr addrspace(1) %arrayidx237 %3 = load i32, ptr addrspace(1) %arrayidx338 %src1.0 = insertelement <2 x i32> poison, i32 %0, i64 039 %src1 = insertelement <2 x i32> %src1.0, i32 %1, i64 140 %src2.0 = insertelement <4 x i32> poison, i32 %2, i64 041 %src2.1 = insertelement <4 x i32> %src2.0, i32 %3, i64 142 %src2.2 = insertelement <4 x i32> %src2.1, i32 %3, i64 243 %src2 = insertelement <4 x i32> %src2.2, i32 %3, i64 344 %4 = tail call <4 x i32> @llvm.amdgcn.smfmac.i32.16x16x64.i8(<2 x i32> %src1, <4 x i32> %src2, <4 x i32> zeroinitializer, i32 %1, i32 0, i32 0)45 %vecext = extractelement <4 x i32> %4, i64 046 %vecext.1 = extractelement <4 x i32> %4, i64 147 %vecext.2 = extractelement <4 x i32> %4, i64 248 %vecext.3 = extractelement <4 x i32> %4, i64 349 %arrayidx4 = getelementptr inbounds i32, ptr addrspace(1) %out, i64 350 store i32 %vecext.3, ptr addrspace(1) %arrayidx451 ret void52}53declare <4 x i32> @llvm.amdgcn.smfmac.i32.16x16x64.i8(<2 x i32>, <4 x i32>, <4 x i32>, i32, i32 immarg, i32 immarg)54 55attributes #0 = { "amdgpu-agpr-alloc"="0" }56