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1; RUN: llc -mtriple=amdgcn -mcpu=verde < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SIVI,FUNC %s2; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SIVI,FUNC %s3; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9,FUNC %s4; RUN: llc -mtriple=r600 -mcpu=cypress < %s | FileCheck -check-prefixes=EG,FUNC %s5 6; FUNC-LABEL: {{^}}s_abs_i32:7; GCN: s_abs_i328; GCN: s_add_i329 10; EG: MAX_INT11define amdgpu_kernel void @s_abs_i32(ptr addrspace(1) %out, i32 %val) nounwind {12 %neg = sub i32 0, %val13 %cond = icmp sgt i32 %val, %neg14 %res = select i1 %cond, i32 %val, i32 %neg15 %res2 = add i32 %res, 216 store i32 %res2, ptr addrspace(1) %out, align 417 ret void18}19 20; FUNC-LABEL: {{^}}v_abs_i32:21; SIVI: v_sub_{{i|u}}32_e32 [[NEG:v[0-9]+]], vcc, 0, [[SRC:v[0-9]+]]22; GFX9: v_sub_u32_e32 [[NEG:v[0-9]+]], 0, [[SRC:v[0-9]+]]23 24; GCN: v_max_i32_e32 {{v[0-9]+}}, [[SRC]], [[NEG]]25 26; SIVI: v_add_{{i|u}}32_e32 v{{[0-9]+}}, vcc27; GFX9: v_add_u32_e32 v{{[0-9]+}}, 228 29; EG: MAX_INT30define amdgpu_kernel void @v_abs_i32(ptr addrspace(1) %out, ptr addrspace(1) %src) nounwind {31 %tid = call i32 @llvm.amdgcn.workitem.id.x()32 %gep.in = getelementptr inbounds i32, ptr addrspace(1) %src, i32 %tid33 %val = load i32, ptr addrspace(1) %gep.in, align 434 %neg = sub i32 0, %val35 %cond = icmp sgt i32 %val, %neg36 %res = select i1 %cond, i32 %val, i32 %neg37 %res2 = add i32 %res, 238 store i32 %res2, ptr addrspace(1) %out, align 439 ret void40}41 42; GCN-LABEL: {{^}}v_abs_i32_repeat_user:43; SIVI: v_sub_{{i|u}}32_e32 [[NEG:v[0-9]+]], vcc, 0, [[SRC:v[0-9]+]]44; GFX9: v_sub_u32_e32 [[NEG:v[0-9]+]], 0, [[SRC:v[0-9]+]]45; GCN: v_max_i32_e32 [[MAX:v[0-9]+]], [[SRC]], [[NEG]]46; GCN: v_mul_lo_u32 v{{[0-9]+}}, [[MAX]], [[MAX]]47define amdgpu_kernel void @v_abs_i32_repeat_user(ptr addrspace(1) %out, ptr addrspace(1) %src) nounwind {48 %tid = call i32 @llvm.amdgcn.workitem.id.x()49 %gep.in = getelementptr inbounds i32, ptr addrspace(1) %src, i32 %tid50 %val = load i32, ptr addrspace(1) %gep.in, align 451 %neg = sub i32 0, %val52 %cond = icmp sgt i32 %val, %neg53 %res = select i1 %cond, i32 %val, i32 %neg54 %mul = mul i32 %res, %res55 store i32 %mul, ptr addrspace(1) %out, align 456 ret void57}58 59; FUNC-LABEL: {{^}}s_abs_v2i32:60; GCN: s_abs_i3261; GCN: s_abs_i3262; GCN: s_add_i3263; GCN: s_add_i3264 65; EG: MAX_INT66; EG: MAX_INT67define amdgpu_kernel void @s_abs_v2i32(ptr addrspace(1) %out, <2 x i32> %val) nounwind {68 %z0 = insertelement <2 x i32> poison, i32 0, i32 069 %z1 = insertelement <2 x i32> %z0, i32 0, i32 170 %t0 = insertelement <2 x i32> poison, i32 2, i32 071 %t1 = insertelement <2 x i32> %t0, i32 2, i32 172 %neg = sub <2 x i32> %z1, %val73 %cond = icmp sgt <2 x i32> %val, %neg74 %res = select <2 x i1> %cond, <2 x i32> %val, <2 x i32> %neg75 %res2 = add <2 x i32> %res, %t176 store <2 x i32> %res2, ptr addrspace(1) %out, align 477 ret void78}79 80; FUNC-LABEL: {{^}}v_abs_v2i32:81; SIVI-DAG: v_sub_{{i|u}}32_e32 [[NEG0:v[0-9]+]], vcc, 0, [[SRC0:v[0-9]+]]82; SIVI-DAG: v_sub_{{i|u}}32_e32 [[NEG1:v[0-9]+]], vcc, 0, [[SRC1:v[0-9]+]]83 84; GFX9-DAG: v_sub_u32_e32 [[NEG0:v[0-9]+]], 0, [[SRC0:v[0-9]+]]85; GFX9-DAG: v_sub_u32_e32 [[NEG1:v[0-9]+]], 0, [[SRC1:v[0-9]+]]86 87; GCN-DAG: v_max_i32_e32 {{v[0-9]+}}, [[SRC0]], [[NEG0]]88; GCN-DAG: v_max_i32_e32 {{v[0-9]+}}, [[SRC1]], [[NEG1]]89 90; SIVI: v_add_{{i|u}}32_e32 v{{[0-9]+}}, vcc91; SIVI: v_add_{{i|u}}32_e32 v{{[0-9]+}}, vcc92 93; GFX9: v_add_u32_e32 v{{[0-9]+}}, 2,94; GFX9: v_add_u32_e32 v{{[0-9]+}}, 2,95 96; EG: MAX_INT97; EG: MAX_INT98define amdgpu_kernel void @v_abs_v2i32(ptr addrspace(1) %out, ptr addrspace(1) %src) nounwind {99 %z0 = insertelement <2 x i32> poison, i32 0, i32 0100 %z1 = insertelement <2 x i32> %z0, i32 0, i32 1101 %t0 = insertelement <2 x i32> poison, i32 2, i32 0102 %t1 = insertelement <2 x i32> %t0, i32 2, i32 1103 %tid = call i32 @llvm.amdgcn.workitem.id.x()104 %gep.in = getelementptr inbounds <2 x i32>, ptr addrspace(1) %src, i32 %tid105 %val = load <2 x i32>, ptr addrspace(1) %gep.in, align 4106 %neg = sub <2 x i32> %z1, %val107 %cond = icmp sgt <2 x i32> %val, %neg108 %res = select <2 x i1> %cond, <2 x i32> %val, <2 x i32> %neg109 %res2 = add <2 x i32> %res, %t1110 store <2 x i32> %res2, ptr addrspace(1) %out, align 4111 ret void112}113 114; FUNC-LABEL: {{^}}s_abs_v4i32:115; TODO: this should use s_abs_i32116; GCN: s_abs_i32117; GCN: s_abs_i32118; GCN: s_abs_i32119; GCN: s_abs_i32120 121; GCN: s_add_i32122; GCN: s_add_i32123; GCN: s_add_i32124; GCN: s_add_i32125 126; EG: MAX_INT127; EG: MAX_INT128; EG: MAX_INT129; EG: MAX_INT130define amdgpu_kernel void @s_abs_v4i32(ptr addrspace(1) %out, <4 x i32> %val) nounwind {131 %z0 = insertelement <4 x i32> poison, i32 0, i32 0132 %z1 = insertelement <4 x i32> %z0, i32 0, i32 1133 %z2 = insertelement <4 x i32> %z1, i32 0, i32 2134 %z3 = insertelement <4 x i32> %z2, i32 0, i32 3135 %t0 = insertelement <4 x i32> poison, i32 2, i32 0136 %t1 = insertelement <4 x i32> %t0, i32 2, i32 1137 %t2 = insertelement <4 x i32> %t1, i32 2, i32 2138 %t3 = insertelement <4 x i32> %t2, i32 2, i32 3139 %neg = sub <4 x i32> %z3, %val140 %cond = icmp sgt <4 x i32> %val, %neg141 %res = select <4 x i1> %cond, <4 x i32> %val, <4 x i32> %neg142 %res2 = add <4 x i32> %res, %t3143 store <4 x i32> %res2, ptr addrspace(1) %out, align 4144 ret void145}146 147; FUNC-LABEL: {{^}}v_abs_v4i32:148 149; SIVI-DAG: v_sub_{{i|u}}32_e32 [[NEG0:v[0-9]+]], vcc, 0, [[SRC0:v[0-9]+]]150; SIVI-DAG: v_sub_{{i|u}}32_e32 [[NEG1:v[0-9]+]], vcc, 0, [[SRC1:v[0-9]+]]151; SIVI-DAG: v_sub_{{i|u}}32_e32 [[NEG2:v[0-9]+]], vcc, 0, [[SRC2:v[0-9]+]]152; SIVI-DAG: v_sub_{{i|u}}32_e32 [[NEG3:v[0-9]+]], vcc, 0, [[SRC3:v[0-9]+]]153 154; GFX9-DAG: v_sub_u32_e32 [[NEG0:v[0-9]+]], 0, [[SRC0:v[0-9]+]]155; GFX9-DAG: v_sub_u32_e32 [[NEG1:v[0-9]+]], 0, [[SRC1:v[0-9]+]]156; GFX9-DAG: v_sub_u32_e32 [[NEG2:v[0-9]+]], 0, [[SRC2:v[0-9]+]]157; GFX9-DAG: v_sub_u32_e32 [[NEG3:v[0-9]+]], 0, [[SRC3:v[0-9]+]]158 159; GCN-DAG: v_max_i32_e32 {{v[0-9]+}}, [[SRC0]], [[NEG0]]160; GCN-DAG: v_max_i32_e32 {{v[0-9]+}}, [[SRC1]], [[NEG1]]161; GCN-DAG: v_max_i32_e32 {{v[0-9]+}}, [[SRC2]], [[NEG2]]162; GCN-DAG: v_max_i32_e32 {{v[0-9]+}}, [[SRC3]], [[NEG3]]163 164; SIVI: v_add_{{i|u}}32_e32 v{{[0-9]+}}, vcc,165; SIVI: v_add_{{i|u}}32_e32 v{{[0-9]+}}, vcc,166; SIVI: v_add_{{i|u}}32_e32 v{{[0-9]+}}, vcc,167; SIVI: v_add_{{i|u}}32_e32 v{{[0-9]+}}, vcc,168 169; GFX9: v_add_u32_e32 v{{[0-9]+}}, 2,170; GFX9: v_add_u32_e32 v{{[0-9]+}}, 2,171; GFX9: v_add_u32_e32 v{{[0-9]+}}, 2,172; GFX9: v_add_u32_e32 v{{[0-9]+}}, 2,173 174; EG: MAX_INT175; EG: MAX_INT176; EG: MAX_INT177; EG: MAX_INT178define amdgpu_kernel void @v_abs_v4i32(ptr addrspace(1) %out, ptr addrspace(1) %src) nounwind {179 %z0 = insertelement <4 x i32> poison, i32 0, i32 0180 %z1 = insertelement <4 x i32> %z0, i32 0, i32 1181 %z2 = insertelement <4 x i32> %z1, i32 0, i32 2182 %z3 = insertelement <4 x i32> %z2, i32 0, i32 3183 %t0 = insertelement <4 x i32> poison, i32 2, i32 0184 %t1 = insertelement <4 x i32> %t0, i32 2, i32 1185 %t2 = insertelement <4 x i32> %t1, i32 2, i32 2186 %t3 = insertelement <4 x i32> %t2, i32 2, i32 3187 %tid = call i32 @llvm.amdgcn.workitem.id.x()188 %gep.in = getelementptr inbounds <4 x i32>, ptr addrspace(1) %src, i32 %tid189 %val = load <4 x i32>, ptr addrspace(1) %gep.in, align 4190 %neg = sub <4 x i32> %z3, %val191 %cond = icmp sgt <4 x i32> %val, %neg192 %res = select <4 x i1> %cond, <4 x i32> %val, <4 x i32> %neg193 %res2 = add <4 x i32> %res, %t3194 store <4 x i32> %res2, ptr addrspace(1) %out, align 4195 ret void196}197 198; FUNC-LABEL: {{^}}s_min_max_i32:199; GCN: s_load_dword [[VAL0:s[0-9]+]]200; GCN: s_load_dword [[VAL1:s[0-9]+]]201 202; GCN-DAG: s_min_i32 s{{[0-9]+}}, [[VAL0]], [[VAL1]]203; GCN-DAG: s_max_i32 s{{[0-9]+}}, [[VAL0]], [[VAL1]]204define amdgpu_kernel void @s_min_max_i32(ptr addrspace(1) %out0, ptr addrspace(1) %out1, [8 x i32], i32 %val0, [8 x i32], i32 %val1) nounwind {205 %cond0 = icmp sgt i32 %val0, %val1206 %sel0 = select i1 %cond0, i32 %val0, i32 %val1207 %sel1 = select i1 %cond0, i32 %val1, i32 %val0208 209 store volatile i32 %sel0, ptr addrspace(1) %out0, align 4210 store volatile i32 %sel1, ptr addrspace(1) %out1, align 4211 ret void212}213 214; FUNC-LABEL: {{^}}v_min_max_i32:215; GCN: {{buffer|flat|global}}_load_dword [[VAL0:v[0-9]+]]216; GCN: {{buffer|flat|global}}_load_dword [[VAL1:v[0-9]+]]217 218; GCN-DAG: v_min_i32_e32 v{{[0-9]+}}, [[VAL0]], [[VAL1]]219; GCN-DAG: v_max_i32_e32 v{{[0-9]+}}, [[VAL0]], [[VAL1]]220define amdgpu_kernel void @v_min_max_i32(ptr addrspace(1) %out0, ptr addrspace(1) %out1, ptr addrspace(1) %ptr0, ptr addrspace(1) %ptr1) nounwind {221 %val0 = load volatile i32, ptr addrspace(1) %ptr0222 %val1 = load volatile i32, ptr addrspace(1) %ptr1223 224 %cond0 = icmp sgt i32 %val0, %val1225 %sel0 = select i1 %cond0, i32 %val0, i32 %val1226 %sel1 = select i1 %cond0, i32 %val1, i32 %val0227 228 store volatile i32 %sel0, ptr addrspace(1) %out0, align 4229 store volatile i32 %sel1, ptr addrspace(1) %out1, align 4230 ret void231}232 233; FUNC-LABEL: {{^}}s_min_max_v4i32:234; GCN-DAG: s_min_i32235; GCN-DAG: s_min_i32236; GCN-DAG: s_min_i32237; GCN-DAG: s_min_i32238; GCN-DAG: s_max_i32239; GCN-DAG: s_max_i32240; GCN-DAG: s_max_i32241; GCN-DAG: s_max_i32242define amdgpu_kernel void @s_min_max_v4i32(ptr addrspace(1) %out0, ptr addrspace(1) %out1, <4 x i32> %val0, <4 x i32> %val1) nounwind {243 %cond0 = icmp sgt <4 x i32> %val0, %val1244 %sel0 = select <4 x i1> %cond0, <4 x i32> %val0, <4 x i32> %val1245 %sel1 = select <4 x i1> %cond0, <4 x i32> %val1, <4 x i32> %val0246 247 store volatile <4 x i32> %sel0, ptr addrspace(1) %out0, align 4248 store volatile <4 x i32> %sel1, ptr addrspace(1) %out1, align 4249 ret void250}251 252; FUNC-LABEL: {{^}}v_min_max_i32_user:253; GCN: v_cmp_gt_i32_e32254; GCN-DAG: v_cndmask_b32_e32255; GCN-DAG: v_cndmask_b32_e32256; GCN-DAG: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, vcc257define amdgpu_kernel void @v_min_max_i32_user(ptr addrspace(1) %out0, ptr addrspace(1) %out1, ptr addrspace(1) %ptr0, ptr addrspace(1) %ptr1) nounwind {258 %val0 = load volatile i32, ptr addrspace(1) %ptr0259 %val1 = load volatile i32, ptr addrspace(1) %ptr1260 261 %cond0 = icmp sgt i32 %val0, %val1262 %sel0 = select i1 %cond0, i32 %val0, i32 %val1263 %sel1 = select i1 %cond0, i32 %val1, i32 %val0264 265 store volatile i32 %sel0, ptr addrspace(1) %out0, align 4266 store volatile i32 %sel1, ptr addrspace(1) %out1, align 4267 store volatile i1 %cond0, ptr addrspace(1) poison268 ret void269}270 271declare i32 @llvm.amdgcn.workitem.id.x() #0272 273attributes #0 = { nounwind readnone }274attributes #1 = { nounwind }275