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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s3; RUN: llc -mtriple=amdgcn -mcpu=tonga< %s | FileCheck -check-prefix=VI %s4; RUN: llc -mtriple=amdgcn -mcpu=bonaire < %s | FileCheck -check-prefix=CI %s5 6 7define amdgpu_kernel void @s_abs_v2i16(ptr addrspace(1) %out, <2 x i16> %val) #0 {8; GFX9-LABEL: s_abs_v2i16:9; GFX9: ; %bb.0:10; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c11; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2412; GFX9-NEXT: v_mov_b32_e32 v0, 013; GFX9-NEXT: s_waitcnt lgkmcnt(0)14; GFX9-NEXT: v_pk_sub_i16 v1, 0, s215; GFX9-NEXT: v_pk_max_i16 v1, s2, v116; GFX9-NEXT: v_pk_add_u16 v1, v1, 2 op_sel_hi:[1,0]17; GFX9-NEXT: global_store_dword v0, v1, s[0:1]18; GFX9-NEXT: s_endpgm19;20; VI-LABEL: s_abs_v2i16:21; VI: ; %bb.0:22; VI-NEXT: s_load_dword s2, s[4:5], 0x2c23; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2424; VI-NEXT: s_waitcnt lgkmcnt(0)25; VI-NEXT: s_sub_i32 s3, 0, s226; VI-NEXT: s_lshr_b32 s4, s2, 1627; VI-NEXT: s_ashr_i32 s5, s2, 1628; VI-NEXT: s_sub_i32 s4, 0, s429; VI-NEXT: s_sext_i32_i16 s3, s330; VI-NEXT: s_sext_i32_i16 s2, s231; VI-NEXT: s_sext_i32_i16 s4, s432; VI-NEXT: s_max_i32 s2, s2, s333; VI-NEXT: s_max_i32 s4, s5, s434; VI-NEXT: s_add_i32 s2, s2, 235; VI-NEXT: s_lshl_b32 s3, s4, 1636; VI-NEXT: s_and_b32 s2, s2, 0xffff37; VI-NEXT: s_or_b32 s2, s3, s238; VI-NEXT: s_add_i32 s2, s2, 0x2000039; VI-NEXT: v_mov_b32_e32 v0, s040; VI-NEXT: v_mov_b32_e32 v1, s141; VI-NEXT: v_mov_b32_e32 v2, s242; VI-NEXT: flat_store_dword v[0:1], v243; VI-NEXT: s_endpgm44;45; CI-LABEL: s_abs_v2i16:46; CI: ; %bb.0:47; CI-NEXT: s_load_dword s6, s[4:5], 0xb48; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x949; CI-NEXT: s_mov_b32 s3, 0xf00050; CI-NEXT: s_mov_b32 s2, -151; CI-NEXT: s_waitcnt lgkmcnt(0)52; CI-NEXT: s_lshr_b32 s5, s6, 1653; CI-NEXT: s_ashr_i32 s4, s6, 1654; CI-NEXT: s_sext_i32_i16 s7, s655; CI-NEXT: s_sub_i32 s6, 0, s656; CI-NEXT: s_sub_i32 s5, 0, s557; CI-NEXT: s_sext_i32_i16 s6, s658; CI-NEXT: s_sext_i32_i16 s5, s559; CI-NEXT: s_max_i32 s4, s4, s560; CI-NEXT: s_max_i32 s5, s7, s661; CI-NEXT: s_add_i32 s5, s5, 262; CI-NEXT: s_lshl_b32 s4, s4, 1663; CI-NEXT: s_and_b32 s5, s5, 0xffff64; CI-NEXT: s_or_b32 s4, s4, s565; CI-NEXT: s_add_i32 s4, s4, 0x2000066; CI-NEXT: v_mov_b32_e32 v0, s467; CI-NEXT: buffer_store_dword v0, off, s[0:3], 068; CI-NEXT: s_endpgm69 %neg = sub <2 x i16> zeroinitializer, %val70 %cond = icmp sgt <2 x i16> %val, %neg71 %res = select <2 x i1> %cond, <2 x i16> %val, <2 x i16> %neg72 %res2 = add <2 x i16> %res, <i16 2, i16 2>73 store <2 x i16> %res2, ptr addrspace(1) %out, align 474 ret void75}76 77define amdgpu_kernel void @v_abs_v2i16(ptr addrspace(1) %out, ptr addrspace(1) %src) #0 {78; GFX9-LABEL: v_abs_v2i16:79; GFX9: ; %bb.0:80; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2481; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v082; GFX9-NEXT: s_waitcnt lgkmcnt(0)83; GFX9-NEXT: global_load_dword v1, v0, s[2:3]84; GFX9-NEXT: s_waitcnt vmcnt(0)85; GFX9-NEXT: v_pk_sub_i16 v2, 0, v186; GFX9-NEXT: v_pk_max_i16 v1, v1, v287; GFX9-NEXT: v_pk_add_u16 v1, v1, 2 op_sel_hi:[1,0]88; GFX9-NEXT: global_store_dword v0, v1, s[0:1]89; GFX9-NEXT: s_endpgm90;91; VI-LABEL: v_abs_v2i16:92; VI: ; %bb.0:93; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2494; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v095; VI-NEXT: v_mov_b32_e32 v4, 096; VI-NEXT: v_mov_b32_e32 v5, 297; VI-NEXT: s_waitcnt lgkmcnt(0)98; VI-NEXT: v_mov_b32_e32 v1, s399; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2100; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc101; VI-NEXT: flat_load_dword v3, v[0:1]102; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2103; VI-NEXT: v_mov_b32_e32 v1, s1104; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc105; VI-NEXT: s_waitcnt vmcnt(0)106; VI-NEXT: v_sub_u16_e32 v2, 0, v3107; VI-NEXT: v_sub_u16_sdwa v4, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1108; VI-NEXT: v_max_i16_sdwa v4, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD109; VI-NEXT: v_max_i16_e32 v2, v3, v2110; VI-NEXT: v_add_u16_e32 v2, 2, v2111; VI-NEXT: v_add_u16_sdwa v3, v4, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD112; VI-NEXT: v_or_b32_e32 v2, v2, v3113; VI-NEXT: flat_store_dword v[0:1], v2114; VI-NEXT: s_endpgm115;116; CI-LABEL: v_abs_v2i16:117; CI: ; %bb.0:118; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9119; CI-NEXT: s_mov_b32 s7, 0xf000120; CI-NEXT: s_mov_b32 s6, 0121; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0122; CI-NEXT: v_mov_b32_e32 v1, 0123; CI-NEXT: s_waitcnt lgkmcnt(0)124; CI-NEXT: s_mov_b64 s[4:5], s[2:3]125; CI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64126; CI-NEXT: s_mov_b64 s[2:3], s[6:7]127; CI-NEXT: s_waitcnt vmcnt(0)128; CI-NEXT: v_bfe_i32 v3, v2, 0, 16129; CI-NEXT: v_ashrrev_i32_e32 v4, 16, v2130; CI-NEXT: v_lshrrev_b32_e32 v5, 16, v2131; CI-NEXT: v_sub_i32_e32 v2, vcc, 0, v2132; CI-NEXT: v_bfe_i32 v2, v2, 0, 16133; CI-NEXT: v_sub_i32_e32 v5, vcc, 0, v5134; CI-NEXT: v_bfe_i32 v5, v5, 0, 16135; CI-NEXT: v_max_i32_e32 v2, v3, v2136; CI-NEXT: v_max_i32_e32 v3, v4, v5137; CI-NEXT: v_add_i32_e32 v2, vcc, 2, v2138; CI-NEXT: v_and_b32_e32 v2, 0xffff, v2139; CI-NEXT: v_lshlrev_b32_e32 v3, 16, v3140; CI-NEXT: v_or_b32_e32 v2, v3, v2141; CI-NEXT: v_add_i32_e32 v2, vcc, 0x20000, v2142; CI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64143; CI-NEXT: s_endpgm144 %tid = call i32 @llvm.amdgcn.workitem.id.x()145 %gep.in = getelementptr inbounds <2 x i16>, ptr addrspace(1) %src, i32 %tid146 %gep.out = getelementptr inbounds <2 x i16>, ptr addrspace(1) %out, i32 %tid147 %val = load <2 x i16>, ptr addrspace(1) %gep.in, align 4148 %neg = sub <2 x i16> zeroinitializer, %val149 %cond = icmp sgt <2 x i16> %val, %neg150 %res = select <2 x i1> %cond, <2 x i16> %val, <2 x i16> %neg151 %res2 = add <2 x i16> %res, <i16 2, i16 2>152 store <2 x i16> %res2, ptr addrspace(1) %gep.out, align 4153 ret void154}155 156define amdgpu_kernel void @s_abs_v2i16_2(ptr addrspace(1) %out, <2 x i16> %val) #0 {157; GFX9-LABEL: s_abs_v2i16_2:158; GFX9: ; %bb.0:159; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c160; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24161; GFX9-NEXT: v_mov_b32_e32 v0, 0162; GFX9-NEXT: s_waitcnt lgkmcnt(0)163; GFX9-NEXT: v_pk_sub_i16 v1, 0, s2164; GFX9-NEXT: v_pk_max_i16 v1, s2, v1165; GFX9-NEXT: v_pk_add_u16 v1, v1, 2 op_sel_hi:[1,0]166; GFX9-NEXT: global_store_dword v0, v1, s[0:1]167; GFX9-NEXT: s_endpgm168;169; VI-LABEL: s_abs_v2i16_2:170; VI: ; %bb.0:171; VI-NEXT: s_load_dword s2, s[4:5], 0x2c172; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24173; VI-NEXT: s_waitcnt lgkmcnt(0)174; VI-NEXT: s_sub_i32 s3, 0, s2175; VI-NEXT: s_lshr_b32 s4, s2, 16176; VI-NEXT: s_ashr_i32 s5, s2, 16177; VI-NEXT: s_sub_i32 s4, 0, s4178; VI-NEXT: s_sext_i32_i16 s3, s3179; VI-NEXT: s_sext_i32_i16 s2, s2180; VI-NEXT: s_sext_i32_i16 s4, s4181; VI-NEXT: s_max_i32 s2, s2, s3182; VI-NEXT: s_max_i32 s4, s5, s4183; VI-NEXT: s_add_i32 s2, s2, 2184; VI-NEXT: s_lshl_b32 s3, s4, 16185; VI-NEXT: s_and_b32 s2, s2, 0xffff186; VI-NEXT: s_or_b32 s2, s3, s2187; VI-NEXT: s_add_i32 s2, s2, 0x20000188; VI-NEXT: v_mov_b32_e32 v0, s0189; VI-NEXT: v_mov_b32_e32 v1, s1190; VI-NEXT: v_mov_b32_e32 v2, s2191; VI-NEXT: flat_store_dword v[0:1], v2192; VI-NEXT: s_endpgm193;194; CI-LABEL: s_abs_v2i16_2:195; CI: ; %bb.0:196; CI-NEXT: s_load_dword s6, s[4:5], 0xb197; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9198; CI-NEXT: s_mov_b32 s3, 0xf000199; CI-NEXT: s_mov_b32 s2, -1200; CI-NEXT: s_waitcnt lgkmcnt(0)201; CI-NEXT: s_lshr_b32 s5, s6, 16202; CI-NEXT: s_ashr_i32 s4, s6, 16203; CI-NEXT: s_sext_i32_i16 s7, s6204; CI-NEXT: s_sub_i32 s6, 0, s6205; CI-NEXT: s_sub_i32 s5, 0, s5206; CI-NEXT: s_sext_i32_i16 s6, s6207; CI-NEXT: s_sext_i32_i16 s5, s5208; CI-NEXT: s_max_i32 s4, s4, s5209; CI-NEXT: s_max_i32 s5, s7, s6210; CI-NEXT: s_add_i32 s5, s5, 2211; CI-NEXT: s_lshl_b32 s4, s4, 16212; CI-NEXT: s_and_b32 s5, s5, 0xffff213; CI-NEXT: s_or_b32 s4, s4, s5214; CI-NEXT: s_add_i32 s4, s4, 0x20000215; CI-NEXT: v_mov_b32_e32 v0, s4216; CI-NEXT: buffer_store_dword v0, off, s[0:3], 0217; CI-NEXT: s_endpgm218 %z0 = insertelement <2 x i16> poison, i16 0, i16 0219 %z1 = insertelement <2 x i16> %z0, i16 0, i16 1220 %t0 = insertelement <2 x i16> poison, i16 2, i16 0221 %t1 = insertelement <2 x i16> %t0, i16 2, i16 1222 %neg = sub <2 x i16> %z1, %val223 %cond = icmp sgt <2 x i16> %val, %neg224 %res = select <2 x i1> %cond, <2 x i16> %val, <2 x i16> %neg225 %res2 = add <2 x i16> %res, %t1226 store <2 x i16> %res2, ptr addrspace(1) %out, align 4227 ret void228}229 230define amdgpu_kernel void @v_abs_v2i16_2(ptr addrspace(1) %out, ptr addrspace(1) %src) #0 {231; GFX9-LABEL: v_abs_v2i16_2:232; GFX9: ; %bb.0:233; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24234; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0235; GFX9-NEXT: v_mov_b32_e32 v1, 0236; GFX9-NEXT: s_waitcnt lgkmcnt(0)237; GFX9-NEXT: global_load_dword v0, v0, s[2:3]238; GFX9-NEXT: s_waitcnt vmcnt(0)239; GFX9-NEXT: v_pk_sub_i16 v2, 0, v0240; GFX9-NEXT: v_pk_max_i16 v0, v0, v2241; GFX9-NEXT: v_pk_add_u16 v0, v0, 2 op_sel_hi:[1,0]242; GFX9-NEXT: global_store_dword v1, v0, s[0:1]243; GFX9-NEXT: s_endpgm244;245; VI-LABEL: v_abs_v2i16_2:246; VI: ; %bb.0:247; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24248; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0249; VI-NEXT: v_mov_b32_e32 v3, 0250; VI-NEXT: v_mov_b32_e32 v4, 2251; VI-NEXT: s_waitcnt lgkmcnt(0)252; VI-NEXT: v_mov_b32_e32 v1, s3253; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0254; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc255; VI-NEXT: flat_load_dword v2, v[0:1]256; VI-NEXT: v_mov_b32_e32 v0, s0257; VI-NEXT: v_mov_b32_e32 v1, s1258; VI-NEXT: s_waitcnt vmcnt(0)259; VI-NEXT: v_sub_u16_e32 v5, 0, v2260; VI-NEXT: v_sub_u16_sdwa v3, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1261; VI-NEXT: v_max_i16_sdwa v3, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD262; VI-NEXT: v_max_i16_e32 v2, v2, v5263; VI-NEXT: v_add_u16_e32 v2, 2, v2264; VI-NEXT: v_add_u16_sdwa v3, v3, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD265; VI-NEXT: v_or_b32_e32 v2, v2, v3266; VI-NEXT: flat_store_dword v[0:1], v2267; VI-NEXT: s_endpgm268;269; CI-LABEL: v_abs_v2i16_2:270; CI: ; %bb.0:271; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9272; CI-NEXT: s_mov_b32 s7, 0xf000273; CI-NEXT: s_mov_b32 s10, 0274; CI-NEXT: s_mov_b32 s11, s7275; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0276; CI-NEXT: s_waitcnt lgkmcnt(0)277; CI-NEXT: s_mov_b64 s[8:9], s[2:3]278; CI-NEXT: v_mov_b32_e32 v1, 0279; CI-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64280; CI-NEXT: s_mov_b32 s6, -1281; CI-NEXT: s_mov_b32 s4, s0282; CI-NEXT: s_mov_b32 s5, s1283; CI-NEXT: s_waitcnt vmcnt(0)284; CI-NEXT: v_bfe_i32 v1, v0, 0, 16285; CI-NEXT: v_ashrrev_i32_e32 v2, 16, v0286; CI-NEXT: v_lshrrev_b32_e32 v3, 16, v0287; CI-NEXT: v_sub_i32_e32 v0, vcc, 0, v0288; CI-NEXT: v_bfe_i32 v0, v0, 0, 16289; CI-NEXT: v_sub_i32_e32 v3, vcc, 0, v3290; CI-NEXT: v_bfe_i32 v3, v3, 0, 16291; CI-NEXT: v_max_i32_e32 v0, v1, v0292; CI-NEXT: v_max_i32_e32 v1, v2, v3293; CI-NEXT: v_add_i32_e32 v0, vcc, 2, v0294; CI-NEXT: v_and_b32_e32 v0, 0xffff, v0295; CI-NEXT: v_lshlrev_b32_e32 v1, 16, v1296; CI-NEXT: v_or_b32_e32 v0, v1, v0297; CI-NEXT: v_add_i32_e32 v0, vcc, 0x20000, v0298; CI-NEXT: buffer_store_dword v0, off, s[4:7], 0299; CI-NEXT: s_endpgm300 %z0 = insertelement <2 x i16> poison, i16 0, i16 0301 %z1 = insertelement <2 x i16> %z0, i16 0, i16 1302 %t0 = insertelement <2 x i16> poison, i16 2, i16 0303 %t1 = insertelement <2 x i16> %t0, i16 2, i16 1304 %tid = call i32 @llvm.amdgcn.workitem.id.x()305 %gep.in = getelementptr inbounds <2 x i16>, ptr addrspace(1) %src, i32 %tid306 %val = load <2 x i16>, ptr addrspace(1) %gep.in, align 4307 %neg = sub <2 x i16> %z1, %val308 %cond = icmp sgt <2 x i16> %val, %neg309 %res = select <2 x i1> %cond, <2 x i16> %val, <2 x i16> %neg310 %res2 = add <2 x i16> %res, %t1311 store <2 x i16> %res2, ptr addrspace(1) %out, align 4312 ret void313}314 315define amdgpu_kernel void @s_abs_v4i16(ptr addrspace(1) %out, <4 x i16> %val) #0 {316; GFX9-LABEL: s_abs_v4i16:317; GFX9: ; %bb.0:318; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24319; GFX9-NEXT: v_mov_b32_e32 v2, 0320; GFX9-NEXT: s_waitcnt lgkmcnt(0)321; GFX9-NEXT: v_pk_sub_i16 v0, 0, s3322; GFX9-NEXT: v_pk_sub_i16 v1, 0, s2323; GFX9-NEXT: v_pk_max_i16 v3, s2, v1324; GFX9-NEXT: v_pk_max_i16 v0, s3, v0325; GFX9-NEXT: v_pk_add_u16 v1, v0, 2 op_sel_hi:[1,0]326; GFX9-NEXT: v_pk_add_u16 v0, v3, 2 op_sel_hi:[1,0]327; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]328; GFX9-NEXT: s_endpgm329;330; VI-LABEL: s_abs_v4i16:331; VI: ; %bb.0:332; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24333; VI-NEXT: s_waitcnt lgkmcnt(0)334; VI-NEXT: s_lshr_b32 s7, s2, 16335; VI-NEXT: s_sub_i32 s7, 0, s7336; VI-NEXT: s_sub_i32 s4, 0, s3337; VI-NEXT: s_lshr_b32 s6, s3, 16338; VI-NEXT: s_ashr_i32 s8, s2, 16339; VI-NEXT: s_sext_i32_i16 s7, s7340; VI-NEXT: s_sub_i32 s5, 0, s2341; VI-NEXT: s_sub_i32 s6, 0, s6342; VI-NEXT: s_max_i32 s7, s8, s7343; VI-NEXT: s_ashr_i32 s8, s3, 16344; VI-NEXT: s_sext_i32_i16 s4, s4345; VI-NEXT: s_sext_i32_i16 s3, s3346; VI-NEXT: s_sext_i32_i16 s6, s6347; VI-NEXT: s_sext_i32_i16 s5, s5348; VI-NEXT: s_sext_i32_i16 s2, s2349; VI-NEXT: s_max_i32 s3, s3, s4350; VI-NEXT: s_max_i32 s6, s8, s6351; VI-NEXT: s_max_i32 s2, s2, s5352; VI-NEXT: s_add_i32 s3, s3, 2353; VI-NEXT: s_lshl_b32 s4, s6, 16354; VI-NEXT: s_and_b32 s3, s3, 0xffff355; VI-NEXT: s_add_i32 s2, s2, 2356; VI-NEXT: s_or_b32 s3, s4, s3357; VI-NEXT: s_lshl_b32 s4, s7, 16358; VI-NEXT: s_and_b32 s2, s2, 0xffff359; VI-NEXT: s_or_b32 s2, s4, s2360; VI-NEXT: s_add_i32 s3, s3, 0x20000361; VI-NEXT: s_add_i32 s2, s2, 0x20000362; VI-NEXT: v_mov_b32_e32 v3, s1363; VI-NEXT: v_mov_b32_e32 v0, s2364; VI-NEXT: v_mov_b32_e32 v1, s3365; VI-NEXT: v_mov_b32_e32 v2, s0366; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]367; VI-NEXT: s_endpgm368;369; CI-LABEL: s_abs_v4i16:370; CI: ; %bb.0:371; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9372; CI-NEXT: s_waitcnt lgkmcnt(0)373; CI-NEXT: s_mov_b64 s[4:5], s[2:3]374; CI-NEXT: s_ashr_i32 s6, s5, 16375; CI-NEXT: s_lshr_b32 s9, s5, 16376; CI-NEXT: s_sext_i32_i16 s10, s5377; CI-NEXT: s_sub_i32 s5, 0, s5378; CI-NEXT: s_ashr_i32 s7, s4, 16379; CI-NEXT: s_lshr_b32 s8, s4, 16380; CI-NEXT: s_sext_i32_i16 s11, s4381; CI-NEXT: s_sext_i32_i16 s5, s5382; CI-NEXT: s_sub_i32 s4, 0, s4383; CI-NEXT: s_sub_i32 s9, 0, s9384; CI-NEXT: s_sext_i32_i16 s4, s4385; CI-NEXT: s_sext_i32_i16 s9, s9386; CI-NEXT: s_sub_i32 s8, 0, s8387; CI-NEXT: s_max_i32 s5, s10, s5388; CI-NEXT: s_sext_i32_i16 s8, s8389; CI-NEXT: s_max_i32 s6, s6, s9390; CI-NEXT: s_max_i32 s4, s11, s4391; CI-NEXT: s_add_i32 s5, s5, 2392; CI-NEXT: s_max_i32 s7, s7, s8393; CI-NEXT: s_lshl_b32 s6, s6, 16394; CI-NEXT: s_and_b32 s5, s5, 0xffff395; CI-NEXT: s_add_i32 s4, s4, 2396; CI-NEXT: s_or_b32 s5, s6, s5397; CI-NEXT: s_lshl_b32 s6, s7, 16398; CI-NEXT: s_and_b32 s4, s4, 0xffff399; CI-NEXT: s_or_b32 s4, s6, s4400; CI-NEXT: s_add_i32 s5, s5, 0x20000401; CI-NEXT: s_add_i32 s4, s4, 0x20000402; CI-NEXT: s_mov_b32 s3, 0xf000403; CI-NEXT: s_mov_b32 s2, -1404; CI-NEXT: v_mov_b32_e32 v0, s4405; CI-NEXT: v_mov_b32_e32 v1, s5406; CI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0407; CI-NEXT: s_endpgm408 %z0 = insertelement <4 x i16> poison, i16 0, i16 0409 %z1 = insertelement <4 x i16> %z0, i16 0, i16 1410 %z2 = insertelement <4 x i16> %z1, i16 0, i16 2411 %z3 = insertelement <4 x i16> %z2, i16 0, i16 3412 %t0 = insertelement <4 x i16> poison, i16 2, i16 0413 %t1 = insertelement <4 x i16> %t0, i16 2, i16 1414 %t2 = insertelement <4 x i16> %t1, i16 2, i16 2415 %t3 = insertelement <4 x i16> %t2, i16 2, i16 3416 %neg = sub <4 x i16> %z3, %val417 %cond = icmp sgt <4 x i16> %val, %neg418 %res = select <4 x i1> %cond, <4 x i16> %val, <4 x i16> %neg419 %res2 = add <4 x i16> %res, %t3420 store <4 x i16> %res2, ptr addrspace(1) %out, align 4421 ret void422}423 424 425 426define amdgpu_kernel void @v_abs_v4i16(ptr addrspace(1) %out, ptr addrspace(1) %src) #0 {427; GFX9-LABEL: v_abs_v4i16:428; GFX9: ; %bb.0:429; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24430; GFX9-NEXT: v_lshlrev_b32_e32 v0, 3, v0431; GFX9-NEXT: v_mov_b32_e32 v2, 0432; GFX9-NEXT: s_waitcnt lgkmcnt(0)433; GFX9-NEXT: global_load_dwordx2 v[0:1], v0, s[2:3]434; GFX9-NEXT: s_waitcnt vmcnt(0)435; GFX9-NEXT: v_pk_sub_i16 v3, 0, v1436; GFX9-NEXT: v_pk_sub_i16 v4, 0, v0437; GFX9-NEXT: v_pk_max_i16 v0, v0, v4438; GFX9-NEXT: v_pk_max_i16 v1, v1, v3439; GFX9-NEXT: v_pk_add_u16 v1, v1, 2 op_sel_hi:[1,0]440; GFX9-NEXT: v_pk_add_u16 v0, v0, 2 op_sel_hi:[1,0]441; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]442; GFX9-NEXT: s_endpgm443;444; VI-LABEL: v_abs_v4i16:445; VI: ; %bb.0:446; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24447; VI-NEXT: v_lshlrev_b32_e32 v0, 3, v0448; VI-NEXT: v_mov_b32_e32 v4, 0449; VI-NEXT: v_mov_b32_e32 v5, 2450; VI-NEXT: s_waitcnt lgkmcnt(0)451; VI-NEXT: v_mov_b32_e32 v1, s3452; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0453; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc454; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]455; VI-NEXT: v_mov_b32_e32 v2, s0456; VI-NEXT: v_mov_b32_e32 v3, s1457; VI-NEXT: s_waitcnt vmcnt(0)458; VI-NEXT: v_sub_u16_e32 v6, 0, v1459; VI-NEXT: v_sub_u16_sdwa v7, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1460; VI-NEXT: v_sub_u16_e32 v8, 0, v0461; VI-NEXT: v_sub_u16_sdwa v4, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1462; VI-NEXT: v_max_i16_sdwa v4, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD463; VI-NEXT: v_max_i16_e32 v0, v0, v8464; VI-NEXT: v_max_i16_sdwa v7, v1, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD465; VI-NEXT: v_max_i16_e32 v1, v1, v6466; VI-NEXT: v_add_u16_e32 v1, 2, v1467; VI-NEXT: v_add_u16_sdwa v6, v7, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD468; VI-NEXT: v_add_u16_e32 v0, 2, v0469; VI-NEXT: v_add_u16_sdwa v4, v4, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD470; VI-NEXT: v_or_b32_e32 v1, v1, v6471; VI-NEXT: v_or_b32_e32 v0, v0, v4472; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]473; VI-NEXT: s_endpgm474;475; CI-LABEL: v_abs_v4i16:476; CI: ; %bb.0:477; CI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x9478; CI-NEXT: s_mov_b32 s3, 0xf000479; CI-NEXT: s_mov_b32 s10, 0480; CI-NEXT: s_mov_b32 s11, s3481; CI-NEXT: v_lshlrev_b32_e32 v0, 3, v0482; CI-NEXT: s_waitcnt lgkmcnt(0)483; CI-NEXT: s_mov_b64 s[8:9], s[6:7]484; CI-NEXT: v_mov_b32_e32 v1, 0485; CI-NEXT: buffer_load_dwordx2 v[0:1], v[0:1], s[8:11], 0 addr64486; CI-NEXT: s_mov_b32 s2, -1487; CI-NEXT: s_mov_b32 s0, s4488; CI-NEXT: s_mov_b32 s1, s5489; CI-NEXT: s_waitcnt vmcnt(0)490; CI-NEXT: v_bfe_i32 v2, v1, 0, 16491; CI-NEXT: v_ashrrev_i32_e32 v3, 16, v1492; CI-NEXT: v_bfe_i32 v4, v0, 0, 16493; CI-NEXT: v_ashrrev_i32_e32 v5, 16, v0494; CI-NEXT: v_lshrrev_b32_e32 v6, 16, v0495; CI-NEXT: v_lshrrev_b32_e32 v7, 16, v1496; CI-NEXT: v_sub_i32_e32 v1, vcc, 0, v1497; CI-NEXT: v_sub_i32_e32 v0, vcc, 0, v0498; CI-NEXT: v_bfe_i32 v1, v1, 0, 16499; CI-NEXT: v_sub_i32_e32 v7, vcc, 0, v7500; CI-NEXT: v_bfe_i32 v0, v0, 0, 16501; CI-NEXT: v_sub_i32_e32 v6, vcc, 0, v6502; CI-NEXT: v_bfe_i32 v7, v7, 0, 16503; CI-NEXT: v_bfe_i32 v6, v6, 0, 16504; CI-NEXT: v_max_i32_e32 v0, v4, v0505; CI-NEXT: v_max_i32_e32 v1, v2, v1506; CI-NEXT: v_max_i32_e32 v2, v5, v6507; CI-NEXT: v_max_i32_e32 v3, v3, v7508; CI-NEXT: v_add_i32_e32 v1, vcc, 2, v1509; CI-NEXT: v_add_i32_e32 v0, vcc, 2, v0510; CI-NEXT: v_and_b32_e32 v1, 0xffff, v1511; CI-NEXT: v_lshlrev_b32_e32 v3, 16, v3512; CI-NEXT: v_and_b32_e32 v0, 0xffff, v0513; CI-NEXT: v_lshlrev_b32_e32 v2, 16, v2514; CI-NEXT: v_or_b32_e32 v1, v3, v1515; CI-NEXT: v_or_b32_e32 v0, v2, v0516; CI-NEXT: v_add_i32_e32 v1, vcc, 0x20000, v1517; CI-NEXT: v_add_i32_e32 v0, vcc, 0x20000, v0518; CI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0519; CI-NEXT: s_endpgm520 %z0 = insertelement <4 x i16> poison, i16 0, i16 0521 %z1 = insertelement <4 x i16> %z0, i16 0, i16 1522 %z2 = insertelement <4 x i16> %z1, i16 0, i16 2523 %z3 = insertelement <4 x i16> %z2, i16 0, i16 3524 %t0 = insertelement <4 x i16> poison, i16 2, i16 0525 %t1 = insertelement <4 x i16> %t0, i16 2, i16 1526 %t2 = insertelement <4 x i16> %t1, i16 2, i16 2527 %t3 = insertelement <4 x i16> %t2, i16 2, i16 3528 %tid = call i32 @llvm.amdgcn.workitem.id.x()529 %gep.in = getelementptr inbounds <4 x i16>, ptr addrspace(1) %src, i32 %tid530 %val = load <4 x i16>, ptr addrspace(1) %gep.in, align 4531 %neg = sub <4 x i16> %z3, %val532 %cond = icmp sgt <4 x i16> %val, %neg533 %res = select <4 x i1> %cond, <4 x i16> %val, <4 x i16> %neg534 %res2 = add <4 x i16> %res, %t3535 store <4 x i16> %res2, ptr addrspace(1) %out, align 4536 ret void537}538 539define amdgpu_kernel void @s_min_max_v2i16(ptr addrspace(1) %out0, ptr addrspace(1) %out1, <2 x i16> %val0, <2 x i16> %val1) #0 {540; GFX9-LABEL: s_min_max_v2i16:541; GFX9: ; %bb.0:542; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34543; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24544; GFX9-NEXT: v_mov_b32_e32 v0, 0545; GFX9-NEXT: s_waitcnt lgkmcnt(0)546; GFX9-NEXT: v_mov_b32_e32 v1, s7547; GFX9-NEXT: v_pk_max_i16 v2, s6, v1548; GFX9-NEXT: v_pk_min_i16 v1, s6, v1549; GFX9-NEXT: global_store_dword v0, v2, s[0:1]550; GFX9-NEXT: s_waitcnt vmcnt(0)551; GFX9-NEXT: global_store_dword v0, v1, s[2:3]552; GFX9-NEXT: s_waitcnt vmcnt(0)553; GFX9-NEXT: s_endpgm554;555; VI-LABEL: s_min_max_v2i16:556; VI: ; %bb.0:557; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24558; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34559; VI-NEXT: s_waitcnt lgkmcnt(0)560; VI-NEXT: v_mov_b32_e32 v0, s0561; VI-NEXT: v_mov_b32_e32 v1, s1562; VI-NEXT: v_mov_b32_e32 v3, s3563; VI-NEXT: s_ashr_i32 s0, s5, 16564; VI-NEXT: s_ashr_i32 s1, s4, 16565; VI-NEXT: s_sext_i32_i16 s3, s5566; VI-NEXT: s_sext_i32_i16 s4, s4567; VI-NEXT: v_mov_b32_e32 v2, s2568; VI-NEXT: s_max_i32 s2, s1, s0569; VI-NEXT: s_max_i32 s5, s4, s3570; VI-NEXT: s_lshl_b32 s2, s2, 16571; VI-NEXT: s_and_b32 s5, s5, 0xffff572; VI-NEXT: s_min_i32 s0, s1, s0573; VI-NEXT: s_min_i32 s1, s4, s3574; VI-NEXT: s_or_b32 s2, s5, s2575; VI-NEXT: s_lshl_b32 s0, s0, 16576; VI-NEXT: s_and_b32 s1, s1, 0xffff577; VI-NEXT: s_or_b32 s0, s1, s0578; VI-NEXT: v_mov_b32_e32 v4, s2579; VI-NEXT: flat_store_dword v[0:1], v4580; VI-NEXT: s_waitcnt vmcnt(0)581; VI-NEXT: v_mov_b32_e32 v0, s0582; VI-NEXT: flat_store_dword v[2:3], v0583; VI-NEXT: s_waitcnt vmcnt(0)584; VI-NEXT: s_endpgm585;586; CI-LABEL: s_min_max_v2i16:587; CI: ; %bb.0:588; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9589; CI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd590; CI-NEXT: s_mov_b32 s7, 0xf000591; CI-NEXT: s_mov_b32 s6, -1592; CI-NEXT: s_waitcnt lgkmcnt(0)593; CI-NEXT: s_mov_b32 s4, s0594; CI-NEXT: s_ashr_i32 s10, s8, 16595; CI-NEXT: s_ashr_i32 s11, s9, 16596; CI-NEXT: s_sext_i32_i16 s8, s8597; CI-NEXT: s_sext_i32_i16 s9, s9598; CI-NEXT: s_max_i32 s12, s10, s11599; CI-NEXT: s_mov_b32 s5, s1600; CI-NEXT: s_max_i32 s13, s8, s9601; CI-NEXT: v_mov_b32_e32 v0, s12602; CI-NEXT: s_min_i32 s10, s10, s11603; CI-NEXT: buffer_store_short v0, off, s[4:7], 0 offset:2604; CI-NEXT: s_waitcnt vmcnt(0)605; CI-NEXT: v_mov_b32_e32 v0, s13606; CI-NEXT: s_mov_b32 s0, s2607; CI-NEXT: s_mov_b32 s1, s3608; CI-NEXT: s_mov_b32 s2, s6609; CI-NEXT: s_mov_b32 s3, s7610; CI-NEXT: s_min_i32 s8, s8, s9611; CI-NEXT: buffer_store_short v0, off, s[4:7], 0612; CI-NEXT: s_waitcnt vmcnt(0)613; CI-NEXT: v_mov_b32_e32 v0, s10614; CI-NEXT: buffer_store_short v0, off, s[0:3], 0 offset:2615; CI-NEXT: s_waitcnt vmcnt(0)616; CI-NEXT: v_mov_b32_e32 v0, s8617; CI-NEXT: buffer_store_short v0, off, s[0:3], 0618; CI-NEXT: s_waitcnt vmcnt(0)619; CI-NEXT: s_endpgm620 %cond0 = icmp sgt <2 x i16> %val0, %val1621 %sel0 = select <2 x i1> %cond0, <2 x i16> %val0, <2 x i16> %val1622 %sel1 = select <2 x i1> %cond0, <2 x i16> %val1, <2 x i16> %val0623 624 store volatile <2 x i16> %sel0, ptr addrspace(1) %out0, align 4625 store volatile <2 x i16> %sel1, ptr addrspace(1) %out1, align 4626 ret void627}628 629define amdgpu_kernel void @v_min_max_v2i16(ptr addrspace(1) %out0, ptr addrspace(1) %out1, ptr addrspace(1) %ptr0, ptr addrspace(1) %ptr1) #0 {630; GFX9-LABEL: v_min_max_v2i16:631; GFX9: ; %bb.0:632; GFX9-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x24633; GFX9-NEXT: v_mov_b32_e32 v0, 0634; GFX9-NEXT: s_waitcnt lgkmcnt(0)635; GFX9-NEXT: global_load_dword v1, v0, s[12:13] glc636; GFX9-NEXT: s_waitcnt vmcnt(0)637; GFX9-NEXT: global_load_dword v2, v0, s[14:15] glc638; GFX9-NEXT: s_waitcnt vmcnt(0)639; GFX9-NEXT: v_pk_max_i16 v3, v1, v2640; GFX9-NEXT: v_pk_min_i16 v1, v1, v2641; GFX9-NEXT: global_store_dword v0, v3, s[8:9]642; GFX9-NEXT: s_waitcnt vmcnt(0)643; GFX9-NEXT: global_store_dword v0, v1, s[10:11]644; GFX9-NEXT: s_waitcnt vmcnt(0)645; GFX9-NEXT: s_endpgm646;647; VI-LABEL: v_min_max_v2i16:648; VI: ; %bb.0:649; VI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24650; VI-NEXT: s_waitcnt lgkmcnt(0)651; VI-NEXT: v_mov_b32_e32 v0, s4652; VI-NEXT: v_mov_b32_e32 v1, s5653; VI-NEXT: v_mov_b32_e32 v2, s6654; VI-NEXT: v_mov_b32_e32 v3, s7655; VI-NEXT: flat_load_dword v4, v[0:1] glc656; VI-NEXT: s_waitcnt vmcnt(0)657; VI-NEXT: flat_load_dword v5, v[2:3] glc658; VI-NEXT: s_waitcnt vmcnt(0)659; VI-NEXT: v_mov_b32_e32 v0, s0660; VI-NEXT: v_mov_b32_e32 v1, s1661; VI-NEXT: v_mov_b32_e32 v2, s2662; VI-NEXT: v_mov_b32_e32 v3, s3663; VI-NEXT: v_max_i32_sdwa v6, sext(v4), sext(v5) dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1664; VI-NEXT: v_max_i32_sdwa v7, sext(v4), sext(v5) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:WORD_0665; VI-NEXT: v_min_i32_sdwa v8, sext(v4), sext(v5) dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1666; VI-NEXT: v_min_i32_sdwa v4, sext(v4), sext(v5) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:WORD_0667; VI-NEXT: v_or_b32_sdwa v5, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD668; VI-NEXT: v_or_b32_sdwa v4, v4, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD669; VI-NEXT: flat_store_dword v[0:1], v5670; VI-NEXT: s_waitcnt vmcnt(0)671; VI-NEXT: flat_store_dword v[2:3], v4672; VI-NEXT: s_waitcnt vmcnt(0)673; VI-NEXT: s_endpgm674;675; CI-LABEL: v_min_max_v2i16:676; CI: ; %bb.0:677; CI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9678; CI-NEXT: s_mov_b32 s11, 0xf000679; CI-NEXT: s_mov_b32 s10, -1680; CI-NEXT: s_mov_b32 s14, s10681; CI-NEXT: s_mov_b32 s15, s11682; CI-NEXT: s_waitcnt lgkmcnt(0)683; CI-NEXT: s_mov_b32 s12, s4684; CI-NEXT: s_mov_b32 s13, s5685; CI-NEXT: s_mov_b32 s4, s6686; CI-NEXT: s_mov_b32 s5, s7687; CI-NEXT: s_mov_b32 s6, s10688; CI-NEXT: s_mov_b32 s7, s11689; CI-NEXT: buffer_load_sshort v0, off, s[12:15], 0 glc690; CI-NEXT: s_waitcnt vmcnt(0)691; CI-NEXT: buffer_load_sshort v1, off, s[12:15], 0 offset:2 glc692; CI-NEXT: s_waitcnt vmcnt(0)693; CI-NEXT: buffer_load_sshort v2, off, s[4:7], 0 glc694; CI-NEXT: s_waitcnt vmcnt(0)695; CI-NEXT: buffer_load_sshort v3, off, s[4:7], 0 offset:2 glc696; CI-NEXT: s_waitcnt vmcnt(0)697; CI-NEXT: s_mov_b32 s8, s0698; CI-NEXT: s_mov_b32 s9, s1699; CI-NEXT: s_mov_b32 s4, s2700; CI-NEXT: s_mov_b32 s5, s3701; CI-NEXT: v_max_i32_e32 v4, v0, v2702; CI-NEXT: v_max_i32_e32 v5, v1, v3703; CI-NEXT: v_min_i32_e32 v0, v0, v2704; CI-NEXT: v_min_i32_e32 v1, v1, v3705; CI-NEXT: buffer_store_short v5, off, s[8:11], 0 offset:2706; CI-NEXT: s_waitcnt vmcnt(0)707; CI-NEXT: buffer_store_short v4, off, s[8:11], 0708; CI-NEXT: s_waitcnt vmcnt(0)709; CI-NEXT: buffer_store_short v1, off, s[4:7], 0 offset:2710; CI-NEXT: s_waitcnt vmcnt(0)711; CI-NEXT: buffer_store_short v0, off, s[4:7], 0712; CI-NEXT: s_waitcnt vmcnt(0)713; CI-NEXT: s_endpgm714 %val0 = load volatile <2 x i16>, ptr addrspace(1) %ptr0715 %val1 = load volatile <2 x i16>, ptr addrspace(1) %ptr1716 717 %cond0 = icmp sgt <2 x i16> %val0, %val1718 %sel0 = select <2 x i1> %cond0, <2 x i16> %val0, <2 x i16> %val1719 %sel1 = select <2 x i1> %cond0, <2 x i16> %val1, <2 x i16> %val0720 721 store volatile <2 x i16> %sel0, ptr addrspace(1) %out0, align 4722 store volatile <2 x i16> %sel1, ptr addrspace(1) %out1, align 4723 ret void724}725 726define amdgpu_kernel void @s_min_max_v4i16(ptr addrspace(1) %out0, ptr addrspace(1) %out1, <4 x i16> %val0, <4 x i16> %val1) #0 {727; GFX9-LABEL: s_min_max_v4i16:728; GFX9: ; %bb.0:729; GFX9-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x24730; GFX9-NEXT: v_mov_b32_e32 v4, 0731; GFX9-NEXT: s_waitcnt lgkmcnt(0)732; GFX9-NEXT: v_mov_b32_e32 v2, s15733; GFX9-NEXT: v_mov_b32_e32 v5, s14734; GFX9-NEXT: v_pk_max_i16 v1, s13, v2735; GFX9-NEXT: v_pk_max_i16 v0, s12, v5736; GFX9-NEXT: v_pk_min_i16 v3, s13, v2737; GFX9-NEXT: v_pk_min_i16 v2, s12, v5738; GFX9-NEXT: global_store_dwordx2 v4, v[0:1], s[8:9]739; GFX9-NEXT: s_waitcnt vmcnt(0)740; GFX9-NEXT: global_store_dwordx2 v4, v[2:3], s[10:11]741; GFX9-NEXT: s_waitcnt vmcnt(0)742; GFX9-NEXT: s_endpgm743;744; VI-LABEL: s_min_max_v4i16:745; VI: ; %bb.0:746; VI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24747; VI-NEXT: s_waitcnt lgkmcnt(0)748; VI-NEXT: v_mov_b32_e32 v0, s0749; VI-NEXT: v_mov_b32_e32 v1, s1750; VI-NEXT: v_mov_b32_e32 v3, s3751; VI-NEXT: s_ashr_i32 s0, s7, 16752; VI-NEXT: s_ashr_i32 s1, s5, 16753; VI-NEXT: s_sext_i32_i16 s3, s7754; VI-NEXT: s_sext_i32_i16 s5, s5755; VI-NEXT: v_mov_b32_e32 v2, s2756; VI-NEXT: s_max_i32 s2, s1, s0757; VI-NEXT: s_max_i32 s7, s5, s3758; VI-NEXT: s_lshl_b32 s2, s2, 16759; VI-NEXT: s_and_b32 s7, s7, 0xffff760; VI-NEXT: s_or_b32 s2, s7, s2761; VI-NEXT: s_ashr_i32 s7, s6, 16762; VI-NEXT: s_ashr_i32 s8, s4, 16763; VI-NEXT: s_sext_i32_i16 s6, s6764; VI-NEXT: s_sext_i32_i16 s4, s4765; VI-NEXT: s_min_i32 s0, s1, s0766; VI-NEXT: s_min_i32 s1, s5, s3767; VI-NEXT: s_max_i32 s9, s8, s7768; VI-NEXT: s_max_i32 s10, s4, s6769; VI-NEXT: s_lshl_b32 s0, s0, 16770; VI-NEXT: s_and_b32 s1, s1, 0xffff771; VI-NEXT: s_lshl_b32 s9, s9, 16772; VI-NEXT: s_and_b32 s10, s10, 0xffff773; VI-NEXT: v_mov_b32_e32 v5, s2774; VI-NEXT: s_or_b32 s0, s1, s0775; VI-NEXT: s_min_i32 s1, s8, s7776; VI-NEXT: s_min_i32 s2, s4, s6777; VI-NEXT: s_or_b32 s9, s10, s9778; VI-NEXT: s_lshl_b32 s1, s1, 16779; VI-NEXT: s_and_b32 s2, s2, 0xffff780; VI-NEXT: v_mov_b32_e32 v4, s9781; VI-NEXT: s_or_b32 s1, s2, s1782; VI-NEXT: v_mov_b32_e32 v6, s1783; VI-NEXT: v_mov_b32_e32 v7, s0784; VI-NEXT: flat_store_dwordx2 v[0:1], v[4:5]785; VI-NEXT: s_waitcnt vmcnt(0)786; VI-NEXT: flat_store_dwordx2 v[2:3], v[6:7]787; VI-NEXT: s_waitcnt vmcnt(0)788; VI-NEXT: s_endpgm789;790; CI-LABEL: s_min_max_v4i16:791; CI: ; %bb.0:792; CI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9793; CI-NEXT: s_mov_b32 s11, 0xf000794; CI-NEXT: s_mov_b32 s10, -1795; CI-NEXT: s_waitcnt lgkmcnt(0)796; CI-NEXT: s_ashr_i32 s12, s5, 16797; CI-NEXT: s_ashr_i32 s14, s7, 16798; CI-NEXT: s_sext_i32_i16 s5, s5799; CI-NEXT: s_sext_i32_i16 s7, s7800; CI-NEXT: s_max_i32 s17, s12, s14801; CI-NEXT: s_mov_b32 s8, s0802; CI-NEXT: s_mov_b32 s9, s1803; CI-NEXT: s_ashr_i32 s13, s4, 16804; CI-NEXT: s_ashr_i32 s15, s6, 16805; CI-NEXT: s_max_i32 s19, s5, s7806; CI-NEXT: v_mov_b32_e32 v0, s17807; CI-NEXT: s_sext_i32_i16 s4, s4808; CI-NEXT: s_sext_i32_i16 s6, s6809; CI-NEXT: s_max_i32 s16, s13, s15810; CI-NEXT: buffer_store_short v0, off, s[8:11], 0 offset:6811; CI-NEXT: s_waitcnt vmcnt(0)812; CI-NEXT: v_mov_b32_e32 v0, s19813; CI-NEXT: s_max_i32 s18, s4, s6814; CI-NEXT: buffer_store_short v0, off, s[8:11], 0 offset:4815; CI-NEXT: s_waitcnt vmcnt(0)816; CI-NEXT: v_mov_b32_e32 v0, s16817; CI-NEXT: s_min_i32 s12, s12, s14818; CI-NEXT: buffer_store_short v0, off, s[8:11], 0 offset:2819; CI-NEXT: s_waitcnt vmcnt(0)820; CI-NEXT: v_mov_b32_e32 v0, s18821; CI-NEXT: s_mov_b32 s0, s2822; CI-NEXT: s_mov_b32 s1, s3823; CI-NEXT: s_mov_b32 s2, s10824; CI-NEXT: s_mov_b32 s3, s11825; CI-NEXT: s_min_i32 s5, s5, s7826; CI-NEXT: buffer_store_short v0, off, s[8:11], 0827; CI-NEXT: s_waitcnt vmcnt(0)828; CI-NEXT: v_mov_b32_e32 v0, s12829; CI-NEXT: s_min_i32 s13, s13, s15830; CI-NEXT: buffer_store_short v0, off, s[0:3], 0 offset:6831; CI-NEXT: s_waitcnt vmcnt(0)832; CI-NEXT: v_mov_b32_e32 v0, s5833; CI-NEXT: s_min_i32 s4, s4, s6834; CI-NEXT: buffer_store_short v0, off, s[0:3], 0 offset:4835; CI-NEXT: s_waitcnt vmcnt(0)836; CI-NEXT: v_mov_b32_e32 v0, s13837; CI-NEXT: buffer_store_short v0, off, s[0:3], 0 offset:2838; CI-NEXT: s_waitcnt vmcnt(0)839; CI-NEXT: v_mov_b32_e32 v0, s4840; CI-NEXT: buffer_store_short v0, off, s[0:3], 0841; CI-NEXT: s_waitcnt vmcnt(0)842; CI-NEXT: s_endpgm843 %cond0 = icmp sgt <4 x i16> %val0, %val1844 %sel0 = select <4 x i1> %cond0, <4 x i16> %val0, <4 x i16> %val1845 %sel1 = select <4 x i1> %cond0, <4 x i16> %val1, <4 x i16> %val0846 847 store volatile <4 x i16> %sel0, ptr addrspace(1) %out0, align 4848 store volatile <4 x i16> %sel1, ptr addrspace(1) %out1, align 4849 ret void850}851 852define amdgpu_kernel void @v_min_max_v2i16_user(ptr addrspace(1) %out0, ptr addrspace(1) %out1, ptr addrspace(1) %ptr0, ptr addrspace(1) %ptr1) #0 {853; GFX9-LABEL: v_min_max_v2i16_user:854; GFX9: ; %bb.0:855; GFX9-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x24856; GFX9-NEXT: v_mov_b32_e32 v0, 0857; GFX9-NEXT: s_waitcnt lgkmcnt(0)858; GFX9-NEXT: global_load_dword v1, v0, s[12:13] glc859; GFX9-NEXT: s_waitcnt vmcnt(0)860; GFX9-NEXT: global_load_dword v2, v0, s[14:15] glc861; GFX9-NEXT: s_waitcnt vmcnt(0)862; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v1863; GFX9-NEXT: v_cmp_gt_i32_sdwa vcc, sext(v1), sext(v2) src0_sel:WORD_0 src1_sel:WORD_0864; GFX9-NEXT: v_cmp_gt_i32_sdwa s[0:1], sext(v1), sext(v2) src0_sel:WORD_1 src1_sel:WORD_1865; GFX9-NEXT: v_lshrrev_b32_e32 v4, 16, v2866; GFX9-NEXT: v_cndmask_b32_e32 v5, v2, v1, vcc867; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc868; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]869; GFX9-NEXT: v_cndmask_b32_e64 v6, v4, v3, s[0:1]870; GFX9-NEXT: v_cndmask_b32_e64 v3, v3, v4, s[0:1]871; GFX9-NEXT: v_and_b32_e32 v4, 0xffff, v5872; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc873; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v1874; GFX9-NEXT: v_lshlrev_b32_e32 v2, 1, v2875; GFX9-NEXT: v_lshl_or_b32 v4, v6, 16, v4876; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1877; GFX9-NEXT: v_or_b32_e32 v2, v5, v2878; GFX9-NEXT: global_store_dword v0, v4, s[8:9]879; GFX9-NEXT: s_waitcnt vmcnt(0)880; GFX9-NEXT: global_store_dword v0, v1, s[10:11]881; GFX9-NEXT: s_waitcnt vmcnt(0)882; GFX9-NEXT: v_and_b32_e32 v0, 3, v2883; GFX9-NEXT: global_store_byte v[0:1], v0, off884; GFX9-NEXT: s_waitcnt vmcnt(0)885; GFX9-NEXT: s_endpgm886;887; VI-LABEL: v_min_max_v2i16_user:888; VI: ; %bb.0:889; VI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24890; VI-NEXT: s_waitcnt lgkmcnt(0)891; VI-NEXT: v_mov_b32_e32 v0, s4892; VI-NEXT: v_mov_b32_e32 v1, s5893; VI-NEXT: v_mov_b32_e32 v2, s6894; VI-NEXT: v_mov_b32_e32 v3, s7895; VI-NEXT: flat_load_dword v4, v[0:1] glc896; VI-NEXT: s_waitcnt vmcnt(0)897; VI-NEXT: flat_load_dword v5, v[2:3] glc898; VI-NEXT: s_waitcnt vmcnt(0)899; VI-NEXT: v_mov_b32_e32 v0, s0900; VI-NEXT: v_mov_b32_e32 v1, s1901; VI-NEXT: v_mov_b32_e32 v2, s2902; VI-NEXT: v_mov_b32_e32 v3, s3903; VI-NEXT: v_ashrrev_i32_e32 v10, 16, v4904; VI-NEXT: v_ashrrev_i32_e32 v11, 16, v5905; VI-NEXT: v_bfe_i32 v6, v4, 0, 16906; VI-NEXT: v_bfe_i32 v7, v5, 0, 16907; VI-NEXT: v_lshrrev_b32_e32 v8, 16, v4908; VI-NEXT: v_lshrrev_b32_e32 v9, 16, v5909; VI-NEXT: v_cmp_gt_i32_e32 vcc, v10, v11910; VI-NEXT: v_cndmask_b32_e32 v10, v9, v8, vcc911; VI-NEXT: v_cmp_gt_i32_e64 s[0:1], v6, v7912; VI-NEXT: v_cndmask_b32_e64 v6, v5, v4, s[0:1]913; VI-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc914; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v10915; VI-NEXT: v_cndmask_b32_e64 v4, v4, v5, s[0:1]916; VI-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc917; VI-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[0:1]918; VI-NEXT: v_or_b32_sdwa v6, v6, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD919; VI-NEXT: v_lshlrev_b32_e32 v5, 1, v5920; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7921; VI-NEXT: flat_store_dword v[0:1], v6922; VI-NEXT: s_waitcnt vmcnt(0)923; VI-NEXT: v_or_b32_e32 v0, v9, v5924; VI-NEXT: v_or_b32_sdwa v4, v4, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD925; VI-NEXT: v_and_b32_e32 v0, 3, v0926; VI-NEXT: flat_store_dword v[2:3], v4927; VI-NEXT: s_waitcnt vmcnt(0)928; VI-NEXT: flat_store_byte v[0:1], v0929; VI-NEXT: s_waitcnt vmcnt(0)930; VI-NEXT: s_endpgm931;932; CI-LABEL: v_min_max_v2i16_user:933; CI: ; %bb.0:934; CI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x9935; CI-NEXT: s_mov_b32 s7, 0xf000936; CI-NEXT: s_mov_b32 s6, -1937; CI-NEXT: s_mov_b32 s2, s6938; CI-NEXT: s_mov_b32 s3, s7939; CI-NEXT: s_waitcnt lgkmcnt(0)940; CI-NEXT: s_mov_b32 s0, s12941; CI-NEXT: s_mov_b32 s1, s13942; CI-NEXT: s_mov_b32 s12, s14943; CI-NEXT: s_mov_b32 s13, s15944; CI-NEXT: s_mov_b32 s14, s6945; CI-NEXT: s_mov_b32 s15, s7946; CI-NEXT: buffer_load_sshort v0, off, s[0:3], 0 glc947; CI-NEXT: s_waitcnt vmcnt(0)948; CI-NEXT: buffer_load_sshort v1, off, s[0:3], 0 offset:2 glc949; CI-NEXT: s_waitcnt vmcnt(0)950; CI-NEXT: buffer_load_sshort v2, off, s[12:15], 0 glc951; CI-NEXT: s_waitcnt vmcnt(0)952; CI-NEXT: buffer_load_sshort v3, off, s[12:15], 0 offset:2 glc953; CI-NEXT: s_waitcnt vmcnt(0)954; CI-NEXT: s_mov_b32 s4, s8955; CI-NEXT: s_mov_b32 s5, s9956; CI-NEXT: s_mov_b32 s12, s10957; CI-NEXT: s_mov_b32 s13, s11958; CI-NEXT: v_cmp_gt_i32_e32 vcc, v0, v2959; CI-NEXT: v_cmp_gt_i32_e64 s[0:1], v1, v3960; CI-NEXT: v_cndmask_b32_e32 v4, v2, v0, vcc961; CI-NEXT: v_cndmask_b32_e64 v5, v3, v1, s[0:1]962; CI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc963; CI-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1]964; CI-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]965; CI-NEXT: buffer_store_short v5, off, s[4:7], 0 offset:2966; CI-NEXT: s_waitcnt vmcnt(0)967; CI-NEXT: buffer_store_short v4, off, s[4:7], 0968; CI-NEXT: s_waitcnt vmcnt(0)969; CI-NEXT: buffer_store_short v1, off, s[12:15], 0 offset:2970; CI-NEXT: s_waitcnt vmcnt(0)971; CI-NEXT: buffer_store_short v0, off, s[12:15], 0972; CI-NEXT: s_waitcnt vmcnt(0)973; CI-NEXT: v_lshlrev_b32_e32 v0, 1, v2974; CI-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc975; CI-NEXT: v_or_b32_e32 v0, v1, v0976; CI-NEXT: v_and_b32_e32 v0, 3, v0977; CI-NEXT: buffer_store_byte v0, off, s[4:7], 0978; CI-NEXT: s_waitcnt vmcnt(0)979; CI-NEXT: s_endpgm980 %val0 = load volatile <2 x i16>, ptr addrspace(1) %ptr0981 %val1 = load volatile <2 x i16>, ptr addrspace(1) %ptr1982 983 %cond0 = icmp sgt <2 x i16> %val0, %val1984 %sel0 = select <2 x i1> %cond0, <2 x i16> %val0, <2 x i16> %val1985 %sel1 = select <2 x i1> %cond0, <2 x i16> %val1, <2 x i16> %val0986 987 store volatile <2 x i16> %sel0, ptr addrspace(1) %out0, align 4988 store volatile <2 x i16> %sel1, ptr addrspace(1) %out1, align 4989 store volatile <2 x i1> %cond0, ptr addrspace(1) poison990 ret void991}992 993define amdgpu_kernel void @u_min_max_v2i16(ptr addrspace(1) %out0, ptr addrspace(1) %out1, <2 x i16> %val0, <2 x i16> %val1) nounwind {994; GFX9-LABEL: u_min_max_v2i16:995; GFX9: ; %bb.0:996; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34997; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24998; GFX9-NEXT: v_mov_b32_e32 v0, 0999; GFX9-NEXT: s_waitcnt lgkmcnt(0)1000; GFX9-NEXT: v_mov_b32_e32 v1, s71001; GFX9-NEXT: v_pk_max_u16 v2, s6, v11002; GFX9-NEXT: v_pk_min_u16 v1, s6, v11003; GFX9-NEXT: global_store_dword v0, v2, s[0:1]1004; GFX9-NEXT: s_waitcnt vmcnt(0)1005; GFX9-NEXT: global_store_dword v0, v1, s[2:3]1006; GFX9-NEXT: s_waitcnt vmcnt(0)1007; GFX9-NEXT: s_endpgm1008;1009; VI-LABEL: u_min_max_v2i16:1010; VI: ; %bb.0:1011; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241012; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x341013; VI-NEXT: s_waitcnt lgkmcnt(0)1014; VI-NEXT: v_mov_b32_e32 v1, s11015; VI-NEXT: v_mov_b32_e32 v3, s31016; VI-NEXT: s_and_b32 s1, s4, 0xffff1017; VI-NEXT: s_lshr_b32 s3, s5, 161018; VI-NEXT: s_lshr_b32 s4, s4, 161019; VI-NEXT: v_mov_b32_e32 v0, s01020; VI-NEXT: s_and_b32 s0, s5, 0xffff1021; VI-NEXT: s_max_u32 s5, s4, s31022; VI-NEXT: v_mov_b32_e32 v2, s21023; VI-NEXT: s_max_u32 s2, s1, s01024; VI-NEXT: s_lshl_b32 s5, s5, 161025; VI-NEXT: s_min_u32 s0, s1, s01026; VI-NEXT: s_min_u32 s1, s4, s31027; VI-NEXT: s_or_b32 s2, s2, s51028; VI-NEXT: s_lshl_b32 s1, s1, 161029; VI-NEXT: s_or_b32 s0, s0, s11030; VI-NEXT: v_mov_b32_e32 v4, s21031; VI-NEXT: flat_store_dword v[0:1], v41032; VI-NEXT: s_waitcnt vmcnt(0)1033; VI-NEXT: v_mov_b32_e32 v0, s01034; VI-NEXT: flat_store_dword v[2:3], v01035; VI-NEXT: s_waitcnt vmcnt(0)1036; VI-NEXT: s_endpgm1037;1038; CI-LABEL: u_min_max_v2i16:1039; CI: ; %bb.0:1040; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91041; CI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd1042; CI-NEXT: s_mov_b32 s7, 0xf0001043; CI-NEXT: s_mov_b32 s6, -11044; CI-NEXT: s_waitcnt lgkmcnt(0)1045; CI-NEXT: s_mov_b32 s4, s01046; CI-NEXT: s_lshr_b32 s10, s8, 161047; CI-NEXT: s_lshr_b32 s11, s9, 161048; CI-NEXT: s_and_b32 s8, s8, 0xffff1049; CI-NEXT: s_and_b32 s9, s9, 0xffff1050; CI-NEXT: s_max_u32 s13, s10, s111051; CI-NEXT: s_mov_b32 s5, s11052; CI-NEXT: s_max_u32 s12, s8, s91053; CI-NEXT: v_mov_b32_e32 v0, s131054; CI-NEXT: s_min_u32 s8, s8, s91055; CI-NEXT: s_min_u32 s9, s10, s111056; CI-NEXT: buffer_store_short v0, off, s[4:7], 0 offset:21057; CI-NEXT: s_waitcnt vmcnt(0)1058; CI-NEXT: v_mov_b32_e32 v0, s121059; CI-NEXT: s_mov_b32 s0, s21060; CI-NEXT: s_mov_b32 s1, s31061; CI-NEXT: s_mov_b32 s2, s61062; CI-NEXT: s_mov_b32 s3, s71063; CI-NEXT: buffer_store_short v0, off, s[4:7], 01064; CI-NEXT: s_waitcnt vmcnt(0)1065; CI-NEXT: v_mov_b32_e32 v0, s91066; CI-NEXT: buffer_store_short v0, off, s[0:3], 0 offset:21067; CI-NEXT: s_waitcnt vmcnt(0)1068; CI-NEXT: v_mov_b32_e32 v0, s81069; CI-NEXT: buffer_store_short v0, off, s[0:3], 01070; CI-NEXT: s_waitcnt vmcnt(0)1071; CI-NEXT: s_endpgm1072 %cond0 = icmp ugt <2 x i16> %val0, %val11073 %sel0 = select <2 x i1> %cond0, <2 x i16> %val0, <2 x i16> %val11074 %sel1 = select <2 x i1> %cond0, <2 x i16> %val1, <2 x i16> %val01075 1076 store volatile <2 x i16> %sel0, ptr addrspace(1) %out0, align 41077 store volatile <2 x i16> %sel1, ptr addrspace(1) %out1, align 41078 ret void1079}1080 1081declare i32 @llvm.amdgcn.workitem.id.x() #11082 1083attributes #0 = { nounwind }1084attributes #1 = { nounwind readnone }1085