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1; RUN: llc -mtriple=amdgcn -mcpu=tahiti -show-mc-encoding < %s | FileCheck --check-prefixes=SI,GCN,SICIVI,SICI,SIVIGFX9_10 %s2; RUN: llc -mtriple=amdgcn -mcpu=bonaire -show-mc-encoding < %s | FileCheck --check-prefixes=CI,GCN,SICIVI,SICI %s3; RUN: llc -mtriple=amdgcn -mcpu=tonga -show-mc-encoding < %s | FileCheck --check-prefixes=VI,GCN,SICIVI,VIGFX9_10,SIVIGFX9_10 %s4; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -show-mc-encoding < %s | FileCheck --check-prefixes=GFX9_10,GCN,VIGFX9_10,SIVIGFX9_10 %s5; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -show-mc-encoding < %s | FileCheck --check-prefixes=GFX10,GFX9_10,GCN,VIGFX9_10,SIVIGFX9_10 %s6 7; SMRD load with an immediate offset.8; GCN-LABEL: {{^}}smrd0:9; SICI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x1 ; encoding: [0x0110; VIGFX9_10: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x411define amdgpu_kernel void @smrd0(ptr addrspace(1) %out, ptr addrspace(4) %ptr) #0 {12entry:13 %tmp = getelementptr i32, ptr addrspace(4) %ptr, i64 114 %tmp1 = load i32, ptr addrspace(4) %tmp15 store i32 %tmp1, ptr addrspace(1) %out16 ret void17}18 19; SMRD load with the largest possible immediate offset.20; GCN-LABEL: {{^}}smrd1:21; SICI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xff ; encoding: [0xff,0x{{[0-9]+[137]}}22; VIGFX9_10: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3fc23define amdgpu_kernel void @smrd1(ptr addrspace(1) %out, ptr addrspace(4) %ptr) #0 {24entry:25 %tmp = getelementptr i32, ptr addrspace(4) %ptr, i64 25526 %tmp1 = load i32, ptr addrspace(4) %tmp27 store i32 %tmp1, ptr addrspace(1) %out28 ret void29}30 31; SMRD load with an offset greater than the largest possible immediate.32; GCN-LABEL: {{^}}smrd2:33; SI: s_movk_i32 s[[OFFSET:[0-9]]], 0x40034; SI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], s[[OFFSET]] ; encoding: [0x0[[OFFSET]]35; CI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x10036; VIGFX9_10: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x40037; GCN: s_endpgm38define amdgpu_kernel void @smrd2(ptr addrspace(1) %out, ptr addrspace(4) %ptr) #0 {39entry:40 %tmp = getelementptr i32, ptr addrspace(4) %ptr, i64 25641 %tmp1 = load i32, ptr addrspace(4) %tmp42 store i32 %tmp1, ptr addrspace(1) %out43 ret void44}45 46; SMRD load with a 64-bit offset47; GCN-LABEL: {{^}}smrd3:48; FIXME: There are too many copies here because we don't fold immediates49; through REG_SEQUENCE50; SI: s_load_dwordx2 s[{{[0-9]:[0-9]}}], s[{{[0-9]:[0-9]}}], 0x13 ; encoding: [0x1351; TODO: Add VI checks52; GCN: s_endpgm53define amdgpu_kernel void @smrd3(ptr addrspace(1) %out, [8 x i32], ptr addrspace(4) %ptr) #0 {54entry:55 %tmp = getelementptr i32, ptr addrspace(4) %ptr, i64 429496729656 %tmp1 = load i32, ptr addrspace(4) %tmp57 store i32 %tmp1, ptr addrspace(1) %out58 ret void59}60 61; SMRD load with the largest possible immediate offset on VI62; GCN-LABEL: {{^}}smrd4:63; SI: s_mov_b32 [[OFFSET:s[0-9]+]], 0xffffc64; SI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]]65; CI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3ffff66; VI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xffffc67; GFX9_10: s_mov_b32 [[OFFSET:s[0-9]+]], 0xffffc68; GFX9_10: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]]69define amdgpu_kernel void @smrd4(ptr addrspace(1) %out, ptr addrspace(4) %ptr) #0 {70entry:71 %tmp = getelementptr i32, ptr addrspace(4) %ptr, i64 26214372 %tmp1 = load i32, ptr addrspace(4) %tmp73 store i32 %tmp1, ptr addrspace(1) %out74 ret void75}76 77; SMRD load with an offset greater than the largest possible immediate on VI78; GCN-LABEL: {{^}}smrd5:79; SIVIGFX9_10: s_mov_b32 [[OFFSET:s[0-9]+]], 0x10000080; SIVIGFX9_10: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]]81; CI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x4000082; GCN: s_endpgm83define amdgpu_kernel void @smrd5(ptr addrspace(1) %out, ptr addrspace(4) %ptr) #0 {84entry:85 %tmp = getelementptr i32, ptr addrspace(4) %ptr, i64 26214486 %tmp1 = load i32, ptr addrspace(4) %tmp87 store i32 %tmp1, ptr addrspace(1) %out88 ret void89}90 91; GFX9+ can use a signed immediate byte offset but not without sgpr[offset]92; GCN-LABEL: {{^}}smrd6:93; SICIVI: s_add_u32 s{{[0-9]}}, s{{[0-9]}}, -494; SICIVI: s_load_dword s{{[0-9]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x095; GFX9_10: s_add_u32 s2, s2, -496; GFX9_10: s_addc_u32 s3, s3, -197; GFX9_10: s_load_dword s{{[0-9]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x098define amdgpu_kernel void @smrd6(ptr addrspace(1) %out, ptr addrspace(4) %ptr) #0 {99entry:100 %tmp = getelementptr i32, ptr addrspace(4) %ptr, i64 -1101 %tmp1 = load i32, ptr addrspace(4) %tmp102 store i32 %tmp1, ptr addrspace(1) %out103 ret void104}105 106; Don't use a negative SGPR offset107; GCN-LABEL: {{^}}smrd7:108; GCN: s_add_u32 s{{[0-9]}}, s{{[0-9]}}, 0xffe00000109; SICIVI: s_load_dword s{{[0-9]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x0110; GFX9_10: s_load_dword s{{[0-9]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x0111define amdgpu_kernel void @smrd7(ptr addrspace(1) %out, ptr addrspace(4) %ptr) #0 {112entry:113 %tmp = getelementptr i32, ptr addrspace(4) %ptr, i64 -524288114 %tmp1 = load i32, ptr addrspace(4) %tmp115 store i32 %tmp1, ptr addrspace(1) %out116 ret void117}118 119; GCN-LABEL: {{^}}smrd_hazard:120; GCN-DAG: s_mov_b32 s3, 3121; GCN-DAG: s_mov_b32 s2, 2122; GCN-DAG: s_mov_b32 s1, 1123; GCN-DAG: s_mov_b32 s0, 0124; SI-NEXT: nop 3125; GCN-NEXT: s_buffer_load_dword s0, s[0:3], 0x0126define amdgpu_ps float @smrd_hazard(<4 x i32> inreg %desc) #0 {127main_body:128 %d0 = insertelement <4 x i32> poison, i32 0, i32 0129 %d1 = insertelement <4 x i32> %d0, i32 1, i32 1130 %d2 = insertelement <4 x i32> %d1, i32 2, i32 2131 %d3 = insertelement <4 x i32> %d2, i32 3, i32 3132 %r = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %d3, i32 0, i32 0)133 ret float %r134}135 136; SMRD load using the load.const.v4i32 intrinsic with an immediate offset137; GCN-LABEL: {{^}}smrd_load_const0:138; SICI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x4 ; encoding: [0x04139; VIGFX9_10: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x10140define amdgpu_ps void @smrd_load_const0(ptr addrspace(4) inreg %arg, ptr addrspace(4) inreg %arg1, ptr addrspace(4) inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, ptr addrspace(4) inreg %in) #0 {141main_body:142 %tmp20 = load <4 x i32>, ptr addrspace(4) %arg143 %tmp21 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 16, i32 0)144 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %tmp21, float %tmp21, float %tmp21, float %tmp21, i1 true, i1 true) #0145 ret void146}147 148; SMRD load using the load.const.v4i32 intrinsic with the largest possible immediate149; offset.150; GCN-LABEL: {{^}}smrd_load_const1:151; SICI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xff ; encoding: [0xff152; SICI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xff glc ; encoding: [0xff153; VIGFX9_10: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]+}}], 0x3fc ;154; VIGFX9_10: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]+}}], 0x3fc glc ;155define amdgpu_ps void @smrd_load_const1(ptr addrspace(4) inreg %arg, ptr addrspace(4) inreg %arg1, ptr addrspace(4) inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, ptr addrspace(4) inreg %in) #0 {156main_body:157 %tmp20 = load <4 x i32>, ptr addrspace(4) %arg158 %tmp21 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 1020, i32 0)159 %tmp22 = load <4 x i32>, ptr addrspace(4) %in160 %s.buffer = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %tmp22, i32 1020, i32 1)161 %s.buffer.float = bitcast i32 %s.buffer to float162 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %tmp21, float %tmp21, float %tmp21, float %s.buffer.float, i1 true, i1 true) #0163 ret void164}165 166; SMRD load using the load.const.v4i32 intrinsic with an offset greater than the167; largets possible immediate.168; immediate offset.169; GCN-LABEL: {{^}}smrd_load_const2:170; SI: s_movk_i32 s[[OFFSET:[0-9]]], 0x400171; SI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], s[[OFFSET]] ; encoding: [0x0[[OFFSET]]172; SI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], s[[OFFSET]] ; encoding: [0x0[[OFFSET]]173; CI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x100174; CI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x100175; VIGFX9_10: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]+}}], 0x400176; VIGFX9_10: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]+}}], 0x400177define amdgpu_ps void @smrd_load_const2(ptr addrspace(4) inreg %arg, ptr addrspace(4) inreg %arg1, ptr addrspace(4) inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, ptr addrspace(4) inreg %in) #0 {178main_body:179 %tmp20 = load <4 x i32>, ptr addrspace(4) %arg180 %tmp21 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 1024, i32 0)181 %tmp22 = load <4 x i32>, ptr addrspace(4) %in182 %s.buffer = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %tmp22, i32 1024, i32 0)183 %s.buffer.float = bitcast i32 %s.buffer to float184 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %tmp21, float %tmp21, float %tmp21, float %s.buffer.float, i1 true, i1 true) #0185 ret void186}187 188; SMRD load with the largest possible immediate offset on VI189; GCN-LABEL: {{^}}smrd_load_const3:190; SI: s_mov_b32 [[OFFSET:s[0-9]+]], 0xffffc191; SI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]]192; SI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]]193; CI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3ffff194; CI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3ffff195; VIGFX9_10: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]+}}], 0xffffc196; VIGFX9_10: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]+}}], 0xffffc197define amdgpu_ps void @smrd_load_const3(ptr addrspace(4) inreg %arg, ptr addrspace(4) inreg %arg1, ptr addrspace(4) inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, ptr addrspace(4) inreg %in) #0 {198main_body:199 %tmp20 = load <4 x i32>, ptr addrspace(4) %arg200 %tmp21 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 1048572, i32 0)201 %tmp22 = load <4 x i32>, ptr addrspace(4) %in202 %s.buffer = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %tmp22, i32 1048572, i32 0)203 %s.buffer.float = bitcast i32 %s.buffer to float204 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %tmp21, float %tmp21, float %tmp21, float %s.buffer.float, i1 true, i1 true) #0205 ret void206}207 208; SMRD load with an offset greater than the largest possible immediate on VI209; GCN-LABEL: {{^}}smrd_load_const4:210; SIVIGFX9_10: s_mov_b32 [[OFFSET:s[0-9]+]], 0x100000211; SIVIGFX9_10: s_buffer_load_dword s{{[0-9]+}}, s[{{[0-9]:[0-9]+}}], [[OFFSET]]212; SIVIGFX9_10: s_buffer_load_dword s{{[0-9]+}}, s[{{[0-9]:[0-9]+}}], [[OFFSET]]213; CI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x40000214; CI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x40000215; GCN: s_endpgm216define amdgpu_ps void @smrd_load_const4(ptr addrspace(4) inreg %arg, ptr addrspace(4) inreg %arg1, ptr addrspace(4) inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, ptr addrspace(4) inreg %in) #0 {217main_body:218 %tmp20 = load <4 x i32>, ptr addrspace(4) %arg219 %tmp21 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 1048576, i32 0)220 %tmp22 = load <4 x i32>, ptr addrspace(4) %in221 %s.buffer = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %tmp22, i32 1048576, i32 0)222 %s.buffer.float = bitcast i32 %s.buffer to float223 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %tmp21, float %tmp21, float %tmp21, float %s.buffer.float, i1 true, i1 true) #0224 ret void225}226 227; dwordx2 s.buffer.load228; GCN-LABEL: {{^}}s_buffer_load_dwordx2:229; VIGFX9_10: s_buffer_load_dwordx2 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]:[0-9]}}], 0x80230; SICI: s_buffer_load_dwordx2 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]:[0-9]}}], 0x20231define amdgpu_ps void @s_buffer_load_dwordx2(ptr addrspace(4) inreg %arg, ptr addrspace(4) inreg %arg1, ptr addrspace(4) inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, ptr addrspace(4) inreg %in) #0 {232main_body:233 %tmp22 = load <4 x i32>, ptr addrspace(4) %in234 %s.buffer = call <2 x i32> @llvm.amdgcn.s.buffer.load.v2i32(<4 x i32> %tmp22, i32 128, i32 0)235 %s.buffer.0 = extractelement <2 x i32> %s.buffer, i32 0236 %s.buffer.0.float = bitcast i32 %s.buffer.0 to float237 %s.buffer.1 = extractelement <2 x i32> %s.buffer, i32 1238 %s.buffer.1.float = bitcast i32 %s.buffer.1 to float239 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %s.buffer.0.float, float %s.buffer.1.float, float %s.buffer.0.float, float %s.buffer.1.float, i1 true, i1 true) #0240 ret void241}242 243; dwordx4 s.buffer.load244; GCN-LABEL: {{^}}s_buffer_load_dwordx4:245; VIGFX9_10: s_buffer_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]:[0-9]}}], 0x80246; SICI: s_buffer_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]:[0-9]}}], 0x20247define amdgpu_ps void @s_buffer_load_dwordx4(ptr addrspace(4) inreg %arg, ptr addrspace(4) inreg %arg1, ptr addrspace(4) inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, ptr addrspace(4) inreg %in) #0 {248main_body:249 %tmp22 = load <4 x i32>, ptr addrspace(4) %in250 %s.buffer = call <4 x i32> @llvm.amdgcn.s.buffer.load.v4i32(<4 x i32> %tmp22, i32 128, i32 0)251 %s.buffer.0 = extractelement <4 x i32> %s.buffer, i32 0252 %s.buffer.0.float = bitcast i32 %s.buffer.0 to float253 %s.buffer.1 = extractelement <4 x i32> %s.buffer, i32 1254 %s.buffer.1.float = bitcast i32 %s.buffer.1 to float255 %s.buffer.2 = extractelement <4 x i32> %s.buffer, i32 2256 %s.buffer.2.float = bitcast i32 %s.buffer.2 to float257 %s.buffer.3 = extractelement <4 x i32> %s.buffer, i32 3258 %s.buffer.3.float = bitcast i32 %s.buffer.3 to float259 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %s.buffer.0.float, float %s.buffer.1.float, float %s.buffer.2.float, float %s.buffer.3.float, i1 true, i1 true) #0260 ret void261}262 263; dwordx8 s.buffer.load264; GCN-LABEL: {{^}}s_buffer_load_dwordx8:265; VIGFX9_10: s_buffer_load_dwordx8 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]:[0-9]}}], 0x80266; SICI: s_buffer_load_dwordx8 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]:[0-9]}}], 0x20267define amdgpu_ps void @s_buffer_load_dwordx8(ptr addrspace(4) inreg %arg, ptr addrspace(4) inreg %arg1, ptr addrspace(4) inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, ptr addrspace(4) inreg %in) #0 {268main_body:269 %tmp22 = load <4 x i32>, ptr addrspace(4) %in270 %s.buffer = call <8 x i32> @llvm.amdgcn.s.buffer.load.v8i32(<4 x i32> %tmp22, i32 128, i32 0)271 %s.buffer.0 = extractelement <8 x i32> %s.buffer, i32 0272 %s.buffer.0.float = bitcast i32 %s.buffer.0 to float273 %s.buffer.1 = extractelement <8 x i32> %s.buffer, i32 2274 %s.buffer.1.float = bitcast i32 %s.buffer.1 to float275 %s.buffer.2 = extractelement <8 x i32> %s.buffer, i32 5276 %s.buffer.2.float = bitcast i32 %s.buffer.2 to float277 %s.buffer.3 = extractelement <8 x i32> %s.buffer, i32 7278 %s.buffer.3.float = bitcast i32 %s.buffer.3 to float279 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %s.buffer.0.float, float %s.buffer.1.float, float %s.buffer.2.float, float %s.buffer.3.float, i1 true, i1 true) #0280 ret void281}282 283; dwordx8 s.buffer.load284; GCN-LABEL: {{^}}s_buffer_load_dwordx8_v8f32:285; VIGFX9_10: s_buffer_load_dwordx8 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]:[0-9]}}], 0x80286; SICI: s_buffer_load_dwordx8 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]:[0-9]}}], 0x20287define amdgpu_ps void @s_buffer_load_dwordx8_v8f32(ptr addrspace(4) inreg %arg, ptr addrspace(4) inreg %arg1, ptr addrspace(4) inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, ptr addrspace(4) inreg %in) #0 {288main_body:289 %tmp22 = load <4 x i32>, ptr addrspace(4) %in290 %s.buffer = call <8 x float> @llvm.amdgcn.s.buffer.load.v8f32(<4 x i32> %tmp22, i32 128, i32 0)291 %s.buffer.0 = extractelement <8 x float> %s.buffer, i32 0292 %s.buffer.1 = extractelement <8 x float> %s.buffer, i32 2293 %s.buffer.2 = extractelement <8 x float> %s.buffer, i32 5294 %s.buffer.3 = extractelement <8 x float> %s.buffer, i32 7295 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %s.buffer.0, float %s.buffer.1, float %s.buffer.2, float %s.buffer.3, i1 true, i1 true) #0296 ret void297}298 299; dwordx16 s.buffer.load300; GCN-LABEL: {{^}}s_buffer_load_dwordx16:301; VIGFX9_10: s_buffer_load_dwordx16 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]:[0-9]}}], 0x80302; SICI: s_buffer_load_dwordx16 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]:[0-9]}}], 0x20303define amdgpu_ps void @s_buffer_load_dwordx16(ptr addrspace(4) inreg %arg, ptr addrspace(4) inreg %arg1, ptr addrspace(4) inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, ptr addrspace(4) inreg %in) #0 {304main_body:305 %tmp22 = load <4 x i32>, ptr addrspace(4) %in306 %s.buffer = call <16 x i32> @llvm.amdgcn.s.buffer.load.v16i32(<4 x i32> %tmp22, i32 128, i32 0)307 %s.buffer.0 = extractelement <16 x i32> %s.buffer, i32 0308 %s.buffer.0.float = bitcast i32 %s.buffer.0 to float309 %s.buffer.1 = extractelement <16 x i32> %s.buffer, i32 3310 %s.buffer.1.float = bitcast i32 %s.buffer.1 to float311 %s.buffer.2 = extractelement <16 x i32> %s.buffer, i32 12312 %s.buffer.2.float = bitcast i32 %s.buffer.2 to float313 %s.buffer.3 = extractelement <16 x i32> %s.buffer, i32 15314 %s.buffer.3.float = bitcast i32 %s.buffer.3 to float315 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %s.buffer.0.float, float %s.buffer.1.float, float %s.buffer.2.float, float %s.buffer.3.float, i1 true, i1 true) #0316 ret void317}318 319; GCN-LABEL: {{^}}s_buffer_load_dwordx16_v16f32:320; VIGFX9_10: s_buffer_load_dwordx16 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]:[0-9]}}], 0x80321; SICI: s_buffer_load_dwordx16 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]:[0-9]}}], 0x20322define amdgpu_ps void @s_buffer_load_dwordx16_v16f32(ptr addrspace(4) inreg %arg, ptr addrspace(4) inreg %arg1, ptr addrspace(4) inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, ptr addrspace(4) inreg %in) #0 {323main_body:324 %tmp22 = load <4 x i32>, ptr addrspace(4) %in325 %s.buffer = call <16 x float> @llvm.amdgcn.s.buffer.load.v16f32(<4 x i32> %tmp22, i32 128, i32 0)326 %s.buffer.0 = extractelement <16 x float> %s.buffer, i32 0327 %s.buffer.1 = extractelement <16 x float> %s.buffer, i32 3328 %s.buffer.2 = extractelement <16 x float> %s.buffer, i32 12329 %s.buffer.3 = extractelement <16 x float> %s.buffer, i32 15330 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %s.buffer.0, float %s.buffer.1, float %s.buffer.2, float %s.buffer.3, i1 true, i1 true) #0331 ret void332}333 334; GCN-LABEL: {{^}}smrd_sgpr_offset:335; GCN: s_buffer_load_dword s{{[0-9]}}, s[0:3], s4336define amdgpu_ps float @smrd_sgpr_offset(<4 x i32> inreg %desc, i32 inreg %offset) #0 {337main_body:338 %r = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %desc, i32 %offset, i32 0)339 ret float %r340}341 342; GCN-LABEL: {{^}}smrd_vgpr_offset:343; GCN: buffer_load_dword v{{[0-9]}}, v0, s[0:3], 0 offen ;344define amdgpu_ps float @smrd_vgpr_offset(<4 x i32> inreg %desc, i32 %offset) #0 {345main_body:346 %r = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %desc, i32 %offset, i32 0)347 ret float %r348}349 350; GCN-LABEL: {{^}}smrd_vgpr_offset_imm:351; GCN-NEXT: %bb.352; GCN-NEXT: buffer_load_dword v{{[0-9]}}, v0, s[0:3], 0 offen offset:4092 ;353define amdgpu_ps float @smrd_vgpr_offset_imm(<4 x i32> inreg %desc, i32 %offset) #0 {354main_body:355 %off = add i32 %offset, 4092356 %r = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %desc, i32 %off, i32 0)357 ret float %r358}359 360; GCN-LABEL: {{^}}smrd_vgpr_offset_imm_too_large:361; GCN-NEXT: %bb.362; SICI-NEXT: v_add_{{i|u}}32_e32 v0, {{(vcc, )?}}0x1000, v0363; SICI-NEXT: buffer_load_dword v{{[0-9]}}, v0, s[0:3], 0 offen ;364; VIGFX9_10-NEXT: buffer_load_dword v{{[0-9]}}, v0, s[0:3], 4 offen offset:4092 ;365define amdgpu_ps float @smrd_vgpr_offset_imm_too_large(<4 x i32> inreg %desc, i32 %offset) #0 {366main_body:367 %off = add i32 %offset, 4096368 %r = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %desc, i32 %off, i32 0)369 ret float %r370}371 372; GCN-LABEL: {{^}}smrd_imm_merged:373; GCN-NEXT: %bb.374; SICI-NEXT: s_buffer_load_dwordx4 s[{{[0-9]}}:{{[0-9]}}], s[0:3], 0x1375; SICI-NEXT: s_buffer_load_dwordx2 s[{{[0-9]}}:{{[0-9]}}], s[0:3], 0x7376; GFX10-NEXT: s_clause377; VIGFX9_10-NEXT: s_buffer_load_dwordx4 s[{{[0-9]}}:{{[0-9]}}], s[0:3], 0x4378; VIGFX9_10-NEXT: s_buffer_load_dwordx2 s[{{[0-9]}}:{{[0-9]}}], s[0:3], 0x1c379define amdgpu_ps void @smrd_imm_merged(<4 x i32> inreg %desc) #0 {380main_body:381 %r1 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %desc, i32 4, i32 0)382 %r2 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %desc, i32 8, i32 0)383 %r3 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %desc, i32 12, i32 0)384 %r4 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %desc, i32 16, i32 0)385 %r5 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %desc, i32 28, i32 0)386 %r6 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %desc, i32 32, i32 0)387 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true) #0388 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float poison, float poison, i1 true, i1 true) #0389 ret void390}391 392; GCN-LABEL: {{^}}smrd_imm_merge_m0:393;394; GCN: s_buffer_load_dwordx2395; SICIVI: s_mov_b32 m0396; SICIVI-DAG: v_interp_p1_f32397; SICIVI-DAG: v_interp_p1_f32398; SICIVI-DAG: v_interp_p1_f32399; SICIVI-DAG: v_interp_p2_f32400; SICIVI-DAG: v_interp_p2_f32401; SICIVI-DAG: v_interp_p2_f32402;403; extractelement does not result in movrels anymore for vectors gitting 8 dwords404; SICIVI-NOT: s_mov_b32 m0405; SICIVI-NOT: v_movrels_b32_e32406; v_cndmask_b32_e32407; v_cndmask_b32_e32408;409; Merging is still thwarted on GFX9 due to s_set_gpr_idx410;411define amdgpu_ps float @smrd_imm_merge_m0(<4 x i32> inreg %desc, i32 inreg %prim, float %u, float %v) #0 {412main_body:413 %idx1.f = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %desc, i32 0, i32 0)414 %idx1 = bitcast float %idx1.f to i32415 416 %v0.x1 = call nsz float @llvm.amdgcn.interp.p1(float %u, i32 0, i32 0, i32 %prim)417 %v0.x = call nsz float @llvm.amdgcn.interp.p2(float %v0.x1, float %v, i32 0, i32 0, i32 %prim)418 %v0.y1 = call nsz float @llvm.amdgcn.interp.p1(float %u, i32 0, i32 1, i32 %prim)419 %v0.y = call nsz float @llvm.amdgcn.interp.p2(float %v0.y1, float %v, i32 0, i32 1, i32 %prim)420 %v0.z1 = call nsz float @llvm.amdgcn.interp.p1(float %u, i32 0, i32 2, i32 %prim)421 %v0.z = call nsz float @llvm.amdgcn.interp.p2(float %v0.z1, float %v, i32 0, i32 2, i32 %prim)422 %v0.tmp0 = insertelement <3 x float> poison, float %v0.x, i32 0423 %v0.tmp1 = insertelement <3 x float> %v0.tmp0, float %v0.y, i32 1424 %v0 = insertelement <3 x float> %v0.tmp1, float %v0.z, i32 2425 %a = extractelement <3 x float> %v0, i32 %idx1426 427 %v1.x1 = call nsz float @llvm.amdgcn.interp.p1(float %u, i32 1, i32 0, i32 %prim)428 %v1.x = call nsz float @llvm.amdgcn.interp.p2(float %v1.x1, float %v, i32 1, i32 0, i32 %prim)429 %v1.y1 = call nsz float @llvm.amdgcn.interp.p1(float %u, i32 1, i32 1, i32 %prim)430 %v1.y = call nsz float @llvm.amdgcn.interp.p2(float %v1.y1, float %v, i32 1, i32 1, i32 %prim)431 %v1.z1 = call nsz float @llvm.amdgcn.interp.p1(float %u, i32 1, i32 2, i32 %prim)432 %v1.z = call nsz float @llvm.amdgcn.interp.p2(float %v1.z1, float %v, i32 1, i32 2, i32 %prim)433 %v1.tmp0 = insertelement <3 x float> poison, float %v0.x, i32 0434 %v1.tmp1 = insertelement <3 x float> %v0.tmp0, float %v0.y, i32 1435 %v1 = insertelement <3 x float> %v0.tmp1, float %v0.z, i32 2436 437 %b = extractelement <3 x float> %v1, i32 %idx1438 %c = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %desc, i32 4, i32 0)439 440 %res.tmp = fadd float %a, %b441 %res = fadd float %res.tmp, %c442 ret float %res443}444 445; GCN-LABEL: {{^}}smrd_vgpr_merged:446; GCN-NEXT: %bb.447; GFX10-NEXT: s_clause448; GCN-NEXT: buffer_load_dwordx4 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:4449; GCN-NEXT: buffer_load_dwordx2 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:28450define amdgpu_ps void @smrd_vgpr_merged(<4 x i32> inreg %desc, i32 %a) #0 {451main_body:452 %a1 = add i32 %a, 4453 %a2 = add i32 %a, 8454 %a3 = add i32 %a, 12455 %a4 = add i32 %a, 16456 %a5 = add i32 %a, 28457 %a6 = add i32 %a, 32458 %r1 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %desc, i32 %a1, i32 0)459 %r2 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %desc, i32 %a2, i32 0)460 %r3 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %desc, i32 %a3, i32 0)461 %r4 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %desc, i32 %a4, i32 0)462 %r5 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %desc, i32 %a5, i32 0)463 %r6 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %desc, i32 %a6, i32 0)464 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true) #0465 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float poison, float poison, i1 true, i1 true) #0466 ret void467}468 469; GCN-LABEL: {{^}}smrd_sgpr_descriptor_promoted470; GCN: v_readfirstlane471define amdgpu_cs void @smrd_sgpr_descriptor_promoted(ptr addrspace(4) inreg noalias dereferenceable(18446744073709551615), i32) #0 {472main_body:473 br label %.outer_loop_header474 475ret_block: ; preds = %.outer, %.label22, %main_body476 ret void477 478.outer_loop_header:479 br label %.inner_loop_header480 481.inner_loop_header: ; preds = %.inner_loop_body, %.outer_loop_header482 %loopctr.1 = phi i32 [ 0, %.outer_loop_header ], [ %loopctr.2, %.inner_loop_body ]483 %loopctr.2 = add i32 %loopctr.1, 1484 %inner_br1 = icmp slt i32 %loopctr.2, 10485 br i1 %inner_br1, label %.inner_loop_body, label %ret_block486 487.inner_loop_body:488 %descriptor = load <4 x i32>, ptr addrspace(4) %0, align 16, !invariant.load !0489 %load1result = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %descriptor, i32 0, i32 0)490 store float %load1result, ptr addrspace(1) poison491 %inner_br2 = icmp uge i32 %1, 10492 br i1 %inner_br2, label %.inner_loop_header, label %.outer_loop_body493 494.outer_loop_body:495 %offset = shl i32 %loopctr.2, 6496 %load2result = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %descriptor, i32 %offset, i32 0)497 %outer_br = fcmp ueq float %load2result, 0x0498 br i1 %outer_br, label %.outer_loop_header, label %ret_block499}500 501; SMRD load with a non-const offset502; GCN-LABEL: {{^}}smrd_load_nonconst0:503; SIVIGFX9_10: s_buffer_load_dword s{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}}504; SIVIGFX9_10: s_buffer_load_dword s{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}}505; CI: s_buffer_load_dword s{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}}506; CI: s_buffer_load_dword s{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}}507; GCN: s_endpgm508define amdgpu_ps void @smrd_load_nonconst0(ptr addrspace(4) inreg %arg, ptr addrspace(4) inreg %arg1, ptr addrspace(4) inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, ptr addrspace(4) inreg %in, i32 inreg %ncoff) #0 {509main_body:510 %tmp20 = load <4 x i32>, ptr addrspace(4) %arg511 %tmp21 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 %ncoff, i32 0)512 %tmp22 = load <4 x i32>, ptr addrspace(4) %in513 %s.buffer = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %tmp22, i32 %ncoff, i32 0)514 %s.buffer.float = bitcast i32 %s.buffer to float515 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %tmp21, float %tmp21, float %tmp21, float %s.buffer.float, i1 true, i1 true) #0516 ret void517}518 519; SMRD load with a non-const non-uniform offset520; GCN-LABEL: {{^}}smrd_load_nonconst1:521; SIVIGFX9_10: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen522; SIVIGFX9_10: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen523; CI: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen524; CI: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen525; GCN: s_endpgm526define amdgpu_ps void @smrd_load_nonconst1(ptr addrspace(4) inreg %arg, ptr addrspace(4) inreg %arg1, ptr addrspace(4) inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, ptr addrspace(4) inreg %in, i32 %ncoff) #0 {527main_body:528 %tmp20 = load <4 x i32>, ptr addrspace(4) %arg529 %tmp21 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 %ncoff, i32 0)530 %tmp22 = load <4 x i32>, ptr addrspace(4) %in531 %s.buffer = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %tmp22, i32 %ncoff, i32 0)532 %s.buffer.float = bitcast i32 %s.buffer to float533 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %tmp21, float %tmp21, float %tmp21, float %s.buffer.float, i1 true, i1 true) #0534 ret void535}536 537; SMRD load with a non-const non-uniform offset of > 4 dwords (requires splitting)538; GCN-LABEL: {{^}}smrd_load_nonconst2:539; SIVIGFX9_10-DAG: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen540; SIVIGFX9_10-DAG: buffer_load_dwordx4 v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen541; CI: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen542; CI: buffer_load_dwordx4 v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen543; GCN: s_endpgm544define amdgpu_ps void @smrd_load_nonconst2(ptr addrspace(4) inreg %arg, ptr addrspace(4) inreg %arg1, ptr addrspace(4) inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, ptr addrspace(4) inreg %in, i32 %ncoff) #0 {545main_body:546 %tmp20 = load <4 x i32>, ptr addrspace(4) %arg547 %tmp21 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 %ncoff, i32 0)548 %tmp22 = load <4 x i32>, ptr addrspace(4) %in549 %s.buffer = call <8 x i32> @llvm.amdgcn.s.buffer.load.v8i32(<4 x i32> %tmp22, i32 %ncoff, i32 0)550 %s.buffer.elt = extractelement <8 x i32> %s.buffer, i32 1551 %s.buffer.float = bitcast i32 %s.buffer.elt to float552 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %tmp21, float %tmp21, float %tmp21, float %s.buffer.float, i1 true, i1 true) #0553 ret void554}555 556; SMRD load with a non-const non-uniform offset of > 4 dwords (requires splitting)557; GCN-LABEL: {{^}}smrd_load_nonconst3:558; GCN-DAG: buffer_load_dwordx4 v[0:3], v{{[0-9]+}}, s[0:3], 0 offen ;559; GCN-DAG: buffer_load_dwordx4 v[4:7], v{{[0-9]+}}, s[0:3], 0 offen offset:16 ;560; GCN-DAG: buffer_load_dwordx4 v[8:11], v{{[0-9]+}}, s[0:3], 0 offen offset:32 ;561; GCN-DAG: buffer_load_dwordx4 v[12:15], v{{[0-9]+}}, s[0:3], 0 offen offset:48 ;562; GCN: ; return to shader part epilog563define amdgpu_ps <16 x float> @smrd_load_nonconst3(<4 x i32> inreg %rsrc, i32 %off) #0 {564main_body:565 %ld = call <16 x i32> @llvm.amdgcn.s.buffer.load.v16i32(<4 x i32> %rsrc, i32 %off, i32 0)566 %bc = bitcast <16 x i32> %ld to <16 x float>567 ret <16 x float> %bc568}569 570; GCN-LABEL: {{^}}smrd_load_nonconst4:571; SICI: v_add_i32_e32 v{{[0-9]+}}, vcc, 0xff8, v0 ;572; SICI-DAG: buffer_load_dwordx4 v[0:3], v{{[0-9]+}}, s[0:3], 0 offen ;573; SICI-DAG: buffer_load_dwordx4 v[4:7], v{{[0-9]+}}, s[0:3], 0 offen offset:16 ;574; SICI-DAG: buffer_load_dwordx4 v[8:11], v{{[0-9]+}}, s[0:3], 0 offen offset:32 ;575; SICI-DAG: buffer_load_dwordx4 v[12:15], v{{[0-9]+}}, s[0:3], 0 offen offset:48 ;576; VIGFX9_10-DAG: buffer_load_dwordx4 v[0:3], v{{[0-9]+}}, s[0:3], 56 offen offset:4032 ;577; VIGFX9_10-DAG: buffer_load_dwordx4 v[4:7], v{{[0-9]+}}, s[0:3], 56 offen offset:4048 ;578; VIGFX9_10-DAG: buffer_load_dwordx4 v[8:11], v{{[0-9]+}}, s[0:3], 56 offen offset:4064 ;579; VIGFX9_10-DAG: buffer_load_dwordx4 v[12:15], v{{[0-9]+}}, s[0:3], 56 offen offset:4080 ;580; GCN: ; return to shader part epilog581define amdgpu_ps <16 x float> @smrd_load_nonconst4(<4 x i32> inreg %rsrc, i32 %off) #0 {582main_body:583 %off.2 = add i32 %off, 4088584 %ld = call <16 x i32> @llvm.amdgcn.s.buffer.load.v16i32(<4 x i32> %rsrc, i32 %off.2, i32 0)585 %bc = bitcast <16 x i32> %ld to <16 x float>586 ret <16 x float> %bc587}588 589; GCN-LABEL: {{^}}smrd_load_nonconst5:590; SICI: v_add_i32_e32 v{{[0-9]+}}, vcc, 0x1004, v0591; SICI-DAG: buffer_load_dwordx4 v[0:3], v{{[0-9]+}}, s[0:3], 0 offen ;592; SICI-DAG: buffer_load_dwordx4 v[4:7], v{{[0-9]+}}, s[0:3], 0 offen offset:16 ;593; SICI-DAG: buffer_load_dwordx4 v[8:11], v{{[0-9]+}}, s[0:3], 0 offen offset:32 ;594; SICI-DAG: buffer_load_dwordx4 v[12:15], v{{[0-9]+}}, s[0:3], 0 offen offset:48 ;595; VIGFX9_10: s_movk_i32 s4, 0xfc0596; VIGFX9_10-DAG: buffer_load_dwordx4 v[0:3], v{{[0-9]+}}, s[0:3], s4 offen offset:68 ;597; VIGFX9_10-DAG: buffer_load_dwordx4 v[4:7], v{{[0-9]+}}, s[0:3], s4 offen offset:84 ;598; VIGFX9_10-DAG: buffer_load_dwordx4 v[8:11], v{{[0-9]+}}, s[0:3], s4 offen offset:100 ;599; VIGFX9_10-DAG: buffer_load_dwordx4 v[12:15], v{{[0-9]+}}, s[0:3], s4 offen offset:116 ;600; GCN: ; return to shader part epilog601define amdgpu_ps <16 x float> @smrd_load_nonconst5(<4 x i32> inreg %rsrc, i32 %off) #0 {602main_body:603 %off.2 = add i32 %off, 4100604 %ld = call <16 x i32> @llvm.amdgcn.s.buffer.load.v16i32(<4 x i32> %rsrc, i32 %off.2, i32 0)605 %bc = bitcast <16 x i32> %ld to <16 x float>606 ret <16 x float> %bc607}608 609; SMRD load dwordx2610; GCN-LABEL: {{^}}smrd_load_dwordx2:611; SIVIGFX9_10: s_buffer_load_dwordx2 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}}612; CI: s_buffer_load_dwordx2 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}}613; GCN: s_endpgm614define amdgpu_ps void @smrd_load_dwordx2(ptr addrspace(4) inreg %arg, ptr addrspace(4) inreg %arg1, ptr addrspace(4) inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, ptr addrspace(4) inreg %in, i32 inreg %ncoff) #0 {615main_body:616 %tmp22 = load <4 x i32>, ptr addrspace(4) %in617 %s.buffer = call <2 x i32> @llvm.amdgcn.s.buffer.load.v2i32(<4 x i32> %tmp22, i32 %ncoff, i32 0)618 %s.buffer.float = bitcast <2 x i32> %s.buffer to <2 x float>619 %r.1 = extractelement <2 x float> %s.buffer.float, i32 0620 %r.2 = extractelement <2 x float> %s.buffer.float, i32 1621 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r.1, float %r.1, float %r.1, float %r.2, i1 true, i1 true) #0622 ret void623}624 625; GCN-LABEL: {{^}}smrd_uniform_loop:626;627; TODO: we should keep the loop counter in an SGPR628;629; GCN: s_buffer_load_dword630define amdgpu_ps float @smrd_uniform_loop(<4 x i32> inreg %desc, i32 %bound) #0 {631main_body:632 br label %loop633 634loop:635 %counter = phi i32 [ 0, %main_body ], [ %counter.next, %loop ]636 %sum = phi float [ 0.0, %main_body ], [ %sum.next, %loop ]637 %offset = shl i32 %counter, 2638 %v = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %desc, i32 %offset, i32 0)639 %sum.next = fadd float %sum, %v640 %counter.next = add i32 %counter, 1641 %cc = icmp uge i32 %counter.next, %bound642 br i1 %cc, label %exit, label %loop643 644exit:645 ret float %sum.next646}647 648 649; GCN-LABEL: {{^}}smrd_uniform_loop2:650; (this test differs from smrd_uniform_loop by the more complex structure of phis)651;652; TODO: we should keep the loop counter in an SGPR and use an S_BUFFER_LOAD653;654; GCN: buffer_load_dword655define amdgpu_ps float @smrd_uniform_loop2(<4 x i32> inreg %desc, i32 %bound, i32 %bound.a) #0 {656main_body:657 br label %loop658 659loop:660 %counter = phi i32 [ 0, %main_body ], [ %counter.next, %loop.a ], [ %counter.next, %loop.b ]661 %sum = phi float [ 0.0, %main_body ], [ %sum.next, %loop.a ], [ %sum.next.b, %loop.b ]662 %offset = shl i32 %counter, 2663 %v = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %desc, i32 %offset, i32 0)664 %sum.next = fadd float %sum, %v665 %counter.next = add i32 %counter, 1666 %cc = icmp uge i32 %counter.next, %bound667 br i1 %cc, label %exit, label %loop.a668 669loop.a:670 %cc.a = icmp uge i32 %counter.next, %bound.a671 br i1 %cc, label %loop, label %loop.b672 673loop.b:674 %sum.next.b = fadd float %sum.next, 1.0675 br label %loop676 677exit:678 ret float %sum.next679}680 681; This test checks that the load after some control flow with an offset based682; on a divergent shader input is correctly recognized as divergent. This was683; reduced from an actual regression. Yes, the %unused argument matters, as684; well as the fact that %arg4 is a vector.685;686; GCN-LABEL: {{^}}arg_divergence:687; GCN: buffer_load_dword v0, v0,688; GCN-NEXT: s_waitcnt689; GCN-NEXT: ; return to shader part epilog690define amdgpu_cs float @arg_divergence(i32 inreg %cmp, <3 x i32> %arg4) #0 {691main_body:692 %uniform.cond = icmp eq i32 %cmp, 0693 br i1 %uniform.cond, label %endif1, label %if1694 695if1: ; preds = %main_body696 store i32 0, ptr addrspace(3) poison, align 4697 br label %endif1698 699endif1: ; preds = %if1, %main_body700 %tmp13 = extractelement <3 x i32> %arg4, i32 0701 %tmp97 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> poison, i32 %tmp13, i32 0)702 ret float %tmp97703}704 705; GCN-LABEL: {{^}}s_buffer_load_f32:706; GCN: s_buffer_load_dword s0, s[0:3], s4707define amdgpu_ps void @s_buffer_load_f32(<4 x i32> inreg %rsrc, i32 inreg %offset) {708 %sgpr = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 %offset, i32 0)709 call void asm sideeffect "; use $0", "s"(float %sgpr)710 ret void711}712 713; GCN-LABEL: {{^}}s_buffer_load_v2f32:714; GCN: s_buffer_load_dwordx2 s[0:1], s[0:3], s4715define amdgpu_ps void @s_buffer_load_v2f32(<4 x i32> inreg %rsrc, i32 inreg %offset) {716 %sgpr = call <2 x float> @llvm.amdgcn.s.buffer.load.v2f32(<4 x i32> %rsrc, i32 %offset, i32 0)717 call void asm sideeffect "; use $0", "s"(<2 x float> %sgpr)718 ret void719}720 721; GCN-LABEL: {{^}}s_buffer_load_v4f32:722; GCN: s_buffer_load_dwordx4 s[0:3], s[0:3], s4723define amdgpu_ps void @s_buffer_load_v4f32(<4 x i32> inreg %rsrc, i32 inreg %offset) {724 %sgpr = call <4 x float> @llvm.amdgcn.s.buffer.load.v4f32(<4 x i32> %rsrc, i32 %offset, i32 0)725 call void asm sideeffect "; use $0", "s"(<4 x float> %sgpr)726 ret void727}728 729; GCN-LABEL: {{^}}s_buffer_load_v8f32:730; GCN: s_buffer_load_dwordx8 s[0:7], s[0:3], s4731define amdgpu_ps void @s_buffer_load_v8f32(<4 x i32> inreg %rsrc, i32 inreg %offset) {732 %sgpr = call <8 x float> @llvm.amdgcn.s.buffer.load.v8f32(<4 x i32> %rsrc, i32 %offset, i32 0)733 call void asm sideeffect "; use $0", "s"(<8 x float> %sgpr)734 ret void735}736 737; GCN-LABEL: {{^}}s_buffer_load_v16f32:738; GCN: s_buffer_load_dwordx16 s[0:15], s[0:3], s4739define amdgpu_ps void @s_buffer_load_v16f32(<4 x i32> inreg %rsrc, i32 inreg %offset) {740 %sgpr = call <16 x float> @llvm.amdgcn.s.buffer.load.v16f32(<4 x i32> %rsrc, i32 %offset, i32 0)741 call void asm sideeffect "; use $0", "s"(<16 x float> %sgpr)742 ret void743}744 745declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0746declare float @llvm.amdgcn.interp.p1(float, i32, i32, i32) #2747declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32) #2748 749declare i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32>, i32, i32) #1750declare <2 x i32> @llvm.amdgcn.s.buffer.load.v2i32(<4 x i32>, i32, i32)751declare <4 x i32> @llvm.amdgcn.s.buffer.load.v4i32(<4 x i32>, i32, i32)752declare <8 x i32> @llvm.amdgcn.s.buffer.load.v8i32(<4 x i32>, i32, i32)753declare <16 x i32> @llvm.amdgcn.s.buffer.load.v16i32(<4 x i32>, i32, i32)754 755declare float @llvm.amdgcn.s.buffer.load.f32(<4 x i32>, i32, i32)756declare <2 x float> @llvm.amdgcn.s.buffer.load.v2f32(<4 x i32>, i32, i32)757declare <4 x float> @llvm.amdgcn.s.buffer.load.v4f32(<4 x i32>, i32, i32)758declare <8 x float> @llvm.amdgcn.s.buffer.load.v8f32(<4 x i32>, i32, i32)759declare <16 x float> @llvm.amdgcn.s.buffer.load.v16f32(<4 x i32>, i32, i32)760 761attributes #0 = { nounwind }762attributes #1 = { nounwind readnone }763attributes #2 = { nounwind readnone speculatable }764 765!0 = !{}766