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1; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tahiti < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s2; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s3 4; Since this intrinsic is exposed as a constant after isel, use it to5; defeat the DAG's compare with constant canonicalizations.6declare i32 @llvm.amdgcn.groupstaticsize() #17 8@lds = addrspace(3) global [512 x i32] poison, align 49 10; GCN-LABEL: {{^}}br_scc_eq_i32_inline_imm:11; GCN: s_cmp_eq_u32 s{{[0-9]+}}, 4{{$}}12define amdgpu_kernel void @br_scc_eq_i32_inline_imm(i32 %cond, ptr addrspace(1) %out) #0 {13entry:14 %cmp0 = icmp eq i32 %cond, 415 br i1 %cmp0, label %endif, label %if16 17if:18 call void asm sideeffect "", ""()19 br label %endif20 21endif:22 store volatile i32 1, ptr addrspace(1) %out23 ret void24}25 26; GCN-LABEL: {{^}}br_scc_eq_i32_simm16_max:27; GCN: s_cmpk_eq_i32 s{{[0-9]+}}, 0x7fff{{$}}28define amdgpu_kernel void @br_scc_eq_i32_simm16_max(i32 %cond, ptr addrspace(1) %out) #0 {29entry:30 %cmp0 = icmp eq i32 %cond, 3276731 br i1 %cmp0, label %endif, label %if32 33if:34 call void asm sideeffect "", ""()35 br label %endif36 37endif:38 store volatile i32 1, ptr addrspace(1) %out39 ret void40}41 42; GCN-LABEL: {{^}}br_scc_eq_i32_simm16_max_p1:43; GCN: s_cmpk_eq_u32 s{{[0-9]+}}, 0x8000{{$}}44define amdgpu_kernel void @br_scc_eq_i32_simm16_max_p1(i32 %cond, ptr addrspace(1) %out) #0 {45entry:46 %cmp0 = icmp eq i32 %cond, 3276847 br i1 %cmp0, label %endif, label %if48 49if:50 call void asm sideeffect "", ""()51 br label %endif52 53endif:54 store volatile i32 1, ptr addrspace(1) %out55 ret void56}57 58; GCN-LABEL: {{^}}br_scc_ne_i32_simm16_max_p1:59; GCN: s_cmpk_lg_u32 s{{[0-9]+}}, 0x8000{{$}}60define amdgpu_kernel void @br_scc_ne_i32_simm16_max_p1(i32 %cond, ptr addrspace(1) %out) #0 {61entry:62 %cmp0 = icmp ne i32 %cond, 3276863 br i1 %cmp0, label %endif, label %if64 65if:66 call void asm sideeffect "", ""()67 br label %endif68 69endif:70 store volatile i32 1, ptr addrspace(1) %out71 ret void72}73 74; GCN-LABEL: {{^}}br_scc_eq_i32_simm16_min:75; GCN: s_cmpk_eq_i32 s{{[0-9]+}}, 0x8000{{$}}76define amdgpu_kernel void @br_scc_eq_i32_simm16_min(i32 %cond, ptr addrspace(1) %out) #0 {77entry:78 %cmp0 = icmp eq i32 %cond, -3276879 br i1 %cmp0, label %endif, label %if80 81if:82 call void asm sideeffect "", ""()83 br label %endif84 85endif:86 store volatile i32 1, ptr addrspace(1) %out87 ret void88}89 90; GCN-LABEL: {{^}}br_scc_eq_i32_simm16_min_m1:91; GCN: s_cmp_eq_u32 s{{[0-9]+}}, 0xffff7fff{{$}}92define amdgpu_kernel void @br_scc_eq_i32_simm16_min_m1(i32 %cond, ptr addrspace(1) %out) #0 {93entry:94 %cmp0 = icmp eq i32 %cond, -3276995 br i1 %cmp0, label %endif, label %if96 97if:98 call void asm sideeffect "", ""()99 br label %endif100 101endif:102 store volatile i32 1, ptr addrspace(1) %out103 ret void104}105 106; GCN-LABEL: {{^}}br_scc_eq_i32_uimm15_max:107; GCN: s_cmpk_eq_u32 s{{[0-9]+}}, 0xffff{{$}}108define amdgpu_kernel void @br_scc_eq_i32_uimm15_max(i32 %cond, ptr addrspace(1) %out) #0 {109entry:110 %cmp0 = icmp eq i32 %cond, 65535111 br i1 %cmp0, label %endif, label %if112 113if:114 call void asm sideeffect "", ""()115 br label %endif116 117endif:118 store volatile i32 1, ptr addrspace(1) %out119 ret void120}121 122; GCN-LABEL: {{^}}br_scc_eq_i32_uimm16_max:123; GCN: s_cmpk_eq_u32 s{{[0-9]+}}, 0xffff{{$}}124define amdgpu_kernel void @br_scc_eq_i32_uimm16_max(i32 %cond, ptr addrspace(1) %out) #0 {125entry:126 %cmp0 = icmp eq i32 %cond, 65535127 br i1 %cmp0, label %endif, label %if128 129if:130 call void asm sideeffect "", ""()131 br label %endif132 133endif:134 store volatile i32 1, ptr addrspace(1) %out135 ret void136}137 138; GCN-LABEL: {{^}}br_scc_eq_i32_uimm16_max_p1:139; GCN: s_cmp_eq_u32 s{{[0-9]+}}, 0x10000{{$}}140define amdgpu_kernel void @br_scc_eq_i32_uimm16_max_p1(i32 %cond, ptr addrspace(1) %out) #0 {141entry:142 %cmp0 = icmp eq i32 %cond, 65536143 br i1 %cmp0, label %endif, label %if144 145if:146 call void asm sideeffect "", ""()147 br label %endif148 149endif:150 store volatile i32 1, ptr addrspace(1) %out151 ret void152}153 154 155; GCN-LABEL: {{^}}br_scc_eq_i32:156; GCN: s_cmpk_eq_i32 s{{[0-9]+}}, 0x41{{$}}157define amdgpu_kernel void @br_scc_eq_i32(i32 %cond, ptr addrspace(1) %out) #0 {158entry:159 %cmp0 = icmp eq i32 %cond, 65160 br i1 %cmp0, label %endif, label %if161 162if:163 call void asm sideeffect "", ""()164 br label %endif165 166endif:167 store volatile i32 1, ptr addrspace(1) %out168 ret void169}170 171; GCN-LABEL: {{^}}br_scc_ne_i32:172; GCN: s_cmpk_lg_i32 s{{[0-9]+}}, 0x41{{$}}173define amdgpu_kernel void @br_scc_ne_i32(i32 %cond, ptr addrspace(1) %out) #0 {174entry:175 %cmp0 = icmp ne i32 %cond, 65176 br i1 %cmp0, label %endif, label %if177 178if:179 call void asm sideeffect "", ""()180 br label %endif181 182endif:183 store volatile i32 1, ptr addrspace(1) %out184 ret void185}186 187; GCN-LABEL: {{^}}br_scc_sgt_i32:188; GCN: s_cmpk_gt_i32 s{{[0-9]+}}, 0x41{{$}}189define amdgpu_kernel void @br_scc_sgt_i32(i32 %cond, ptr addrspace(1) %out) #0 {190entry:191 %cmp0 = icmp sgt i32 %cond, 65192 br i1 %cmp0, label %endif, label %if193 194if:195 call void asm sideeffect "", ""()196 br label %endif197 198endif:199 store volatile i32 1, ptr addrspace(1) %out200 ret void201}202 203; GCN-LABEL: {{^}}br_scc_sgt_i32_simm16_max:204; GCN: s_cmpk_gt_i32 s{{[0-9]+}}, 0x7fff{{$}}205define amdgpu_kernel void @br_scc_sgt_i32_simm16_max(i32 %cond, ptr addrspace(1) %out) #0 {206entry:207 %cmp0 = icmp sgt i32 %cond, 32767208 br i1 %cmp0, label %endif, label %if209 210if:211 call void asm sideeffect "", ""()212 br label %endif213 214endif:215 store volatile i32 1, ptr addrspace(1) %out216 ret void217}218 219; GCN-LABEL: {{^}}br_scc_sgt_i32_simm16_max_p1:220; GCN: s_cmp_gt_i32 s{{[0-9]+}}, 0x8000{{$}}221define amdgpu_kernel void @br_scc_sgt_i32_simm16_max_p1(i32 %cond, ptr addrspace(1) %out) #0 {222entry:223 %cmp0 = icmp sgt i32 %cond, 32768224 br i1 %cmp0, label %endif, label %if225 226if:227 call void asm sideeffect "", ""()228 br label %endif229 230endif:231 store volatile i32 1, ptr addrspace(1) %out232 ret void233}234 235; GCN-LABEL: {{^}}br_scc_sge_i32:236; GCN: s_cmpk_ge_i32 s{{[0-9]+}}, 0x800{{$}}237define amdgpu_kernel void @br_scc_sge_i32(i32 %cond, ptr addrspace(1) %out) #0 {238entry:239 %size = call i32 @llvm.amdgcn.groupstaticsize()240 %cmp0 = icmp sge i32 %cond, %size241 br i1 %cmp0, label %endif, label %if242 243if:244 call void asm sideeffect "; $0", "v"(ptr addrspace(3) @lds)245 br label %endif246 247endif:248 store volatile i32 1, ptr addrspace(1) %out249 ret void250}251 252; GCN-LABEL: {{^}}br_scc_slt_i32:253; GCN: s_cmpk_lt_i32 s{{[0-9]+}}, 0x41{{$}}254define amdgpu_kernel void @br_scc_slt_i32(i32 %cond, ptr addrspace(1) %out) #0 {255entry:256 %cmp0 = icmp slt i32 %cond, 65257 br i1 %cmp0, label %endif, label %if258 259if:260 call void asm sideeffect "", ""()261 br label %endif262 263endif:264 store volatile i32 1, ptr addrspace(1) %out265 ret void266}267 268; GCN-LABEL: {{^}}br_scc_sle_i32:269; GCN: s_cmpk_le_i32 s{{[0-9]+}}, 0x800{{$}}270define amdgpu_kernel void @br_scc_sle_i32(i32 %cond, ptr addrspace(1) %out) #0 {271entry:272 %size = call i32 @llvm.amdgcn.groupstaticsize()273 %cmp0 = icmp sle i32 %cond, %size274 br i1 %cmp0, label %endif, label %if275 276if:277 call void asm sideeffect "; $0", "v"(ptr addrspace(3) @lds)278 br label %endif279 280endif:281 store volatile i32 1, ptr addrspace(1) %out282 ret void283}284 285; GCN-LABEL: {{^}}br_scc_ugt_i32:286; GCN: s_cmpk_gt_u32 s{{[0-9]+}}, 0x800{{$}}287define amdgpu_kernel void @br_scc_ugt_i32(i32 %cond, ptr addrspace(1) %out) #0 {288entry:289 %size = call i32 @llvm.amdgcn.groupstaticsize()290 %cmp0 = icmp ugt i32 %cond, %size291 br i1 %cmp0, label %endif, label %if292 293if:294 call void asm sideeffect "; $0", "v"(ptr addrspace(3) @lds)295 br label %endif296 297endif:298 store volatile i32 1, ptr addrspace(1) %out299 ret void300}301 302; GCN-LABEL: {{^}}br_scc_uge_i32:303; GCN: s_cmpk_ge_u32 s{{[0-9]+}}, 0x800{{$}}304define amdgpu_kernel void @br_scc_uge_i32(i32 %cond, ptr addrspace(1) %out) #0 {305entry:306 %size = call i32 @llvm.amdgcn.groupstaticsize()307 %cmp0 = icmp uge i32 %cond, %size308 br i1 %cmp0, label %endif, label %if309 310if:311 call void asm sideeffect "; $0", "v"(ptr addrspace(3) @lds)312 br label %endif313 314endif:315 store volatile i32 1, ptr addrspace(1) %out316 ret void317}318 319; GCN-LABEL: {{^}}br_scc_ult_i32:320; GCN: s_cmpk_lt_u32 s{{[0-9]+}}, 0x41{{$}}321define amdgpu_kernel void @br_scc_ult_i32(i32 %cond, ptr addrspace(1) %out) #0 {322entry:323 %cmp0 = icmp ult i32 %cond, 65324 br i1 %cmp0, label %endif, label %if325 326if:327 call void asm sideeffect "", ""()328 br label %endif329 330endif:331 store volatile i32 1, ptr addrspace(1) %out332 ret void333}334 335; GCN-LABEL: {{^}}br_scc_ult_i32_min_simm16:336; GCN: s_cmp_lt_u32 s{{[0-9]+}}, 0xffff8000337define amdgpu_kernel void @br_scc_ult_i32_min_simm16(i32 %cond, ptr addrspace(1) %out) #0 {338entry:339 %cmp0 = icmp ult i32 %cond, -32768340 br i1 %cmp0, label %endif, label %if341 342if:343 call void asm sideeffect "", ""()344 br label %endif345 346endif:347 store volatile i32 1, ptr addrspace(1) %out348 ret void349}350 351; GCN-LABEL: {{^}}br_scc_ult_i32_min_simm16_m1:352; GCN: s_cmp_lt_u32 s{{[0-9]+}}, 0xffff7fff{{$}}353define amdgpu_kernel void @br_scc_ult_i32_min_simm16_m1(i32 %cond, ptr addrspace(1) %out) #0 {354entry:355 %cmp0 = icmp ult i32 %cond, -32769356 br i1 %cmp0, label %endif, label %if357 358if:359 call void asm sideeffect "", ""()360 br label %endif361 362endif:363 store volatile i32 1, ptr addrspace(1) %out364 ret void365}366 367; GCN-LABEL: {{^}}br_scc_ule_i32:368; GCN: s_cmpk_le_u32 s{{[0-9]+}}, 0x800{{$}}369define amdgpu_kernel void @br_scc_ule_i32(i32 %cond, ptr addrspace(1) %out) #0 {370entry:371 %size = call i32 @llvm.amdgcn.groupstaticsize()372 %cmp0 = icmp ule i32 %cond, %size373 br i1 %cmp0, label %endif, label %if374 375if:376 call void asm sideeffect "; $0", "v"(ptr addrspace(3) @lds)377 br label %endif378 379endif:380 store volatile i32 1, ptr addrspace(1) %out381 ret void382}383 384; GCN-LABEL: {{^}}commute_br_scc_eq_i32:385; GCN: s_cmpk_eq_i32 s{{[0-9]+}}, 0x800{{$}}386define amdgpu_kernel void @commute_br_scc_eq_i32(i32 %cond, ptr addrspace(1) %out) #0 {387entry:388 %size = call i32 @llvm.amdgcn.groupstaticsize()389 %cmp0 = icmp eq i32 %size, %cond390 br i1 %cmp0, label %endif, label %if391 392if:393 call void asm sideeffect "; $0", "v"(ptr addrspace(3) @lds)394 br label %endif395 396endif:397 store volatile i32 1, ptr addrspace(1) %out398 ret void399}400 401; GCN-LABEL: {{^}}commute_br_scc_ne_i32:402; GCN: s_cmpk_lg_i32 s{{[0-9]+}}, 0x800{{$}}403define amdgpu_kernel void @commute_br_scc_ne_i32(i32 %cond, ptr addrspace(1) %out) #0 {404entry:405 %size = call i32 @llvm.amdgcn.groupstaticsize()406 %cmp0 = icmp ne i32 %size, %cond407 br i1 %cmp0, label %endif, label %if408 409if:410 call void asm sideeffect "; $0", "v"(ptr addrspace(3) @lds)411 br label %endif412 413endif:414 store volatile i32 1, ptr addrspace(1) %out415 ret void416}417 418; GCN-LABEL: {{^}}commute_br_scc_sgt_i32:419; GCN: s_cmpk_lt_i32 s{{[0-9]+}}, 0x800{{$}}420define amdgpu_kernel void @commute_br_scc_sgt_i32(i32 %cond, ptr addrspace(1) %out) #0 {421entry:422 %size = call i32 @llvm.amdgcn.groupstaticsize()423 %cmp0 = icmp sgt i32 %size, %cond424 br i1 %cmp0, label %endif, label %if425 426if:427 call void asm sideeffect "; $0", "v"(ptr addrspace(3) @lds)428 br label %endif429 430endif:431 store volatile i32 1, ptr addrspace(1) %out432 ret void433}434 435; GCN-LABEL: {{^}}commute_br_scc_sge_i32:436; GCN: s_cmpk_le_i32 s{{[0-9]+}}, 0x800{{$}}437define amdgpu_kernel void @commute_br_scc_sge_i32(i32 %cond, ptr addrspace(1) %out) #0 {438entry:439 %size = call i32 @llvm.amdgcn.groupstaticsize()440 %cmp0 = icmp sge i32 %size, %cond441 br i1 %cmp0, label %endif, label %if442 443if:444 call void asm sideeffect "; $0", "v"(ptr addrspace(3) @lds)445 br label %endif446 447endif:448 store volatile i32 1, ptr addrspace(1) %out449 ret void450}451 452; GCN-LABEL: {{^}}commute_br_scc_slt_i32:453; GCN: s_cmpk_gt_i32 s{{[0-9]+}}, 0x800{{$}}454define amdgpu_kernel void @commute_br_scc_slt_i32(i32 %cond, ptr addrspace(1) %out) #0 {455entry:456 %size = call i32 @llvm.amdgcn.groupstaticsize()457 %cmp0 = icmp slt i32 %size, %cond458 br i1 %cmp0, label %endif, label %if459 460if:461 call void asm sideeffect "; $0", "v"(ptr addrspace(3) @lds)462 br label %endif463 464endif:465 store volatile i32 1, ptr addrspace(1) %out466 ret void467}468 469; GCN-LABEL: {{^}}commute_br_scc_sle_i32:470; GCN: s_cmpk_ge_i32 s{{[0-9]+}}, 0x800{{$}}471define amdgpu_kernel void @commute_br_scc_sle_i32(i32 %cond, ptr addrspace(1) %out) #0 {472entry:473 %size = call i32 @llvm.amdgcn.groupstaticsize()474 %cmp0 = icmp sle i32 %size, %cond475 br i1 %cmp0, label %endif, label %if476 477if:478 call void asm sideeffect "; $0", "v"(ptr addrspace(3) @lds)479 br label %endif480 481endif:482 store volatile i32 1, ptr addrspace(1) %out483 ret void484}485 486; GCN-LABEL: {{^}}commute_br_scc_ugt_i32:487; GCN: s_cmpk_lt_u32 s{{[0-9]+}}, 0x800{{$}}488define amdgpu_kernel void @commute_br_scc_ugt_i32(i32 %cond, ptr addrspace(1) %out) #0 {489entry:490 %size = call i32 @llvm.amdgcn.groupstaticsize()491 %cmp0 = icmp ugt i32 %size, %cond492 br i1 %cmp0, label %endif, label %if493 494if:495 call void asm sideeffect "; $0", "v"(ptr addrspace(3) @lds)496 br label %endif497 498endif:499 store volatile i32 1, ptr addrspace(1) %out500 ret void501}502 503; GCN-LABEL: {{^}}commute_br_scc_uge_i32:504; GCN: s_cmpk_le_u32 s{{[0-9]+}}, 0x800{{$}}505define amdgpu_kernel void @commute_br_scc_uge_i32(i32 %cond, ptr addrspace(1) %out) #0 {506entry:507 %size = call i32 @llvm.amdgcn.groupstaticsize()508 %cmp0 = icmp uge i32 %size, %cond509 br i1 %cmp0, label %endif, label %if510 511if:512 call void asm sideeffect "; $0", "v"(ptr addrspace(3) @lds)513 br label %endif514 515endif:516 store volatile i32 1, ptr addrspace(1) %out517 ret void518}519 520; GCN-LABEL: {{^}}commute_br_scc_ult_i32:521; GCN: s_cmpk_gt_u32 s{{[0-9]+}}, 0x800{{$}}522define amdgpu_kernel void @commute_br_scc_ult_i32(i32 %cond, ptr addrspace(1) %out) #0 {523entry:524 %size = call i32 @llvm.amdgcn.groupstaticsize()525 %cmp0 = icmp ult i32 %size, %cond526 br i1 %cmp0, label %endif, label %if527 528if:529 call void asm sideeffect "; $0", "v"(ptr addrspace(3) @lds)530 br label %endif531 532endif:533 store volatile i32 1, ptr addrspace(1) %out534 ret void535}536 537; GCN-LABEL: {{^}}commute_br_scc_ule_i32:538; GCN: s_cmpk_ge_u32 s{{[0-9]+}}, 0x800{{$}}539define amdgpu_kernel void @commute_br_scc_ule_i32(i32 %cond, ptr addrspace(1) %out) #0 {540entry:541 %size = call i32 @llvm.amdgcn.groupstaticsize()542 %cmp0 = icmp ule i32 %size, %cond543 br i1 %cmp0, label %endif, label %if544 545if:546 call void asm sideeffect "; $0", "v"(ptr addrspace(3) @lds)547 br label %endif548 549endif:550 store volatile i32 1, ptr addrspace(1) %out551 ret void552}553 554; GCN-LABEL: {{^}}br_scc_ult_i32_non_u16:555; GCN: s_cmp_lt_u32 s{{[0-9]+}}, 0xfffff7ff556define amdgpu_kernel void @br_scc_ult_i32_non_u16(i32 %cond, ptr addrspace(1) %out) #0 {557entry:558 %size = call i32 @llvm.amdgcn.groupstaticsize()559 %not.size = xor i32 %size, -1560 %cmp0 = icmp ult i32 %cond, %not.size561 br i1 %cmp0, label %endif, label %if562 563if:564 call void asm sideeffect "; $0", "v"(ptr addrspace(3) @lds)565 br label %endif566 567endif:568 store volatile i32 1, ptr addrspace(1) %out569 ret void570}571 572; GCN-LABEL: {{^}}br_scc_eq_i64_inline_imm:573; VI: s_cmp_eq_u64 s{{\[[0-9]+:[0-9]+\]}}, 4574 575; SI: v_cmp_eq_u64_e64576define amdgpu_kernel void @br_scc_eq_i64_inline_imm(i64 %cond, ptr addrspace(1) %out) #0 {577entry:578 %cmp0 = icmp eq i64 %cond, 4579 br i1 %cmp0, label %endif, label %if580 581if:582 call void asm sideeffect "", ""()583 br label %endif584 585endif:586 store volatile i32 1, ptr addrspace(1) %out587 ret void588}589 590; GCN-LABEL: {{^}}br_scc_eq_i64_simm16:591; VI-DAG: s_movk_i32 s[[K_LO:[0-9]+]], 0x4d2592; VI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], 1593; VI: s_cmp_eq_u64 s{{\[[0-9]+:[0-9]+\]}}, s[[[K_LO]]:[[K_HI]]]594 595; SI: v_cmp_eq_u64_e32596define amdgpu_kernel void @br_scc_eq_i64_simm16(i64 %cond, ptr addrspace(1) %out) #0 {597entry:598 %cmp0 = icmp eq i64 %cond, 4294968530599 br i1 %cmp0, label %endif, label %if600 601if:602 call void asm sideeffect "", ""()603 br label %endif604 605endif:606 store volatile i32 1, ptr addrspace(1) %out607 ret void608}609 610; GCN-LABEL: {{^}}br_scc_ne_i64_inline_imm:611; VI: s_cmp_lg_u64 s{{\[[0-9]+:[0-9]+\]}}, 4612 613; SI: v_cmp_ne_u64_e64614define amdgpu_kernel void @br_scc_ne_i64_inline_imm(i64 %cond, ptr addrspace(1) %out) #0 {615entry:616 %cmp0 = icmp ne i64 %cond, 4617 br i1 %cmp0, label %endif, label %if618 619if:620 call void asm sideeffect "", ""()621 br label %endif622 623endif:624 store volatile i32 1, ptr addrspace(1) %out625 ret void626}627 628; GCN-LABEL: {{^}}br_scc_ne_i64_simm16:629; VI-DAG: s_movk_i32 s[[K_LO:[0-9]+]], 0x4d2630; VI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], 1631; VI: s_cmp_lg_u64 s{{\[[0-9]+:[0-9]+\]}}, s[[[K_LO]]:[[K_HI]]]632 633; SI: v_cmp_ne_u64_e32634define amdgpu_kernel void @br_scc_ne_i64_simm16(i64 %cond, ptr addrspace(1) %out) #0 {635entry:636 %cmp0 = icmp ne i64 %cond, 4294968530637 br i1 %cmp0, label %endif, label %if638 639if:640 call void asm sideeffect "", ""()641 br label %endif642 643endif:644 store volatile i32 1, ptr addrspace(1) %out645 ret void646}647 648attributes #0 = { nounwind }649attributes #1 = { nounwind readnone }650