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1# REQUIRES: asserts2# RUN: llc -mtriple=amdgcn-- -verify-machineinstrs -debug-only=regalloc -run-pass=greedy -filetype=null %s 2>&1 | FileCheck %s3 4---5# Check that physreg candidate is not used since cannot be spilled in a block,6# e.g. before exec mask preamble7# CHECK: , cannot spill all interferences.8 9name: foo10tracksRegLiveness: true11machineFunctionInfo:12 scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr313 stackPtrOffsetReg: $sgpr3214body: |15 bb.0:16 liveins: $sgpr96_sgpr97, $sgpr98_sgpr99, $sgpr100_sgpr101, $sgpr102_sgpr10317 18 %0:sreg_64 = COPY $sgpr102_sgpr10319 %1:sgpr_128 = COPY $sgpr100_sgpr101_sgpr102_sgpr10320 %2:sgpr_128 = COPY %121 %3:sgpr_128 = COPY %122 %4:sgpr_128 = COPY %123 %5:sgpr_128 = COPY %124 %6:sgpr_128 = COPY %125 %7:sgpr_128 = COPY %126 %8:sgpr_128 = COPY %127 %9:sgpr_128 = COPY %128 %10:sgpr_128 = COPY %129 %11:sgpr_128 = COPY %130 %12:sgpr_128 = COPY %131 %13:sgpr_128 = COPY %132 %14:sgpr_128 = COPY %133 %15:sgpr_128 = COPY %134 %16:sgpr_128 = COPY %135 %17:sgpr_128 = COPY %136 %18:sgpr_128 = COPY %137 %19:sgpr_128 = COPY %138 %20:sgpr_128 = COPY %139 %21:sgpr_128 = COPY %140 %22:sgpr_128 = COPY %141 %23:sgpr_128 = COPY %142 %24:sgpr_128 = COPY %143 %25:sgpr_128 = COPY %144 %26:sgpr_128 = COPY %145 S_BRANCH %bb.146 47 bb.1:48 liveins: $sgpr96_sgpr97, $sgpr98_sgpr99, $sgpr102_sgpr10349 50 %0:sreg_64 = S_OR_SAVEEXEC_B64 $sgpr96_sgpr97, implicit-def $exec, implicit-def $scc, implicit $exec51 $exec = S_XOR_B64_term $exec, %0, implicit-def $scc52 S_CBRANCH_EXECZ %bb.3, implicit $exec53 S_BRANCH %bb.254 55 bb.2:56 liveins: $sgpr98_sgpr99, $sgpr102_sgpr10357 58 %0:sreg_64 = S_OR_SAVEEXEC_B64 $sgpr98_sgpr99, implicit-def $exec, implicit-def $scc, implicit $exec59 $exec = S_XOR_B64_term $exec, %0, implicit-def $scc60 S_CBRANCH_EXECZ %bb.3, implicit $exec61 S_BRANCH %bb.462 63 bb.3:64 liveins: $sgpr102_sgpr10365 66 %0:sreg_64 = S_OR_SAVEEXEC_B64 $sgpr102_sgpr103, implicit-def $exec, implicit-def $scc, implicit $exec67 $exec = S_XOR_B64_term $exec, %0, implicit-def $scc68 S_BRANCH %bb.469 70 bb.4:71 S_CMP_EQ_U64 %1.sub0_sub1, %2.sub2_sub3, implicit-def $scc72 S_CMP_EQ_U64 %3.sub0_sub1, %4.sub2_sub3, implicit-def $scc73 S_CMP_EQ_U64 %5.sub0_sub1, %6.sub2_sub3, implicit-def $scc74 S_CMP_EQ_U64 %7.sub0_sub1, %8.sub2_sub3, implicit-def $scc75 S_CMP_EQ_U64 %9.sub0_sub1, %10.sub2_sub3, implicit-def $scc76 S_CMP_EQ_U64 %11.sub0_sub1, %12.sub2_sub3, implicit-def $scc77 S_CMP_EQ_U64 %13.sub0_sub1, %14.sub2_sub3, implicit-def $scc78 S_CMP_EQ_U64 %15.sub0_sub1, %16.sub2_sub3, implicit-def $scc79 S_CMP_EQ_U64 %17.sub0_sub1, %18.sub2_sub3, implicit-def $scc80 S_CMP_EQ_U64 %19.sub0_sub1, %20.sub2_sub3, implicit-def $scc81 S_CMP_EQ_U64 %21.sub0_sub1, %22.sub2_sub3, implicit-def $scc82 S_CMP_EQ_U64 %23.sub0_sub1, %24.sub2_sub3, implicit-def $scc83 S_CMP_EQ_U64 %25.sub0_sub1, %26.sub2_sub3, implicit-def $scc84 $vgpr0 = V_MOV_B32_e32 0, implicit $exec85 S_SETPC_B64_return undef $sgpr30_sgpr31, implicit %0, implicit $vgpr086...87