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1; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tahiti -stress-regalloc=6 < %s | FileCheck %s2 3; Inline spiller can decide to move a spill as early as possible in the basic block.4; It will skip phis and label, but we also need to make sure it skips instructions5; in the basic block prologue which restore exec mask.6; Make sure instruction to restore exec mask immediately follows label7 8; CHECK-LABEL: {{^}}spill_cfg_position:9; CHECK: s_cbranch_execz [[LABEL1:.LBB[0-9_]+]]10; CHECK: {{^}}[[LABEL1]]:11; CHECK: s_cbranch_execz [[LABEL2:.LBB[0-9_]+]]12; CHECK: {{^}}[[LABEL2]]:13; CHECK-NEXT: s_or_b64 exec14; CHECK: buffer_15 16define amdgpu_kernel void @spill_cfg_position(ptr addrspace(1) nocapture %arg) {17bb:18 %tmp1 = tail call i32 @llvm.amdgcn.workitem.id.x() #019 %tmp14 = load i32, ptr addrspace(1) %arg, align 420 %tmp15 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 121 %tmp16 = load i32, ptr addrspace(1) %tmp15, align 422 %tmp17 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 223 %tmp18 = load i32, ptr addrspace(1) %tmp17, align 424 %tmp19 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 325 %tmp20 = load i32, ptr addrspace(1) %tmp19, align 426 %tmp21 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 427 %tmp22 = load i32, ptr addrspace(1) %tmp21, align 428 %tmp23 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 529 %tmp24 = load i32, ptr addrspace(1) %tmp23, align 430 %tmp25 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 631 %tmp26 = load i32, ptr addrspace(1) %tmp25, align 432 %tmp27 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 733 %tmp28 = load i32, ptr addrspace(1) %tmp27, align 434 %tmp29 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 835 %tmp30 = load i32, ptr addrspace(1) %tmp29, align 436 %tmp33 = getelementptr inbounds i32, ptr addrspace(1) %arg, i32 %tmp137 %tmp34 = load i32, ptr addrspace(1) %tmp33, align 438 %tmp35 = icmp eq i32 %tmp34, 039 br i1 %tmp35, label %bb44, label %bb3640 41bb36: ; preds = %bb42 %tmp37 = mul nsw i32 %tmp20, %tmp1843 %tmp38 = add nsw i32 %tmp37, %tmp1644 %tmp39 = mul nsw i32 %tmp24, %tmp2245 %tmp40 = add nsw i32 %tmp38, %tmp3946 %tmp41 = mul nsw i32 %tmp28, %tmp2647 %tmp42 = add nsw i32 %tmp40, %tmp4148 %tmp43 = add nsw i32 %tmp42, %tmp3049 br label %bb5250 51bb44: ; preds = %bb52 %tmp45 = mul nsw i32 %tmp18, %tmp1653 %tmp46 = mul nsw i32 %tmp22, %tmp2054 %tmp47 = add nsw i32 %tmp46, %tmp4555 %tmp48 = mul nsw i32 %tmp26, %tmp2456 %tmp49 = add nsw i32 %tmp47, %tmp4857 %tmp50 = mul nsw i32 %tmp30, %tmp2858 %tmp51 = add nsw i32 %tmp49, %tmp5059 br label %bb5260 61bb52: ; preds = %bb44, %bb3662 %tmp53 = phi i32 [ %tmp43, %bb36 ], [ %tmp51, %bb44 ]63 %tmp54 = mul nsw i32 %tmp16, %tmp1464 %tmp55 = mul nsw i32 %tmp22, %tmp1865 %tmp56 = mul nsw i32 %tmp24, %tmp2066 %tmp57 = mul nsw i32 %tmp30, %tmp2667 %tmp58 = add i32 %tmp55, %tmp5468 %tmp59 = add i32 %tmp58, %tmp5669 %tmp60 = add i32 %tmp59, %tmp2870 %tmp61 = add i32 %tmp60, %tmp5771 %tmp62 = add i32 %tmp61, %tmp5372 store i32 %tmp62, ptr addrspace(1) %tmp33, align 473 ret void74}75 76declare i32 @llvm.amdgcn.workitem.id.x() #077 78attributes #0 = { nounwind readnone }79