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1; RUN: llc -O0 -amdgpu-spill-sgpr-to-vgpr=1 -mtriple=amdgcn < %s | FileCheck -enable-var-scope -check-prefix=TOVGPR -check-prefix=GCN %s2; RUN: llc -O0 -amdgpu-spill-sgpr-to-vgpr=1 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -enable-var-scope -check-prefix=TOVGPR -check-prefix=GCN %s3; RUN: llc -O0 -amdgpu-spill-sgpr-to-vgpr=0 -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -enable-var-scope -check-prefix=TOVMEM -check-prefix=GCN %s4; RUN: llc -O0 -amdgpu-spill-sgpr-to-vgpr=0 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -enable-var-scope -check-prefix=TOVMEM -check-prefix=GCN %s5 6; XXX - Why does it like to use vcc?7 8; GCN-LABEL: {{^}}spill_m0:9 10; GCN: #ASMSTART11; GCN-NEXT: s_mov_b32 m0, 012; GCN-NEXT: #ASMEND13; GCN-DAG: s_mov_b32 [[M0_COPY:s[0-9]+]], m014 15; TOVGPR: v_writelane_b32 [[SPILL_VREG:v[0-9]+]], [[M0_COPY]], [[M0_LANE:[0-9]+]]16 17; TOVMEM: s_mov_b64 [[COPY_EXEC:s\[[0-9]+:[0-9]+\]]], exec18; TOVMEM: s_mov_b64 exec, 119; TOVMEM: v_writelane_b32 [[SPILL_VREG:v[0-9]+]], [[M0_COPY]], 020; TOVMEM: buffer_store_dword [[SPILL_VREG]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 ; 4-byte Folded Spill21; TOVMEM: s_mov_b64 exec, [[COPY_EXEC]]22 23; GCN: s_cbranch_scc1 [[ENDIF:.LBB[0-9]+_[0-9]+]]24 25; GCN: [[ENDIF]]:26; TOVGPR: v_readlane_b32 [[M0_RESTORE:s[0-9]+]], [[SPILL_VREG]], [[M0_LANE]]27; TOVGPR: s_mov_b32 m0, [[M0_RESTORE]]28 29; TOVMEM: buffer_load_dword [[RELOAD_VREG:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 ; 4-byte Folded Reload30; TOVMEM: s_waitcnt vmcnt(0)31; TOVMEM: v_readlane_b32 [[M0_RESTORE:s[0-9]+]], [[RELOAD_VREG]], 032; TOVMEM: s_mov_b32 m0, [[M0_RESTORE]]33 34; GCN: s_add_i32 s{{[0-9]+}}, m0, 135define amdgpu_kernel void @spill_m0(i32 %cond, ptr addrspace(1) %out) #0 {36entry:37 %m0 = call i32 asm sideeffect "s_mov_b32 m0, 0", "={m0}"() #038 %cmp0 = icmp eq i32 %cond, 039 br i1 %cmp0, label %if, label %endif40 41if:42 call void asm sideeffect "v_nop", ""() #043 br label %endif44 45endif:46 %foo = call i32 asm sideeffect "s_add_i32 $0, $1, 1", "=s,{m0}"(i32 %m0) #047 store i32 %foo, ptr addrspace(1) %out48 ret void49}50 51@lds = internal addrspace(3) global [64 x float] poison52 53; m0 is killed, so it isn't necessary during the entry block spill to preserve it54; GCN-LABEL: {{^}}spill_kill_m0_lds:55 56; GCN-NOT: v_readlane_b32 m057; GCN-NOT: s_buffer_store_dword m058; GCN-NOT: s_buffer_load_dword m059define amdgpu_ps void @spill_kill_m0_lds(ptr addrspace(4) inreg %arg, ptr addrspace(4) inreg %arg1, ptr addrspace(4) inreg %arg2, i32 inreg %m0) #0 {60main_body:61 %tmp = call float @llvm.amdgcn.interp.mov(i32 2, i32 0, i32 0, i32 %m0)62 %cmp = fcmp ueq float 0.000000e+00, %tmp63 br i1 %cmp, label %if, label %else64 65if: ; preds = %main_body66 %lds_data_ = load float, ptr addrspace(3) @lds67 %lds_data = call float @llvm.amdgcn.wqm.f32(float %lds_data_)68 br label %endif69 70else: ; preds = %main_body71 %interp = call float @llvm.amdgcn.interp.mov(i32 2, i32 0, i32 0, i32 %m0)72 br label %endif73 74endif: ; preds = %else, %if75 %export = phi float [ %lds_data, %if ], [ %interp, %else ]76 %tmp4 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %export, float %export)77 call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> %tmp4, <2 x half> %tmp4, i1 true, i1 true) #078 ret void79}80 81; Force save and restore of m0 during SMEM spill82; GCN-LABEL: {{^}}m0_unavailable_spill:83; GCN: s_load_dword [[REG0:s[0-9]+]], s[4:5], {{0x[0-9]+}}84 85; GCN: ; def m0, 186 87; GCN: s_mov_b32 m0, [[REG0]]88; GCN: v_interp_mov_f3289 90; GCN: ; clobber m091 92; TOSMEM: s_mov_b32 s2, m093; TOSMEM: s_add_u32 m0, s3, 0x10094; TOSMEM-NEXT: s_buffer_store_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, m0 ; 8-byte Folded Spill95; TOSMEM: s_mov_b32 m0, s296 97; TOSMEM: s_mov_b64 exec,98; TOSMEM: s_cbranch_execz99; TOSMEM: s_branch100 101; TOSMEM: BB{{[0-9]+_[0-9]+}}:102; TOSMEM: s_add_u32 m0, s3, 0x100103; TOSMEM-NEXT: s_buffer_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, m0 ; 8-byte Folded Reload104 105; GCN-NOT: v_readlane_b32 m0106; GCN-NOT: s_buffer_store_dword m0107; GCN-NOT: s_buffer_load_dword m0108define amdgpu_kernel void @m0_unavailable_spill(i32 %m0.arg) #0 {109main_body:110 %m0 = call i32 asm sideeffect "; def $0, 1", "={m0}"() #0111 %tmp = call float @llvm.amdgcn.interp.mov(i32 2, i32 0, i32 0, i32 %m0.arg)112 call void asm sideeffect "; clobber $0", "~{m0}"() #0113 %cmp = fcmp ueq float 0.000000e+00, %tmp114 br i1 %cmp, label %if, label %else115 116if: ; preds = %main_body117 store volatile i32 8, ptr addrspace(1) poison118 br label %endif119 120else: ; preds = %main_body121 store volatile i32 11, ptr addrspace(1) poison122 br label %endif123 124endif:125 ret void126}127 128; GCN-LABEL: {{^}}restore_m0_lds:129; FIXME: RegScavenger::isRegUsed() always returns true if m0 is reserved, so we have to save and restore it130; FIXME-TOSMEM-NOT: m0131; TOSMEM: s_add_u32 m0, s3, {{0x[0-9]+}}132; TOSMEM: s_buffer_store_dword s1, s[88:91], m0 ; 4-byte Folded Spill133; FIXME-TOSMEM-NOT: m0134; TOSMEM: s_load_dwordx2 [[REG:s\[[0-9]+:[0-9]+\]]]135; TOSMEM: s_add_u32 m0, s3, {{0x[0-9]+}}136; TOSMEM: s_waitcnt lgkmcnt(0)137; TOSMEM: s_buffer_store_dwordx2 [[REG]], s[88:91], m0 ; 8-byte Folded Spill138; FIXME-TOSMEM-NOT: m0139; TOSMEM: s_cmp_eq_u32140; TOSMEM: s_cbranch_scc1141 142; TOSMEM: s_mov_b32 m0, -1143 144; TOSMEM: s_mov_b32 s2, m0145; TOSMEM: s_add_u32 m0, s3, 0x200146; TOSMEM: s_buffer_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[88:91], m0 ; 8-byte Folded Reload147; TOSMEM: s_mov_b32 m0, s2148; TOSMEM: s_waitcnt lgkmcnt(0)149 150; TOSMEM: ds_write_b64151 152; FIXME-TOSMEM-NOT: m0153; TOSMEM: s_add_u32 m0, s3, 0x100154; TOSMEM: s_buffer_load_dword s2, s[88:91], m0 ; 4-byte Folded Reload155; FIXME-TOSMEM-NOT: m0156 157; TOSMEM: s_mov_b32 [[REG1:s[0-9]+]], m0158; TOSMEM: s_add_u32 m0, s3, 0x100159; TOSMEM: s_buffer_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[88:91], m0 ; 8-byte Folded Reload160; TOSMEM: s_mov_b32 m0, [[REG1]]161; TOSMEM: s_mov_b32 m0, -1162 163; TOSMEM: s_waitcnt lgkmcnt(0)164; TOSMEM-NOT: m0165; TOSMEM: s_mov_b32 m0, s2166; TOSMEM: ; use m0167 168; TOSMEM: s_dcache_wb169; TOSMEM: s_endpgm170define amdgpu_kernel void @restore_m0_lds(i32 %arg) {171 %m0 = call i32 asm sideeffect "s_mov_b32 m0, 0", "={m0}"() #0172 %sval = load volatile i64, ptr addrspace(4) poison173 %cmp = icmp eq i32 %arg, 0174 br i1 %cmp, label %ret, label %bb175 176bb:177 store volatile i64 %sval, ptr addrspace(3) poison178 call void asm sideeffect "; use $0", "{m0}"(i32 %m0) #0179 br label %ret180 181ret:182 ret void183}184 185declare float @llvm.amdgcn.interp.mov(i32, i32, i32, i32) #1186declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0187declare void @llvm.amdgcn.exp.compr.v2f16(i32, i32, <2 x half>, <2 x half>, i1, i1) #0188declare <2 x half> @llvm.amdgcn.cvt.pkrtz(float, float) #1189declare float @llvm.amdgcn.wqm.f32(float) #1190 191attributes #0 = { nounwind }192attributes #1 = { nounwind readnone }193 194