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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -enable-misched=0 -post-RA-scheduler=0 -stress-regalloc=8 < %s | FileCheck -check-prefix=MUBUF %s3; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -enable-misched=0 -post-RA-scheduler=0 -stress-regalloc=8 -mattr=+enable-flat-scratch < %s | FileCheck -check-prefix=FLATSCR %s4 5; Test that the VGPR spiller correctly switches to SGPR offsets when the6; instruction offset field would overflow, and that it accounts for memory7; swizzling.8 9define amdgpu_kernel void @test_inst_offset_kernel() {10; MUBUF-LABEL: test_inst_offset_kernel:11; MUBUF: ; %bb.0: ; %entry12; MUBUF-NEXT: s_add_u32 s0, s0, s1713; MUBUF-NEXT: s_addc_u32 s1, s1, 014; MUBUF-NEXT: buffer_load_dword v0, off, s[0:3], 0 offset:4 glc15; MUBUF-NEXT: s_waitcnt vmcnt(0)16; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:4088 ; 4-byte Folded Spill17; MUBUF-NEXT: ;;#ASMSTART18; MUBUF-NEXT: ;;#ASMEND19; MUBUF-NEXT: buffer_load_dword v0, off, s[0:3], 0 offset:4088 ; 4-byte Folded Reload20; MUBUF-NEXT: s_waitcnt vmcnt(0)21; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:422; MUBUF-NEXT: s_waitcnt vmcnt(0)23; MUBUF-NEXT: s_endpgm24;25; FLATSCR-LABEL: test_inst_offset_kernel:26; FLATSCR: ; %bb.0: ; %entry27; FLATSCR-NEXT: s_add_u32 flat_scratch_lo, s8, s1328; FLATSCR-NEXT: s_addc_u32 flat_scratch_hi, s9, 029; FLATSCR-NEXT: s_mov_b32 s0, 030; FLATSCR-NEXT: scratch_load_dword v0, off, s0 offset:4 glc31; FLATSCR-NEXT: s_waitcnt vmcnt(0)32; FLATSCR-NEXT: s_movk_i32 s0, 0xff833; FLATSCR-NEXT: scratch_store_dword off, v0, s0 ; 4-byte Folded Spill34; FLATSCR-NEXT: ;;#ASMSTART35; FLATSCR-NEXT: ;;#ASMEND36; FLATSCR-NEXT: scratch_load_dword v0, off, s0 ; 4-byte Folded Reload37; FLATSCR-NEXT: s_mov_b32 s0, 038; FLATSCR-NEXT: s_waitcnt vmcnt(0)39; FLATSCR-NEXT: scratch_store_dword off, v0, s0 offset:440; FLATSCR-NEXT: s_waitcnt vmcnt(0)41; FLATSCR-NEXT: s_endpgm42entry:43 ; Occupy 4092 bytes of scratch, so the offset of the spill of %a just fits in44 ; the instruction offset field.45 %alloca = alloca i8, i32 4088, align 4, addrspace(5)46 47 %aptr = getelementptr i32, ptr addrspace(5) %alloca, i32 148 49 50 %a = load volatile i32, ptr addrspace(5) %aptr51 52 ; Force %a to spill.53 call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7}" ()54 55 %outptr = getelementptr i32, ptr addrspace(5) %alloca, i32 156 store volatile i32 %a, ptr addrspace(5) %outptr57 58 ret void59}60 61define amdgpu_kernel void @test_sgpr_offset_kernel() {62; MUBUF-LABEL: test_sgpr_offset_kernel:63; MUBUF: ; %bb.0: ; %entry64; MUBUF-NEXT: s_add_u32 s0, s0, s1765; MUBUF-NEXT: s_addc_u32 s1, s1, 066; MUBUF-NEXT: buffer_load_dword v0, off, s[0:3], 0 offset:8 glc67; MUBUF-NEXT: s_waitcnt vmcnt(0)68; MUBUF-NEXT: s_mov_b32 s4, 0x4000069; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], s4 ; 4-byte Folded Spill70; MUBUF-NEXT: ;;#ASMSTART71; MUBUF-NEXT: ;;#ASMEND72; MUBUF-NEXT: buffer_load_dword v0, off, s[0:3], s4 ; 4-byte Folded Reload73; MUBUF-NEXT: s_waitcnt vmcnt(0)74; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:875; MUBUF-NEXT: s_waitcnt vmcnt(0)76; MUBUF-NEXT: s_endpgm77;78; FLATSCR-LABEL: test_sgpr_offset_kernel:79; FLATSCR: ; %bb.0: ; %entry80; FLATSCR-NEXT: s_add_u32 flat_scratch_lo, s8, s1381; FLATSCR-NEXT: s_addc_u32 flat_scratch_hi, s9, 082; FLATSCR-NEXT: s_mov_b32 s0, 083; FLATSCR-NEXT: scratch_load_dword v0, off, s0 offset:8 glc84; FLATSCR-NEXT: s_waitcnt vmcnt(0)85; FLATSCR-NEXT: s_movk_i32 s0, 0x100086; FLATSCR-NEXT: scratch_store_dword off, v0, s0 ; 4-byte Folded Spill87; FLATSCR-NEXT: ;;#ASMSTART88; FLATSCR-NEXT: ;;#ASMEND89; FLATSCR-NEXT: scratch_load_dword v0, off, s0 ; 4-byte Folded Reload90; FLATSCR-NEXT: s_mov_b32 s0, 091; FLATSCR-NEXT: s_waitcnt vmcnt(0)92; FLATSCR-NEXT: scratch_store_dword off, v0, s0 offset:893; FLATSCR-NEXT: s_waitcnt vmcnt(0)94; FLATSCR-NEXT: s_endpgm95entry:96 ; Occupy 4096 bytes of scratch, so the offset of the spill of %a does not97 ; fit in the instruction, and has to live in the SGPR offset.98 %alloca = alloca i8, i32 4092, align 4, addrspace(5)99 100 %aptr = getelementptr i32, ptr addrspace(5) %alloca, i32 1101 ; 0x40000 / 64 = 4096 (for wave64)102 %a = load volatile i32, ptr addrspace(5) %aptr103 ; Force %a to spill104 call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7}" ()105 106 %outptr = getelementptr i32, ptr addrspace(5) %alloca, i32 1107 store volatile i32 %a, ptr addrspace(5) %outptr108 109 ret void110}111 112define void @test_sgpr_offset_function_scavenge_fail_func() #2 {113; MUBUF-LABEL: test_sgpr_offset_function_scavenge_fail_func:114; MUBUF: ; %bb.0: ; %entry115; MUBUF-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)116; MUBUF-NEXT: ;;#ASMSTART117; MUBUF-NEXT: ;;#ASMEND118; MUBUF-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:8 glc119; MUBUF-NEXT: s_waitcnt vmcnt(0)120; MUBUF-NEXT: s_add_i32 s10, s32, 0x40100121; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], s10 ; 4-byte Folded Spill122; MUBUF-NEXT: ;;#ASMSTART123; MUBUF-NEXT: ;;#ASMEND124; MUBUF-NEXT: ;;#ASMSTART125; MUBUF-NEXT: ;;#ASMEND126; MUBUF-NEXT: ;;#ASMSTART127; MUBUF-NEXT: ;;#ASMEND128; MUBUF-NEXT: s_add_i32 s10, s32, 0x40100129; MUBUF-NEXT: buffer_load_dword v0, off, s[0:3], s10 ; 4-byte Folded Reload130; MUBUF-NEXT: s_waitcnt vmcnt(0)131; MUBUF-NEXT: ;;#ASMSTART132; MUBUF-NEXT: ;;#ASMEND133; MUBUF-NEXT: s_setpc_b64 s[30:31]134;135; FLATSCR-LABEL: test_sgpr_offset_function_scavenge_fail_func:136; FLATSCR: ; %bb.0: ; %entry137; FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)138; FLATSCR-NEXT: ;;#ASMSTART139; FLATSCR-NEXT: ;;#ASMEND140; FLATSCR-NEXT: scratch_load_dword v0, off, s32 offset:8 glc141; FLATSCR-NEXT: s_waitcnt vmcnt(0)142; FLATSCR-NEXT: s_add_i32 s8, s32, 0x1004143; FLATSCR-NEXT: scratch_store_dword off, v0, s8 ; 4-byte Folded Spill144; FLATSCR-NEXT: ;;#ASMSTART145; FLATSCR-NEXT: ;;#ASMEND146; FLATSCR-NEXT: ;;#ASMSTART147; FLATSCR-NEXT: ;;#ASMEND148; FLATSCR-NEXT: ;;#ASMSTART149; FLATSCR-NEXT: ;;#ASMEND150; FLATSCR-NEXT: s_add_i32 s8, s32, 0x1004151; FLATSCR-NEXT: scratch_load_dword v0, off, s8 ; 4-byte Folded Reload152; FLATSCR-NEXT: s_waitcnt vmcnt(0)153; FLATSCR-NEXT: ;;#ASMSTART154; FLATSCR-NEXT: ;;#ASMEND155; FLATSCR-NEXT: s_setpc_b64 s[30:31]156entry:157 ; Occupy 4096 bytes of scratch, so the offset of the spill of %a does not158 ; fit in the instruction, and has to live in the SGPR offset.159 %alloca = alloca i8, i32 4096, align 4, addrspace(5)160 161 %aptr = getelementptr i32, ptr addrspace(5) %alloca, i32 1162 163 %asm.0 = call { i32, i32, i32, i32, i32, i32, i32, i32 } asm sideeffect "", "=s,=s,=s,=s,=s,=s,=s,=s"()164 %asm0.0 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32 } %asm.0, 0165 %asm1.0 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32 } %asm.0, 1166 %asm2.0 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32 } %asm.0, 2167 %asm3.0 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32 } %asm.0, 3168 %asm4.0 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32 } %asm.0, 4169 %asm5.0 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32 } %asm.0, 5170 %asm6.0 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32 } %asm.0, 6171 %asm7.0 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32 } %asm.0, 7172 173 ; 0x40000 / 64 = 4096 (for wave64)174 %a = load volatile i32, ptr addrspace(5) %aptr175 call void asm sideeffect "", "s,s,s,s,s,s,s,s,v"(i32 %asm0.0, i32 %asm1.0, i32 %asm2.0, i32 %asm3.0, i32 %asm4.0, i32 %asm5.0, i32 %asm6.0, i32 %asm7.0, i32 %a)176 177 %asm = call { i32, i32, i32, i32, i32, i32, i32, i32 } asm sideeffect "", "=s,=s,=s,=s,=s,=s,=s,=s"()178 %asm0 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32 } %asm, 0179 %asm1 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32 } %asm, 1180 %asm2 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32 } %asm, 2181 %asm3 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32 } %asm, 3182 %asm4 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32 } %asm, 4183 %asm5 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32 } %asm, 5184 %asm6 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32 } %asm, 6185 %asm7 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32 } %asm, 7186 187 call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7}"() #0188 ; Force %a to spill with no free SGPRs189 call void asm sideeffect "", "s,s,s,s,s,s,s,s,v"(i32 %asm0, i32 %asm1, i32 %asm2, i32 %asm3, i32 %asm4, i32 %asm5, i32 %asm6, i32 %asm7, i32 %a)190 ret void191}192 193define amdgpu_kernel void @test_sgpr_offset_function_scavenge_fail_kernel() #3 {194; MUBUF-LABEL: test_sgpr_offset_function_scavenge_fail_kernel:195; MUBUF: ; %bb.0: ; %entry196; MUBUF-NEXT: s_add_u32 s0, s0, s17197; MUBUF-NEXT: s_addc_u32 s1, s1, 0198; MUBUF-NEXT: ;;#ASMSTART199; MUBUF-NEXT: ;;#ASMEND200; MUBUF-NEXT: buffer_load_dword v0, off, s[0:3], 0 offset:8 glc201; MUBUF-NEXT: s_waitcnt vmcnt(0)202; MUBUF-NEXT: s_mov_b32 s10, 0x40100203; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], s10 ; 4-byte Folded Spill204; MUBUF-NEXT: ;;#ASMSTART205; MUBUF-NEXT: ;;#ASMEND206; MUBUF-NEXT: ;;#ASMSTART207; MUBUF-NEXT: ;;#ASMEND208; MUBUF-NEXT: ;;#ASMSTART209; MUBUF-NEXT: ;;#ASMEND210; MUBUF-NEXT: buffer_load_dword v0, off, s[0:3], s10 ; 4-byte Folded Reload211; MUBUF-NEXT: s_waitcnt vmcnt(0)212; MUBUF-NEXT: ;;#ASMSTART213; MUBUF-NEXT: ;;#ASMEND214; MUBUF-NEXT: s_endpgm215;216; FLATSCR-LABEL: test_sgpr_offset_function_scavenge_fail_kernel:217; FLATSCR: ; %bb.0: ; %entry218; FLATSCR-NEXT: s_add_u32 flat_scratch_lo, s8, s13219; FLATSCR-NEXT: s_addc_u32 flat_scratch_hi, s9, 0220; FLATSCR-NEXT: s_mov_b32 s8, 0221; FLATSCR-NEXT: ;;#ASMSTART222; FLATSCR-NEXT: ;;#ASMEND223; FLATSCR-NEXT: scratch_load_dword v0, off, s8 offset:8 glc224; FLATSCR-NEXT: s_waitcnt vmcnt(0)225; FLATSCR-NEXT: s_movk_i32 s8, 0x1004226; FLATSCR-NEXT: scratch_store_dword off, v0, s8 ; 4-byte Folded Spill227; FLATSCR-NEXT: ;;#ASMSTART228; FLATSCR-NEXT: ;;#ASMEND229; FLATSCR-NEXT: ;;#ASMSTART230; FLATSCR-NEXT: ;;#ASMEND231; FLATSCR-NEXT: ;;#ASMSTART232; FLATSCR-NEXT: ;;#ASMEND233; FLATSCR-NEXT: scratch_load_dword v0, off, s8 ; 4-byte Folded Reload234; FLATSCR-NEXT: s_waitcnt vmcnt(0)235; FLATSCR-NEXT: ;;#ASMSTART236; FLATSCR-NEXT: ;;#ASMEND237; FLATSCR-NEXT: s_endpgm238entry:239 ; Occupy 4096 bytes of scratch, so the offset of the spill of %a does not240 ; fit in the instruction, and has to live in the SGPR offset.241 %alloca = alloca i8, i32 4096, align 4, addrspace(5)242 243 %aptr = getelementptr i32, ptr addrspace(5) %alloca, i32 1244 245 %asm.0 = call { i32, i32, i32, i32, i32, i32, i32, i32 } asm sideeffect "", "=s,=s,=s,=s,=s,=s,=s,=s"()246 %asm0.0 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32 } %asm.0, 0247 %asm1.0 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32 } %asm.0, 1248 %asm2.0 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32 } %asm.0, 2249 %asm3.0 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32 } %asm.0, 3250 %asm4.0 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32 } %asm.0, 4251 %asm5.0 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32 } %asm.0, 5252 %asm6.0 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32 } %asm.0, 6253 %asm7.0 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32 } %asm.0, 7254 255 ; 0x40000 / 64 = 4096 (for wave64)256 %a = load volatile i32, ptr addrspace(5) %aptr257 call void asm sideeffect "", "s,s,s,s,s,s,s,s,v"(i32 %asm0.0, i32 %asm1.0, i32 %asm2.0, i32 %asm3.0, i32 %asm4.0, i32 %asm5.0, i32 %asm6.0, i32 %asm7.0, i32 %a)258 259 %asm = call { i32, i32, i32, i32, i32, i32, i32, i32 } asm sideeffect "", "=s,=s,=s,=s,=s,=s,=s,=s"()260 %asm0 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32 } %asm, 0261 %asm1 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32 } %asm, 1262 %asm2 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32 } %asm, 2263 %asm3 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32 } %asm, 3264 %asm4 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32 } %asm, 4265 %asm5 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32 } %asm, 5266 %asm6 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32 } %asm, 6267 %asm7 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32 } %asm, 7268 269 call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7}"() #0270 ; Force %a to spill with no free SGPRs271 call void asm sideeffect "", "s,s,s,s,s,s,s,s,v"(i32 %asm0, i32 %asm1, i32 %asm2, i32 %asm3, i32 %asm4, i32 %asm5, i32 %asm6, i32 %asm7, i32 %a)272 ret void273}274 275define amdgpu_kernel void @test_sgpr_offset_subregs_kernel() {276; MUBUF-LABEL: test_sgpr_offset_subregs_kernel:277; MUBUF: ; %bb.0: ; %entry278; MUBUF-NEXT: s_add_u32 s0, s0, s17279; MUBUF-NEXT: s_addc_u32 s1, s1, 0280; MUBUF-NEXT: buffer_load_dword v0, off, s[0:3], 0 offset:8 glc281; MUBUF-NEXT: s_waitcnt vmcnt(0)282; MUBUF-NEXT: buffer_load_dword v1, off, s[0:3], 0 offset:12 glc283; MUBUF-NEXT: s_waitcnt vmcnt(0)284; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:4084 ; 4-byte Folded Spill285; MUBUF-NEXT: s_nop 0286; MUBUF-NEXT: buffer_store_dword v1, off, s[0:3], 0 offset:4088 ; 4-byte Folded Spill287; MUBUF-NEXT: ;;#ASMSTART288; MUBUF-NEXT: ;;#ASMEND289; MUBUF-NEXT: buffer_load_dword v0, off, s[0:3], 0 offset:4 glc290; MUBUF-NEXT: s_waitcnt vmcnt(0)291; MUBUF-NEXT: buffer_load_dword v0, off, s[0:3], 0 offset:4084 ; 4-byte Folded Reload292; MUBUF-NEXT: buffer_load_dword v1, off, s[0:3], 0 offset:4088 ; 4-byte Folded Reload293; MUBUF-NEXT: s_waitcnt vmcnt(0)294; MUBUF-NEXT: ;;#ASMSTART295; MUBUF-NEXT: ; v[0:1]296; MUBUF-NEXT: ;;#ASMEND297; MUBUF-NEXT: s_endpgm298;299; FLATSCR-LABEL: test_sgpr_offset_subregs_kernel:300; FLATSCR: ; %bb.0: ; %entry301; FLATSCR-NEXT: s_add_u32 flat_scratch_lo, s8, s13302; FLATSCR-NEXT: s_addc_u32 flat_scratch_hi, s9, 0303; FLATSCR-NEXT: s_mov_b32 s0, 0304; FLATSCR-NEXT: scratch_load_dwordx2 v[0:1], off, s0 offset:8 glc305; FLATSCR-NEXT: s_waitcnt vmcnt(0)306; FLATSCR-NEXT: s_movk_i32 s0, 0xff4307; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], s0 ; 8-byte Folded Spill308; FLATSCR-NEXT: s_mov_b32 s0, 0309; FLATSCR-NEXT: ;;#ASMSTART310; FLATSCR-NEXT: ;;#ASMEND311; FLATSCR-NEXT: scratch_load_dword v0, off, s0 offset:4 glc312; FLATSCR-NEXT: s_waitcnt vmcnt(0)313; FLATSCR-NEXT: s_movk_i32 s0, 0xff4314; FLATSCR-NEXT: scratch_load_dwordx2 v[0:1], off, s0 ; 8-byte Folded Reload315; FLATSCR-NEXT: s_waitcnt vmcnt(0)316; FLATSCR-NEXT: ;;#ASMSTART317; FLATSCR-NEXT: ; v[0:1]318; FLATSCR-NEXT: ;;#ASMEND319; FLATSCR-NEXT: s_endpgm320entry:321 ; Occupy 4088 bytes of scratch, so that the spill of the last subreg of %a322 ; still fits below offset 4096 (4088 + 8 - 4 = 4092), and can be placed in323 ; the instruction offset field.324 %alloca = alloca i8, i32 4084, align 4, addrspace(5)325 %aptr = getelementptr <2 x i32>, ptr addrspace(5) %alloca, i32 1326 %a = load volatile <2 x i32>, ptr addrspace(5) %aptr327 328 ; Force %a to spill.329 call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7}" ()330 331 ; Ensure the alloca sticks around.332 %bptr = getelementptr i32, ptr addrspace(5) %alloca, i32 1333 %b = load volatile i32, ptr addrspace(5) %bptr334 335 ; Ensure the spill is of the full super-reg.336 call void asm sideeffect "; $0", "r"(<2 x i32> %a)337 338 ret void339}340 341define amdgpu_kernel void @test_inst_offset_subregs_kernel() {342; MUBUF-LABEL: test_inst_offset_subregs_kernel:343; MUBUF: ; %bb.0: ; %entry344; MUBUF-NEXT: s_add_u32 s0, s0, s17345; MUBUF-NEXT: s_addc_u32 s1, s1, 0346; MUBUF-NEXT: buffer_load_dword v0, off, s[0:3], 0 offset:12 glc347; MUBUF-NEXT: s_waitcnt vmcnt(0)348; MUBUF-NEXT: buffer_load_dword v1, off, s[0:3], 0 offset:16 glc349; MUBUF-NEXT: s_waitcnt vmcnt(0)350; MUBUF-NEXT: s_mov_b32 s4, 0x3ff00351; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], s4 ; 4-byte Folded Spill352; MUBUF-NEXT: s_nop 0353; MUBUF-NEXT: buffer_store_dword v1, off, s[0:3], s4 offset:4 ; 4-byte Folded Spill354; MUBUF-NEXT: ;;#ASMSTART355; MUBUF-NEXT: ;;#ASMEND356; MUBUF-NEXT: buffer_load_dword v0, off, s[0:3], 0 offset:8 glc357; MUBUF-NEXT: s_waitcnt vmcnt(0)358; MUBUF-NEXT: buffer_load_dword v0, off, s[0:3], s4 ; 4-byte Folded Reload359; MUBUF-NEXT: buffer_load_dword v1, off, s[0:3], s4 offset:4 ; 4-byte Folded Reload360; MUBUF-NEXT: s_waitcnt vmcnt(0)361; MUBUF-NEXT: ;;#ASMSTART362; MUBUF-NEXT: ; v[0:1]363; MUBUF-NEXT: ;;#ASMEND364; MUBUF-NEXT: s_endpgm365;366; FLATSCR-LABEL: test_inst_offset_subregs_kernel:367; FLATSCR: ; %bb.0: ; %entry368; FLATSCR-NEXT: s_add_u32 flat_scratch_lo, s8, s13369; FLATSCR-NEXT: s_addc_u32 flat_scratch_hi, s9, 0370; FLATSCR-NEXT: s_mov_b32 s0, 0371; FLATSCR-NEXT: scratch_load_dwordx2 v[0:1], off, s0 offset:12 glc372; FLATSCR-NEXT: s_waitcnt vmcnt(0)373; FLATSCR-NEXT: s_movk_i32 s0, 0xffc374; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], s0 ; 8-byte Folded Spill375; FLATSCR-NEXT: s_mov_b32 s0, 0376; FLATSCR-NEXT: ;;#ASMSTART377; FLATSCR-NEXT: ;;#ASMEND378; FLATSCR-NEXT: scratch_load_dword v0, off, s0 offset:8 glc379; FLATSCR-NEXT: s_waitcnt vmcnt(0)380; FLATSCR-NEXT: s_movk_i32 s0, 0xffc381; FLATSCR-NEXT: scratch_load_dwordx2 v[0:1], off, s0 ; 8-byte Folded Reload382; FLATSCR-NEXT: s_waitcnt vmcnt(0)383; FLATSCR-NEXT: ;;#ASMSTART384; FLATSCR-NEXT: ; v[0:1]385; FLATSCR-NEXT: ;;#ASMEND386; FLATSCR-NEXT: s_endpgm387entry:388 ; Occupy 4092 bytes of scratch, so that the spill of the last subreg of %a389 ; does not fit below offset 4096 (4092 + 8 - 4 = 4096), and has to live390 ; in the SGPR offset.391 %alloca = alloca i8, i32 4088, align 4, addrspace(5)392 393 ; 0x3ff00 / 64 = 4092 (for wave64)394 %aptr = getelementptr <2 x i32>, ptr addrspace(5) %alloca, i32 1395 %a = load volatile <2 x i32>, ptr addrspace(5) %aptr396 397 ; Force %a to spill.398 call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7}" ()399 400 ; Ensure the alloca sticks around.401 %bptr = getelementptr i32, ptr addrspace(5) %alloca, i32 1402 %b = load volatile i32, ptr addrspace(5) %bptr403 404 ; Ensure the spill is of the full super-reg.405 call void asm sideeffect "; $0", "r"(<2 x i32> %a)406 407 ret void408}409 410define void @test_inst_offset_function() {411; MUBUF-LABEL: test_inst_offset_function:412; MUBUF: ; %bb.0: ; %entry413; MUBUF-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)414; MUBUF-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:4 glc415; MUBUF-NEXT: s_waitcnt vmcnt(0)416; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:4088 ; 4-byte Folded Spill417; MUBUF-NEXT: ;;#ASMSTART418; MUBUF-NEXT: ;;#ASMEND419; MUBUF-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:4088 ; 4-byte Folded Reload420; MUBUF-NEXT: s_waitcnt vmcnt(0)421; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:4422; MUBUF-NEXT: s_waitcnt vmcnt(0)423; MUBUF-NEXT: s_setpc_b64 s[30:31]424;425; FLATSCR-LABEL: test_inst_offset_function:426; FLATSCR: ; %bb.0: ; %entry427; FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)428; FLATSCR-NEXT: scratch_load_dword v0, off, s32 offset:4 glc429; FLATSCR-NEXT: s_waitcnt vmcnt(0)430; FLATSCR-NEXT: scratch_store_dword off, v0, s32 offset:4088 ; 4-byte Folded Spill431; FLATSCR-NEXT: ;;#ASMSTART432; FLATSCR-NEXT: ;;#ASMEND433; FLATSCR-NEXT: scratch_load_dword v0, off, s32 offset:4088 ; 4-byte Folded Reload434; FLATSCR-NEXT: s_waitcnt vmcnt(0)435; FLATSCR-NEXT: scratch_store_dword off, v0, s32 offset:4436; FLATSCR-NEXT: s_waitcnt vmcnt(0)437; FLATSCR-NEXT: s_setpc_b64 s[30:31]438entry:439 ; Occupy enough bytes of scratch, so the offset of the spill of %a440 ; just fits in the instruction offset field when the emergency stack441 ; slot is added. It's hard to hit the actual limit since we're also442 ; going to insert the emergency stack slot for large frames.443 %alloca = alloca i8, i32 4088, align 4, addrspace(5)444 445 %aptr = getelementptr i32, ptr addrspace(5) %alloca, i32 1446 447 448 %a = load volatile i32, ptr addrspace(5) %aptr449 450 ; Force %a to spill.451 call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7}" ()452 453 %outptr = getelementptr i32, ptr addrspace(5) %alloca, i32 1454 store volatile i32 %a, ptr addrspace(5) %outptr455 456 ret void457}458 459define void @test_sgpr_offset_function() {460; MUBUF-LABEL: test_sgpr_offset_function:461; MUBUF: ; %bb.0: ; %entry462; MUBUF-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)463; MUBUF-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:8 glc464; MUBUF-NEXT: s_waitcnt vmcnt(0)465; MUBUF-NEXT: s_add_i32 s4, s32, 0x40100466; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], s4 ; 4-byte Folded Spill467; MUBUF-NEXT: ;;#ASMSTART468; MUBUF-NEXT: ;;#ASMEND469; MUBUF-NEXT: s_add_i32 s4, s32, 0x40100470; MUBUF-NEXT: buffer_load_dword v0, off, s[0:3], s4 ; 4-byte Folded Reload471; MUBUF-NEXT: s_waitcnt vmcnt(0)472; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:8473; MUBUF-NEXT: s_waitcnt vmcnt(0)474; MUBUF-NEXT: s_setpc_b64 s[30:31]475;476; FLATSCR-LABEL: test_sgpr_offset_function:477; FLATSCR: ; %bb.0: ; %entry478; FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)479; FLATSCR-NEXT: scratch_load_dword v0, off, s32 offset:8 glc480; FLATSCR-NEXT: s_waitcnt vmcnt(0)481; FLATSCR-NEXT: s_add_i32 s0, s32, 0x1004482; FLATSCR-NEXT: scratch_store_dword off, v0, s0 ; 4-byte Folded Spill483; FLATSCR-NEXT: ;;#ASMSTART484; FLATSCR-NEXT: ;;#ASMEND485; FLATSCR-NEXT: s_add_i32 s0, s32, 0x1004486; FLATSCR-NEXT: scratch_load_dword v0, off, s0 ; 4-byte Folded Reload487; FLATSCR-NEXT: s_waitcnt vmcnt(0)488; FLATSCR-NEXT: scratch_store_dword off, v0, s32 offset:8489; FLATSCR-NEXT: s_waitcnt vmcnt(0)490; FLATSCR-NEXT: s_setpc_b64 s[30:31]491entry:492 ; Occupy 4096 bytes of scratch, so the offset of the spill of %a does not493 ; fit in the instruction, and has to live in the SGPR offset.494 %alloca = alloca i8, i32 4096, align 4, addrspace(5)495 496 %aptr = getelementptr i32, ptr addrspace(5) %alloca, i32 1497 ; 0x40000 / 64 = 4096 (for wave64)498 %a = load volatile i32, ptr addrspace(5) %aptr499 500 ; Force %a to spill501 call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7}" ()502 503 %outptr = getelementptr i32, ptr addrspace(5) %alloca, i32 1504 store volatile i32 %a, ptr addrspace(5) %outptr505 506 ret void507}508 509define void @test_sgpr_offset_subregs_function() {510; MUBUF-LABEL: test_sgpr_offset_subregs_function:511; MUBUF: ; %bb.0: ; %entry512; MUBUF-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)513; MUBUF-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:8 glc514; MUBUF-NEXT: s_waitcnt vmcnt(0)515; MUBUF-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:12 glc516; MUBUF-NEXT: s_waitcnt vmcnt(0)517; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:4084 ; 4-byte Folded Spill518; MUBUF-NEXT: s_nop 0519; MUBUF-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:4088 ; 4-byte Folded Spill520; MUBUF-NEXT: ;;#ASMSTART521; MUBUF-NEXT: ;;#ASMEND522; MUBUF-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:4 glc523; MUBUF-NEXT: s_waitcnt vmcnt(0)524; MUBUF-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:4084 ; 4-byte Folded Reload525; MUBUF-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:4088 ; 4-byte Folded Reload526; MUBUF-NEXT: s_waitcnt vmcnt(0)527; MUBUF-NEXT: ;;#ASMSTART528; MUBUF-NEXT: ; v[0:1]529; MUBUF-NEXT: ;;#ASMEND530; MUBUF-NEXT: s_setpc_b64 s[30:31]531;532; FLATSCR-LABEL: test_sgpr_offset_subregs_function:533; FLATSCR: ; %bb.0: ; %entry534; FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)535; FLATSCR-NEXT: scratch_load_dwordx2 v[0:1], off, s32 offset:8 glc536; FLATSCR-NEXT: s_waitcnt vmcnt(0)537; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], s32 offset:4084 ; 8-byte Folded Spill538; FLATSCR-NEXT: ;;#ASMSTART539; FLATSCR-NEXT: ;;#ASMEND540; FLATSCR-NEXT: scratch_load_dword v0, off, s32 offset:4 glc541; FLATSCR-NEXT: s_waitcnt vmcnt(0)542; FLATSCR-NEXT: scratch_load_dwordx2 v[0:1], off, s32 offset:4084 ; 8-byte Folded Reload543; FLATSCR-NEXT: s_waitcnt vmcnt(0)544; FLATSCR-NEXT: ;;#ASMSTART545; FLATSCR-NEXT: ; v[0:1]546; FLATSCR-NEXT: ;;#ASMEND547; FLATSCR-NEXT: s_setpc_b64 s[30:31]548entry:549 ; We want to test the spill of the last subreg of %a is the highest550 ; valid value for the immediate offset. We enable the emergency551 ; stack slot for large frames, so it's hard to get the frame layout552 ; exactly as we want to test it.553 ; Occupy 4084 bytes of scratch, so that the spill of the last subreg of %a554 ; still fits below offset 4096 (4084 + 8 - 4 = 4092), and can be placed in555 ; the instruction offset field.556 %alloca = alloca i8, i32 4084, align 4, addrspace(5)557 %aptr = getelementptr <2 x i32>, ptr addrspace(5) %alloca, i32 1558 %a = load volatile <2 x i32>, ptr addrspace(5) %aptr559 560 ; Force %a to spill.561 call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7}" ()562 563 ; Ensure the alloca sticks around.564 %bptr = getelementptr i32, ptr addrspace(5) %alloca, i32 1565 %b = load volatile i32, ptr addrspace(5) %bptr566 567 ; Ensure the spill is of the full super-reg.568 call void asm sideeffect "; $0", "r"(<2 x i32> %a)569 570 ret void571}572 573define void @test_inst_offset_subregs_function() {574; MUBUF-LABEL: test_inst_offset_subregs_function:575; MUBUF: ; %bb.0: ; %entry576; MUBUF-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)577; MUBUF-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:12 glc578; MUBUF-NEXT: s_waitcnt vmcnt(0)579; MUBUF-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:16 glc580; MUBUF-NEXT: s_waitcnt vmcnt(0)581; MUBUF-NEXT: s_add_i32 s4, s32, 0x3ff00582; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], s4 ; 4-byte Folded Spill583; MUBUF-NEXT: s_nop 0584; MUBUF-NEXT: buffer_store_dword v1, off, s[0:3], s4 offset:4 ; 4-byte Folded Spill585; MUBUF-NEXT: ;;#ASMSTART586; MUBUF-NEXT: ;;#ASMEND587; MUBUF-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:8 glc588; MUBUF-NEXT: s_waitcnt vmcnt(0)589; MUBUF-NEXT: s_add_i32 s4, s32, 0x3ff00590; MUBUF-NEXT: buffer_load_dword v0, off, s[0:3], s4 ; 4-byte Folded Reload591; MUBUF-NEXT: buffer_load_dword v1, off, s[0:3], s4 offset:4 ; 4-byte Folded Reload592; MUBUF-NEXT: s_waitcnt vmcnt(0)593; MUBUF-NEXT: ;;#ASMSTART594; MUBUF-NEXT: ; v[0:1]595; MUBUF-NEXT: ;;#ASMEND596; MUBUF-NEXT: s_setpc_b64 s[30:31]597;598; FLATSCR-LABEL: test_inst_offset_subregs_function:599; FLATSCR: ; %bb.0: ; %entry600; FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)601; FLATSCR-NEXT: scratch_load_dwordx2 v[0:1], off, s32 offset:12 glc602; FLATSCR-NEXT: s_waitcnt vmcnt(0)603; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], s32 offset:4092 ; 8-byte Folded Spill604; FLATSCR-NEXT: ;;#ASMSTART605; FLATSCR-NEXT: ;;#ASMEND606; FLATSCR-NEXT: scratch_load_dword v0, off, s32 offset:8 glc607; FLATSCR-NEXT: s_waitcnt vmcnt(0)608; FLATSCR-NEXT: scratch_load_dwordx2 v[0:1], off, s32 offset:4092 ; 8-byte Folded Reload609; FLATSCR-NEXT: s_waitcnt vmcnt(0)610; FLATSCR-NEXT: ;;#ASMSTART611; FLATSCR-NEXT: ; v[0:1]612; FLATSCR-NEXT: ;;#ASMEND613; FLATSCR-NEXT: s_setpc_b64 s[30:31]614entry:615 ; Occupy 4088 bytes of scratch, so that the spill of the last subreg of %a616 ; does not fit below offset 4096 (408 + 4 + 8 - 4 = 4096), and has to live617 ; in the SGPR offset.618 %alloca = alloca i8, i32 4088, align 4, addrspace(5)619 620 ; 0x3ff0000 / 64 = 4092 (for wave64)621 %aptr = getelementptr <2 x i32>, ptr addrspace(5) %alloca, i32 1622 %a = load volatile <2 x i32>, ptr addrspace(5) %aptr623 624 ; Force %a to spill.625 call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7}" ()626 627 ; Ensure the alloca sticks around.628 %bptr = getelementptr i32, ptr addrspace(5) %alloca, i32 1629 %b = load volatile i32, ptr addrspace(5) %bptr630 631 ; Ensure the spill is of the full super-reg.632 call void asm sideeffect "; $0", "r"(<2 x i32> %a)633 634 ret void635}636 637attributes #0 = { nounwind }638attributes #1 = { nounwind "amdgpu-num-sgpr"="17" "amdgpu-num-vgpr"="8" }639attributes #2 = { nounwind "amdgpu-num-sgpr"="16" "amdgpu-num-vgpr"="8" }640attributes #3 = { nounwind "amdgpu-num-sgpr"="18" "amdgpu-num-vgpr"="8" }641